1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_DP_TYPES_H 27 #define DC_DP_TYPES_H 28 29 #include "os_types.h" 30 #include "dc_ddc_types.h" 31 32 enum dc_lane_count { 33 LANE_COUNT_UNKNOWN = 0, 34 LANE_COUNT_ONE = 1, 35 LANE_COUNT_TWO = 2, 36 LANE_COUNT_FOUR = 4, 37 LANE_COUNT_EIGHT = 8, 38 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR 39 }; 40 41 /* This is actually a reference clock (27MHz) multiplier 42 * 162MBps bandwidth for 1.62GHz like rate, 43 * 270MBps for 2.70GHz, 44 * 324MBps for 3.24Ghz, 45 * 540MBps for 5.40GHz 46 * 810MBps for 8.10GHz 47 */ 48 enum dc_link_rate { 49 LINK_RATE_UNKNOWN = 0, 50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane 51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane 54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane 55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane 57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane 58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane 59 /* Starting from DP2.0 link rate enum directly represents actual 60 * link rate value in unit of 10 mbps 61 */ 62 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane 63 LINK_RATE_UHBR13_5 = 1350, // UHBR13.5 - 13.5 Gbps/Lane 64 LINK_RATE_UHBR20 = 2000, // UHBR20 - 20.0 Gbps/Lane 65 }; 66 67 enum dc_link_spread { 68 LINK_SPREAD_DISABLED = 0x00, 69 /* 0.5 % downspread 30 kHz */ 70 LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, 71 /* 0.5 % downspread 33 kHz */ 72 LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 73 }; 74 75 enum dc_voltage_swing { 76 VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ 77 VOLTAGE_SWING_LEVEL1, 78 VOLTAGE_SWING_LEVEL2, 79 VOLTAGE_SWING_LEVEL3, 80 VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 81 }; 82 83 enum dc_pre_emphasis { 84 PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ 85 PRE_EMPHASIS_LEVEL1, 86 PRE_EMPHASIS_LEVEL2, 87 PRE_EMPHASIS_LEVEL3, 88 PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 89 }; 90 /* Post Cursor 2 is optional for transmitter 91 * and it applies only to the main link operating at HBR2 92 */ 93 enum dc_post_cursor2 { 94 POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ 95 POST_CURSOR2_LEVEL1, 96 POST_CURSOR2_LEVEL2, 97 POST_CURSOR2_LEVEL3, 98 POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, 99 }; 100 101 enum dc_dp_ffe_preset_level { 102 DP_FFE_PRESET_LEVEL0 = 0, 103 DP_FFE_PRESET_LEVEL1, 104 DP_FFE_PRESET_LEVEL2, 105 DP_FFE_PRESET_LEVEL3, 106 DP_FFE_PRESET_LEVEL4, 107 DP_FFE_PRESET_LEVEL5, 108 DP_FFE_PRESET_LEVEL6, 109 DP_FFE_PRESET_LEVEL7, 110 DP_FFE_PRESET_LEVEL8, 111 DP_FFE_PRESET_LEVEL9, 112 DP_FFE_PRESET_LEVEL10, 113 DP_FFE_PRESET_LEVEL11, 114 DP_FFE_PRESET_LEVEL12, 115 DP_FFE_PRESET_LEVEL13, 116 DP_FFE_PRESET_LEVEL14, 117 DP_FFE_PRESET_LEVEL15, 118 DP_FFE_PRESET_MAX_LEVEL = DP_FFE_PRESET_LEVEL15, 119 }; 120 121 enum dc_dp_training_pattern { 122 DP_TRAINING_PATTERN_SEQUENCE_1 = 0, 123 DP_TRAINING_PATTERN_SEQUENCE_2, 124 DP_TRAINING_PATTERN_SEQUENCE_3, 125 DP_TRAINING_PATTERN_SEQUENCE_4, 126 DP_TRAINING_PATTERN_VIDEOIDLE, 127 DP_128b_132b_TPS1, 128 DP_128b_132b_TPS2, 129 DP_128b_132b_TPS2_CDS, 130 }; 131 132 enum dp_link_encoding { 133 DP_UNKNOWN_ENCODING = 0, 134 DP_8b_10b_ENCODING = 1, 135 DP_128b_132b_ENCODING = 2, 136 }; 137 138 enum dp_test_link_rate { 139 DP_TEST_LINK_RATE_RBR = 0x06, 140 DP_TEST_LINK_RATE_HBR = 0x0A, 141 DP_TEST_LINK_RATE_HBR2 = 0x14, 142 DP_TEST_LINK_RATE_HBR3 = 0x1E, 143 DP_TEST_LINK_RATE_UHBR10 = 0x01, 144 DP_TEST_LINK_RATE_UHBR20 = 0x02, 145 DP_TEST_LINK_RATE_UHBR13_5_LEGACY = 0x03, /* For backward compatibility*/ 146 DP_TEST_LINK_RATE_UHBR13_5 = 0x04, 147 }; 148 149 struct dc_link_settings { 150 enum dc_lane_count lane_count; 151 enum dc_link_rate link_rate; 152 enum dc_link_spread link_spread; 153 bool use_link_rate_set; 154 uint8_t link_rate_set; 155 }; 156 157 union dc_dp_ffe_preset { 158 struct { 159 uint8_t level : 4; 160 uint8_t reserved : 1; 161 uint8_t no_preshoot : 1; 162 uint8_t no_deemphasis : 1; 163 uint8_t method2 : 1; 164 } settings; 165 uint8_t raw; 166 }; 167 168 struct dc_lane_settings { 169 enum dc_voltage_swing VOLTAGE_SWING; 170 enum dc_pre_emphasis PRE_EMPHASIS; 171 enum dc_post_cursor2 POST_CURSOR2; 172 union dc_dp_ffe_preset FFE_PRESET; 173 }; 174 175 struct dc_link_training_overrides { 176 enum dc_voltage_swing *voltage_swing; 177 enum dc_pre_emphasis *pre_emphasis; 178 enum dc_post_cursor2 *post_cursor2; 179 union dc_dp_ffe_preset *ffe_preset; 180 181 uint16_t *cr_pattern_time; 182 uint16_t *eq_pattern_time; 183 enum dc_dp_training_pattern *pattern_for_cr; 184 enum dc_dp_training_pattern *pattern_for_eq; 185 186 enum dc_link_spread *downspread; 187 bool *alternate_scrambler_reset; 188 bool *enhanced_framing; 189 bool *mst_enable; 190 bool *fec_enable; 191 }; 192 193 union payload_table_update_status { 194 struct { 195 uint8_t VC_PAYLOAD_TABLE_UPDATED:1; 196 uint8_t ACT_HANDLED:1; 197 } bits; 198 uint8_t raw; 199 }; 200 201 union dpcd_rev { 202 struct { 203 uint8_t MINOR:4; 204 uint8_t MAJOR:4; 205 } bits; 206 uint8_t raw; 207 }; 208 209 union max_lane_count { 210 struct { 211 uint8_t MAX_LANE_COUNT:5; 212 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1; 213 uint8_t TPS3_SUPPORTED:1; 214 uint8_t ENHANCED_FRAME_CAP:1; 215 } bits; 216 uint8_t raw; 217 }; 218 219 union max_down_spread { 220 struct { 221 uint8_t MAX_DOWN_SPREAD:1; 222 uint8_t RESERVED:5; 223 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1; 224 uint8_t TPS4_SUPPORTED:1; 225 } bits; 226 uint8_t raw; 227 }; 228 229 union mstm_cap { 230 struct { 231 uint8_t MST_CAP:1; 232 uint8_t RESERVED:7; 233 } bits; 234 uint8_t raw; 235 }; 236 237 union lane_count_set { 238 struct { 239 uint8_t LANE_COUNT_SET:5; 240 uint8_t POST_LT_ADJ_REQ_GRANTED:1; 241 uint8_t RESERVED:1; 242 uint8_t ENHANCED_FRAMING:1; 243 } bits; 244 uint8_t raw; 245 }; 246 247 union lane_status { 248 struct { 249 uint8_t CR_DONE_0:1; 250 uint8_t CHANNEL_EQ_DONE_0:1; 251 uint8_t SYMBOL_LOCKED_0:1; 252 uint8_t RESERVED0:1; 253 uint8_t CR_DONE_1:1; 254 uint8_t CHANNEL_EQ_DONE_1:1; 255 uint8_t SYMBOL_LOCKED_1:1; 256 uint8_t RESERVED_1:1; 257 } bits; 258 uint8_t raw; 259 }; 260 261 union device_service_irq { 262 struct { 263 uint8_t REMOTE_CONTROL_CMD_PENDING:1; 264 uint8_t AUTOMATED_TEST:1; 265 uint8_t CP_IRQ:1; 266 uint8_t MCCS_IRQ:1; 267 uint8_t DOWN_REP_MSG_RDY:1; 268 uint8_t UP_REQ_MSG_RDY:1; 269 uint8_t SINK_SPECIFIC:1; 270 uint8_t reserved:1; 271 } bits; 272 uint8_t raw; 273 }; 274 275 union sink_count { 276 struct { 277 uint8_t SINK_COUNT:6; 278 uint8_t CPREADY:1; 279 uint8_t RESERVED:1; 280 } bits; 281 uint8_t raw; 282 }; 283 284 union lane_align_status_updated { 285 struct { 286 uint8_t INTERLANE_ALIGN_DONE:1; 287 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1; 288 uint8_t EQ_INTERLANE_ALIGN_DONE_128b_132b:1; 289 uint8_t CDS_INTERLANE_ALIGN_DONE_128b_132b:1; 290 uint8_t LT_FAILED_128b_132b:1; 291 uint8_t RESERVED:1; 292 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1; 293 uint8_t LINK_STATUS_UPDATED:1; 294 } bits; 295 uint8_t raw; 296 }; 297 298 union lane_adjust { 299 struct { 300 uint8_t VOLTAGE_SWING_LANE:2; 301 uint8_t PRE_EMPHASIS_LANE:2; 302 uint8_t RESERVED:4; 303 } bits; 304 struct { 305 uint8_t PRESET_VALUE :4; 306 uint8_t RESERVED :4; 307 } tx_ffe; 308 uint8_t raw; 309 }; 310 311 union dpcd_training_pattern { 312 struct { 313 uint8_t TRAINING_PATTERN_SET:4; 314 uint8_t RECOVERED_CLOCK_OUT_EN:1; 315 uint8_t SCRAMBLING_DISABLE:1; 316 uint8_t SYMBOL_ERROR_COUNT_SEL:2; 317 } v1_4; 318 struct { 319 uint8_t TRAINING_PATTERN_SET:2; 320 uint8_t LINK_QUAL_PATTERN_SET:2; 321 uint8_t RESERVED:4; 322 } v1_3; 323 uint8_t raw; 324 }; 325 326 /* Training Lane is used to configure downstream DP device's voltage swing 327 and pre-emphasis levels*/ 328 /* The DPCD addresses are from 0x103 to 0x106*/ 329 union dpcd_training_lane { 330 struct { 331 uint8_t VOLTAGE_SWING_SET:2; 332 uint8_t MAX_SWING_REACHED:1; 333 uint8_t PRE_EMPHASIS_SET:2; 334 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 335 uint8_t RESERVED:2; 336 } bits; 337 struct { 338 uint8_t PRESET_VALUE :4; 339 uint8_t RESERVED :4; 340 } tx_ffe; 341 uint8_t raw; 342 }; 343 344 /* TMDS-converter related */ 345 union dwnstream_port_caps_byte0 { 346 struct { 347 uint8_t DWN_STRM_PORTX_TYPE:3; 348 uint8_t DWN_STRM_PORTX_HPD:1; 349 uint8_t RESERVERD:4; 350 } bits; 351 uint8_t raw; 352 }; 353 354 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/ 355 enum dpcd_downstream_port_detailed_type { 356 DOWN_STREAM_DETAILED_DP = 0, 357 DOWN_STREAM_DETAILED_VGA, 358 DOWN_STREAM_DETAILED_DVI, 359 DOWN_STREAM_DETAILED_HDMI, 360 DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/ 361 DOWN_STREAM_DETAILED_DP_PLUS_PLUS 362 }; 363 364 union dwnstream_port_caps_byte2 { 365 struct { 366 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; 367 uint8_t MAX_ENCODED_LINK_BW_SUPPORT:3; 368 uint8_t SOURCE_CONTROL_MODE_SUPPORT:1; 369 uint8_t CONCURRENT_LINK_BRING_UP_SEQ_SUPPORT:1; 370 uint8_t RESERVED:1; 371 } bits; 372 uint8_t raw; 373 }; 374 375 union dp_downstream_port_present { 376 uint8_t byte; 377 struct { 378 uint8_t PORT_PRESENT:1; 379 uint8_t PORT_TYPE:2; 380 uint8_t FMT_CONVERSION:1; 381 uint8_t DETAILED_CAPS:1; 382 uint8_t RESERVED:3; 383 } fields; 384 }; 385 386 union dwnstream_port_caps_byte3_dvi { 387 struct { 388 uint8_t RESERVED1:1; 389 uint8_t DUAL_LINK:1; 390 uint8_t HIGH_COLOR_DEPTH:1; 391 uint8_t RESERVED2:5; 392 } bits; 393 uint8_t raw; 394 }; 395 396 union dwnstream_port_caps_byte3_hdmi { 397 struct { 398 uint8_t FRAME_SEQ_TO_FRAME_PACK:1; 399 uint8_t YCrCr422_PASS_THROUGH:1; 400 uint8_t YCrCr420_PASS_THROUGH:1; 401 uint8_t YCrCr422_CONVERSION:1; 402 uint8_t YCrCr420_CONVERSION:1; 403 uint8_t RESERVED:3; 404 } bits; 405 uint8_t raw; 406 }; 407 408 union hdmi_sink_encoded_link_bw_support { 409 struct { 410 uint8_t HDMI_SINK_ENCODED_LINK_BW_SUPPORT:3; 411 uint8_t RESERVED:5; 412 } bits; 413 uint8_t raw; 414 }; 415 416 union hdmi_encoded_link_bw { 417 struct { 418 uint8_t FRL_MODE:1; // Bit 0 419 uint8_t BW_9Gbps:1; 420 uint8_t BW_18Gbps:1; 421 uint8_t BW_24Gbps:1; 422 uint8_t BW_32Gbps:1; 423 uint8_t BW_40Gbps:1; 424 uint8_t BW_48Gbps:1; 425 uint8_t RESERVED:1; // Bit 7 426 } bits; 427 uint8_t raw; 428 }; 429 430 /*4-byte structure for detailed capabilities of a down-stream port 431 (DP-to-TMDS converter).*/ 432 union dwnstream_portxcaps { 433 struct { 434 union dwnstream_port_caps_byte0 byte0; 435 unsigned char max_TMDS_clock; //byte1 436 union dwnstream_port_caps_byte2 byte2; 437 438 union { 439 union dwnstream_port_caps_byte3_dvi byteDVI; 440 union dwnstream_port_caps_byte3_hdmi byteHDMI; 441 } byte3; 442 } bytes; 443 444 unsigned char raw[4]; 445 }; 446 447 union downstream_port { 448 struct { 449 unsigned char present:1; 450 unsigned char type:2; 451 unsigned char format_conv:1; 452 unsigned char detailed_caps:1; 453 unsigned char reserved:3; 454 } bits; 455 unsigned char raw; 456 }; 457 458 459 union sink_status { 460 struct { 461 uint8_t RX_PORT0_STATUS:1; 462 uint8_t RX_PORT1_STATUS:1; 463 uint8_t RESERVED:6; 464 } bits; 465 uint8_t raw; 466 }; 467 468 /*6-byte structure corresponding to 6 registers (200h-205h) 469 read during handling of HPD-IRQ*/ 470 union hpd_irq_data { 471 struct { 472 union sink_count sink_cnt;/* 200h */ 473 union device_service_irq device_service_irq;/* 201h */ 474 union lane_status lane01_status;/* 202h */ 475 union lane_status lane23_status;/* 203h */ 476 union lane_align_status_updated lane_status_updated;/* 204h */ 477 union sink_status sink_status; 478 } bytes; 479 uint8_t raw[6]; 480 }; 481 482 union down_stream_port_count { 483 struct { 484 uint8_t DOWN_STR_PORT_COUNT:4; 485 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/ 486 /*Bit 6 = MSA_TIMING_PAR_IGNORED 487 0 = Sink device requires the MSA timing parameters 488 1 = Sink device is capable of rendering incoming video 489 stream without MSA timing parameters*/ 490 uint8_t IGNORE_MSA_TIMING_PARAM:1; 491 /*Bit 7 = OUI Support 492 0 = OUI not supported 493 1 = OUI supported 494 (OUI and Device Identification mandatory for DP 1.2)*/ 495 uint8_t OUI_SUPPORT:1; 496 } bits; 497 uint8_t raw; 498 }; 499 500 union down_spread_ctrl { 501 struct { 502 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/ 503 /* Bits 4 = SPREAD_AMP. Spreading amplitude 504 0 = Main link signal is not downspread 505 1 = Main link signal is downspread <= 0.5% 506 with frequency in the range of 30kHz ~ 33kHz*/ 507 uint8_t SPREAD_AMP:1; 508 uint8_t RESERVED2:1;/*Bit 5 = RESERVED. Read all 0s*/ 509 /* Bit 6 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE. 510 0 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is not enabled by the Source device (default) 511 1 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is enabled by Source device */ 512 uint8_t FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE:1; 513 /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN 514 0 = Source device will send valid data for the MSA Timing Params 515 1 = Source device may send invalid data for these MSA Timing Params*/ 516 uint8_t IGNORE_MSA_TIMING_PARAM:1; 517 } bits; 518 uint8_t raw; 519 }; 520 521 union dpcd_edp_config { 522 struct { 523 uint8_t PANEL_MODE_EDP:1; 524 uint8_t FRAMING_CHANGE_ENABLE:1; 525 uint8_t RESERVED:5; 526 uint8_t PANEL_SELF_TEST_ENABLE:1; 527 } bits; 528 uint8_t raw; 529 }; 530 531 struct dp_device_vendor_id { 532 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 533 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 534 }; 535 536 struct dp_sink_hw_fw_revision { 537 uint8_t ieee_hw_rev; 538 uint8_t ieee_fw_rev[2]; 539 }; 540 541 struct dpcd_vendor_signature { 542 bool is_valid; 543 544 union dpcd_ieee_vendor_signature { 545 struct { 546 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 547 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 548 uint8_t ieee_hw_rev; 549 uint8_t ieee_fw_rev[2]; 550 }; 551 uint8_t raw[12]; 552 } data; 553 }; 554 555 struct dpcd_amd_signature { 556 uint8_t AMD_IEEE_TxSignature_byte1; 557 uint8_t AMD_IEEE_TxSignature_byte2; 558 uint8_t AMD_IEEE_TxSignature_byte3; 559 }; 560 561 struct dpcd_amd_device_id { 562 uint8_t device_id_byte1; 563 uint8_t device_id_byte2; 564 uint8_t zero[4]; 565 uint8_t dce_version; 566 uint8_t dal_version_byte1; 567 uint8_t dal_version_byte2; 568 }; 569 570 struct target_luminance_value { 571 uint8_t byte0; 572 uint8_t byte1; 573 uint8_t byte2; 574 }; 575 576 struct dpcd_source_backlight_set { 577 struct { 578 uint8_t byte0; 579 uint8_t byte1; 580 uint8_t byte2; 581 uint8_t byte3; 582 } backlight_level_millinits; 583 584 struct { 585 uint8_t byte0; 586 uint8_t byte1; 587 } backlight_transition_time_ms; 588 }; 589 590 union dpcd_source_backlight_get { 591 struct { 592 uint32_t backlight_millinits_peak; /* 326h */ 593 uint32_t backlight_millinits_avg; /* 32Ah */ 594 } bytes; 595 uint8_t raw[8]; 596 }; 597 598 /*DPCD register of DP receiver capability field bits-*/ 599 union edp_configuration_cap { 600 struct { 601 uint8_t ALT_SCRAMBLER_RESET:1; 602 uint8_t FRAMING_CHANGE:1; 603 uint8_t RESERVED:1; 604 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1; 605 uint8_t RESERVED2:4; 606 } bits; 607 uint8_t raw; 608 }; 609 610 union dprx_feature { 611 struct { 612 uint8_t GTC_CAP:1; // bit 0: DP 1.3+ 613 uint8_t SST_SPLIT_SDP_CAP:1; // bit 1: DP 1.4 614 uint8_t AV_SYNC_CAP:1; // bit 2: DP 1.3+ 615 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1; // bit 3: DP 1.3+ 616 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1; // bit 4: DP 1.4 617 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4 618 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1; // bit 6: DP 1.4 619 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1; // bit 7: DP 1.4 620 } bits; 621 uint8_t raw; 622 }; 623 624 union training_aux_rd_interval { 625 struct { 626 uint8_t TRAINIG_AUX_RD_INTERVAL:7; 627 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1; 628 } bits; 629 uint8_t raw; 630 }; 631 632 /* Automated test structures */ 633 union test_request { 634 struct { 635 uint8_t LINK_TRAINING :1; 636 uint8_t LINK_TEST_PATTRN :1; 637 uint8_t EDID_READ :1; 638 uint8_t PHY_TEST_PATTERN :1; 639 uint8_t PHY_TEST_CHANNEL_CODING_TYPE :2; 640 uint8_t AUDIO_TEST_PATTERN :1; 641 uint8_t TEST_AUDIO_DISABLED_VIDEO :1; 642 } bits; 643 uint8_t raw; 644 }; 645 646 union test_response { 647 struct { 648 uint8_t ACK :1; 649 uint8_t NO_ACK :1; 650 uint8_t EDID_CHECKSUM_WRITE:1; 651 uint8_t RESERVED :5; 652 } bits; 653 uint8_t raw; 654 }; 655 656 union phy_test_pattern { 657 struct { 658 /* This field is 7 bits for DP2.0 */ 659 uint8_t PATTERN :7; 660 uint8_t RESERVED :1; 661 } bits; 662 uint8_t raw; 663 }; 664 665 /* States of Compliance Test Specification (CTS DP1.2). */ 666 union compliance_test_state { 667 struct { 668 unsigned char STEREO_3D_RUNNING : 1; 669 unsigned char RESERVED : 7; 670 } bits; 671 unsigned char raw; 672 }; 673 674 union link_test_pattern { 675 struct { 676 /* dpcd_link_test_patterns */ 677 unsigned char PATTERN :2; 678 unsigned char RESERVED:6; 679 } bits; 680 unsigned char raw; 681 }; 682 683 union test_misc { 684 struct dpcd_test_misc_bits { 685 unsigned char SYNC_CLOCK :1; 686 /* dpcd_test_color_format */ 687 unsigned char CLR_FORMAT :2; 688 /* dpcd_test_dyn_range */ 689 unsigned char DYN_RANGE :1; 690 unsigned char YCBCR_COEFS :1; 691 /* dpcd_test_bit_depth */ 692 unsigned char BPC :3; 693 } bits; 694 unsigned char raw; 695 }; 696 697 union audio_test_mode { 698 struct { 699 unsigned char sampling_rate :4; 700 unsigned char channel_count :4; 701 } bits; 702 unsigned char raw; 703 }; 704 705 union audio_test_pattern_period { 706 struct { 707 unsigned char pattern_period :4; 708 unsigned char reserved :4; 709 } bits; 710 unsigned char raw; 711 }; 712 713 struct audio_test_pattern_type { 714 unsigned char value; 715 }; 716 717 struct dp_audio_test_data_flags { 718 uint8_t test_requested :1; 719 uint8_t disable_video :1; 720 }; 721 722 struct dp_audio_test_data { 723 724 struct dp_audio_test_data_flags flags; 725 uint8_t sampling_rate; 726 uint8_t channel_count; 727 uint8_t pattern_type; 728 uint8_t pattern_period[8]; 729 }; 730 731 /* FEC capability DPCD register field bits-*/ 732 union dpcd_fec_capability { 733 struct { 734 uint8_t FEC_CAPABLE:1; 735 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 736 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 737 uint8_t BIT_ERROR_COUNT_CAPABLE:1; 738 uint8_t PARITY_BLOCK_ERROR_COUNT_CAPABLE:1; 739 uint8_t ARITY_BIT_ERROR_COUNT_CAPABLE:1; 740 uint8_t FEC_RUNNING_INDICATOR_SUPPORTED:1; 741 uint8_t FEC_ERROR_REPORTING_POLICY_SUPPORTED:1; 742 } bits; 743 uint8_t raw; 744 }; 745 746 /* DSC capability DPCD register field bits-*/ 747 struct dpcd_dsc_support { 748 uint8_t DSC_SUPPORT :1; 749 uint8_t DSC_PASSTHROUGH_SUPPORT :1; 750 uint8_t RESERVED :6; 751 }; 752 753 struct dpcd_dsc_algorithm_revision { 754 uint8_t DSC_VERSION_MAJOR :4; 755 uint8_t DSC_VERSION_MINOR :4; 756 }; 757 758 struct dpcd_dsc_rc_buffer_block_size { 759 uint8_t RC_BLOCK_BUFFER_SIZE :2; 760 uint8_t RESERVED :6; 761 }; 762 763 struct dpcd_dsc_slice_capability1 { 764 uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1; 765 uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1; 766 uint8_t RESERVED :1; 767 uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1; 768 uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1; 769 uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1; 770 uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1; 771 uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1; 772 }; 773 774 struct dpcd_dsc_line_buffer_bit_depth { 775 uint8_t LINE_BUFFER_BIT_DEPTH :4; 776 uint8_t RESERVED :4; 777 }; 778 779 struct dpcd_dsc_block_prediction_support { 780 uint8_t BLOCK_PREDICTION_SUPPORT:1; 781 uint8_t RESERVED :7; 782 }; 783 784 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor { 785 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7; 786 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7; 787 uint8_t RESERVED :2; 788 }; 789 790 struct dpcd_dsc_decoder_color_format_capabilities { 791 uint8_t RGB_SUPPORT :1; 792 uint8_t Y_CB_CR_444_SUPPORT :1; 793 uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1; 794 uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1; 795 uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1; 796 uint8_t RESERVED :3; 797 }; 798 799 struct dpcd_dsc_decoder_color_depth_capabilities { 800 uint8_t RESERVED0 :1; 801 uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1; 802 uint8_t TEN_BITS_PER_COLOR_SUPPORT :1; 803 uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1; 804 uint8_t RESERVED1 :4; 805 }; 806 807 struct dpcd_peak_dsc_throughput_dsc_sink { 808 uint8_t THROUGHPUT_MODE_0:4; 809 uint8_t THROUGHPUT_MODE_1:4; 810 }; 811 812 struct dpcd_dsc_slice_capabilities_2 { 813 uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1; 814 uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1; 815 uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1; 816 uint8_t RESERVED :5; 817 }; 818 819 struct dpcd_bits_per_pixel_increment{ 820 uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3; 821 uint8_t RESERVED :5; 822 }; 823 union dpcd_dsc_basic_capabilities { 824 struct { 825 struct dpcd_dsc_support dsc_support; 826 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision; 827 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size; 828 uint8_t dsc_rc_buffer_size; 829 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1; 830 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth; 831 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support; 832 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor; 833 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities; 834 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities; 835 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink; 836 uint8_t dsc_maximum_slice_width; 837 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2; 838 uint8_t reserved; 839 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment; 840 } fields; 841 uint8_t raw[16]; 842 }; 843 844 union dpcd_dsc_branch_decoder_capabilities { 845 struct { 846 uint8_t BRANCH_OVERALL_THROUGHPUT_0; 847 uint8_t BRANCH_OVERALL_THROUGHPUT_1; 848 uint8_t BRANCH_MAX_LINE_WIDTH; 849 } fields; 850 uint8_t raw[3]; 851 }; 852 853 struct dpcd_dsc_capabilities { 854 union dpcd_dsc_basic_capabilities dsc_basic_caps; 855 union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps; 856 }; 857 858 /* These parameters are from PSR capabilities reported by Sink DPCD */ 859 struct psr_caps { 860 unsigned char psr_version; 861 unsigned int psr_rfb_setup_time; 862 bool psr_exit_link_training_required; 863 unsigned char edp_revision; 864 unsigned char support_ver; 865 bool su_granularity_required; 866 bool y_coordinate_required; 867 uint8_t su_y_granularity; 868 bool alpm_cap; 869 bool standby_support; 870 uint8_t rate_control_caps; 871 unsigned int psr_power_opt_flag; 872 }; 873 874 union dpcd_dprx_feature_enumeration_list_cont_1 { 875 struct { 876 uint8_t ADAPTIVE_SYNC_SDP_SUPPORT:1; 877 uint8_t AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED: 1; 878 uint8_t RESERVED0: 2; 879 uint8_t VSC_EXT_SDP_VER1_SUPPORT: 1; 880 uint8_t RESERVED1: 3; 881 } bits; 882 uint8_t raw; 883 }; 884 885 struct adaptive_sync_caps { 886 union dpcd_dprx_feature_enumeration_list_cont_1 dp_adap_sync_caps; 887 }; 888 889 /* Length of router topology ID read from DPCD in bytes. */ 890 #define DPCD_USB4_TOPOLOGY_ID_LEN 5 891 892 /* DPCD[0xE000D] DP_TUNNELING_CAPABILITIES SUPPORT register. */ 893 union dp_tun_cap_support { 894 struct { 895 uint8_t dp_tunneling :1; 896 uint8_t rsvd :5; 897 uint8_t panel_replay_tun_opt :1; 898 uint8_t dpia_bw_alloc :1; 899 } bits; 900 uint8_t raw; 901 }; 902 903 /* DPCD[0xE000E] DP_IN_ADAPTER_INFO register. */ 904 union dpia_info { 905 struct { 906 uint8_t dpia_num :5; 907 uint8_t rsvd :3; 908 } bits; 909 uint8_t raw; 910 }; 911 912 /* DP Tunneling over USB4 */ 913 struct dpcd_usb4_dp_tunneling_info { 914 union dp_tun_cap_support dp_tun_cap; 915 union dpia_info dpia_info; 916 uint8_t usb4_driver_id; 917 uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN]; 918 }; 919 920 #ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT 921 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 922 #endif 923 #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0 924 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230 925 #endif 926 #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256 927 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250 928 #endif 929 930 union dp_main_line_channel_coding_cap { 931 struct { 932 uint8_t DP_8b_10b_SUPPORTED :1; 933 uint8_t DP_128b_132b_SUPPORTED :1; 934 uint8_t RESERVED :6; 935 } bits; 936 uint8_t raw; 937 }; 938 939 union dp_main_link_channel_coding_lttpr_cap { 940 struct { 941 uint8_t DP_128b_132b_SUPPORTED :1; 942 uint8_t RESERVED :7; 943 } bits; 944 uint8_t raw; 945 }; 946 947 union dp_128b_132b_supported_link_rates { 948 struct { 949 uint8_t UHBR10 :1; 950 uint8_t UHBR20 :1; 951 uint8_t UHBR13_5:1; 952 uint8_t RESERVED:5; 953 } bits; 954 uint8_t raw; 955 }; 956 957 union dp_128b_132b_supported_lttpr_link_rates { 958 struct { 959 uint8_t UHBR10 :1; 960 uint8_t UHBR20 :1; 961 uint8_t UHBR13_5:1; 962 uint8_t RESERVED:5; 963 } bits; 964 uint8_t raw; 965 }; 966 967 union dp_sink_video_fallback_formats { 968 struct { 969 uint8_t dp_1024x768_60Hz_24bpp_support :1; 970 uint8_t dp_1280x720_60Hz_24bpp_support :1; 971 uint8_t dp_1920x1080_60Hz_24bpp_support :1; 972 uint8_t RESERVED :5; 973 } bits; 974 uint8_t raw; 975 }; 976 977 union dp_fec_capability1 { 978 struct { 979 uint8_t AGGREGATED_ERROR_COUNTERS_CAPABLE :1; 980 uint8_t RESERVED :7; 981 } bits; 982 uint8_t raw; 983 }; 984 985 union dp_cable_id { 986 struct { 987 uint8_t UHBR10_20_CAPABILITY :2; 988 uint8_t UHBR13_5_CAPABILITY :1; 989 uint8_t CABLE_TYPE :3; 990 uint8_t RESERVED :2; 991 } bits; 992 uint8_t raw; 993 }; 994 995 struct dp_color_depth_caps { 996 uint8_t support_6bpc :1; 997 uint8_t support_8bpc :1; 998 uint8_t support_10bpc :1; 999 uint8_t support_12bpc :1; 1000 uint8_t support_16bpc :1; 1001 uint8_t RESERVED :3; 1002 }; 1003 1004 struct dp_encoding_format_caps { 1005 uint8_t support_rgb :1; 1006 uint8_t support_ycbcr444:1; 1007 uint8_t support_ycbcr422:1; 1008 uint8_t support_ycbcr420:1; 1009 uint8_t RESERVED :4; 1010 }; 1011 1012 union dp_dfp_cap_ext { 1013 struct { 1014 uint8_t supported; 1015 uint8_t max_pixel_rate_in_mps[2]; 1016 uint8_t max_video_h_active_width[2]; 1017 uint8_t max_video_v_active_height[2]; 1018 struct dp_encoding_format_caps encoding_format_caps; 1019 struct dp_color_depth_caps rgb_color_depth_caps; 1020 struct dp_color_depth_caps ycbcr444_color_depth_caps; 1021 struct dp_color_depth_caps ycbcr422_color_depth_caps; 1022 struct dp_color_depth_caps ycbcr420_color_depth_caps; 1023 } fields; 1024 uint8_t raw[12]; 1025 }; 1026 1027 union dp_128b_132b_training_aux_rd_interval { 1028 struct { 1029 uint8_t VALUE :7; 1030 uint8_t UNIT :1; 1031 } bits; 1032 uint8_t raw; 1033 }; 1034 1035 union edp_alpm_caps { 1036 struct { 1037 uint8_t AUX_WAKE_ALPM_CAP :1; 1038 uint8_t PM_STATE_2A_SUPPORT :1; 1039 uint8_t AUX_LESS_ALPM_CAP :1; 1040 uint8_t RESERVED :5; 1041 } bits; 1042 uint8_t raw; 1043 }; 1044 1045 union edp_psr_dpcd_caps { 1046 struct { 1047 uint8_t LINK_TRAINING_ON_EXIT_NOT_REQUIRED :1; 1048 uint8_t PSR_SETUP_TIME :3; 1049 uint8_t Y_COORDINATE_REQUIRED :1; 1050 uint8_t SU_GRANULARITY_REQUIRED :1; 1051 uint8_t FRAME_SYNC_IS_NOT_NEEDED_FOR_SU :1; 1052 uint8_t RESERVED :1; 1053 } bits; 1054 uint8_t raw; 1055 }; 1056 1057 struct edp_psr_info { 1058 uint8_t psr_version; 1059 union edp_psr_dpcd_caps psr_dpcd_caps; 1060 uint8_t psr2_su_y_granularity_cap; 1061 uint8_t force_psrsu_cap; 1062 }; 1063 1064 struct replay_info { 1065 uint8_t pixel_deviation_per_line; 1066 uint8_t max_deviation_line; 1067 }; 1068 1069 struct dprx_states { 1070 bool cable_id_written; 1071 }; 1072 1073 enum dpcd_downstream_port_max_bpc { 1074 DOWN_STREAM_MAX_8BPC = 0, 1075 DOWN_STREAM_MAX_10BPC, 1076 DOWN_STREAM_MAX_12BPC, 1077 DOWN_STREAM_MAX_16BPC 1078 }; 1079 1080 enum link_training_offset { 1081 DPRX = 0, 1082 LTTPR_PHY_REPEATER1 = 1, 1083 LTTPR_PHY_REPEATER2 = 2, 1084 LTTPR_PHY_REPEATER3 = 3, 1085 LTTPR_PHY_REPEATER4 = 4, 1086 LTTPR_PHY_REPEATER5 = 5, 1087 LTTPR_PHY_REPEATER6 = 6, 1088 LTTPR_PHY_REPEATER7 = 7, 1089 LTTPR_PHY_REPEATER8 = 8 1090 }; 1091 1092 #define MAX_REPEATER_CNT 8 1093 1094 struct dc_lttpr_caps { 1095 union dpcd_rev revision; 1096 uint8_t mode; 1097 uint8_t max_lane_count; 1098 uint8_t max_link_rate; 1099 uint8_t phy_repeater_cnt; 1100 uint8_t max_ext_timeout; 1101 union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding; 1102 union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates; 1103 uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1]; 1104 }; 1105 1106 struct dc_dongle_dfp_cap_ext { 1107 bool supported; 1108 uint16_t max_pixel_rate_in_mps; 1109 uint16_t max_video_h_active_width; 1110 uint16_t max_video_v_active_height; 1111 struct dp_encoding_format_caps encoding_format_caps; 1112 struct dp_color_depth_caps rgb_color_depth_caps; 1113 struct dp_color_depth_caps ycbcr444_color_depth_caps; 1114 struct dp_color_depth_caps ycbcr422_color_depth_caps; 1115 struct dp_color_depth_caps ycbcr420_color_depth_caps; 1116 }; 1117 1118 struct dc_dongle_caps { 1119 /* dongle type (DP converter, CV smart dongle) */ 1120 enum display_dongle_type dongle_type; 1121 bool extendedCapValid; 1122 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1123 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1124 bool is_dp_hdmi_s3d_converter; 1125 bool is_dp_hdmi_ycbcr422_pass_through; 1126 bool is_dp_hdmi_ycbcr420_pass_through; 1127 bool is_dp_hdmi_ycbcr422_converter; 1128 bool is_dp_hdmi_ycbcr420_converter; 1129 uint32_t dp_hdmi_max_bpc; 1130 uint32_t dp_hdmi_max_pixel_clk_in_khz; 1131 uint32_t dp_hdmi_frl_max_link_bw_in_kbps; 1132 struct dc_dongle_dfp_cap_ext dfp_cap_ext; 1133 }; 1134 1135 struct dpcd_caps { 1136 union dpcd_rev dpcd_rev; 1137 union max_lane_count max_ln_count; 1138 union max_down_spread max_down_spread; 1139 union dprx_feature dprx_feature; 1140 1141 /* valid only for eDP v1.4 or higher*/ 1142 uint8_t edp_supported_link_rates_count; 1143 enum dc_link_rate edp_supported_link_rates[8]; 1144 1145 /* dongle type (DP converter, CV smart dongle) */ 1146 enum display_dongle_type dongle_type; 1147 bool is_dongle_type_one; 1148 /* branch device or sink device */ 1149 bool is_branch_dev; 1150 /* Dongle's downstream count. */ 1151 union sink_count sink_count; 1152 bool is_mst_capable; 1153 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1154 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1155 struct dc_dongle_caps dongle_caps; 1156 1157 uint32_t sink_dev_id; 1158 int8_t sink_dev_id_str[6]; 1159 int8_t sink_hw_revision; 1160 int8_t sink_fw_revision[2]; 1161 1162 uint32_t branch_dev_id; 1163 int8_t branch_dev_name[6]; 1164 int8_t branch_hw_revision; 1165 int8_t branch_fw_revision[2]; 1166 1167 bool allow_invalid_MSA_timing_param; 1168 bool panel_mode_edp; 1169 bool dpcd_display_control_capable; 1170 bool ext_receiver_cap_field_present; 1171 bool set_power_state_capable_edp; 1172 bool dynamic_backlight_capable_edp; 1173 union dpcd_fec_capability fec_cap; 1174 struct dpcd_dsc_capabilities dsc_caps; 1175 struct dc_lttpr_caps lttpr_caps; 1176 struct adaptive_sync_caps adaptive_sync_caps; 1177 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1178 1179 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1180 union dp_main_line_channel_coding_cap channel_coding_cap; 1181 union dp_sink_video_fallback_formats fallback_formats; 1182 union dp_fec_capability1 fec_cap1; 1183 bool panel_luminance_control; 1184 union dp_cable_id cable_id; 1185 uint8_t edp_rev; 1186 union edp_alpm_caps alpm_caps; 1187 struct edp_psr_info psr_info; 1188 1189 struct replay_info pr_info; 1190 }; 1191 1192 union dpcd_sink_ext_caps { 1193 struct { 1194 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1195 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1196 */ 1197 uint8_t sdr_aux_backlight_control : 1; 1198 uint8_t hdr_aux_backlight_control : 1; 1199 uint8_t reserved_1 : 2; 1200 uint8_t oled : 1; 1201 uint8_t reserved_2 : 1; 1202 uint8_t miniled : 1; 1203 uint8_t reserved : 1; 1204 } bits; 1205 uint8_t raw; 1206 }; 1207 1208 enum dc_link_fec_state { 1209 dc_link_fec_not_ready, 1210 dc_link_fec_ready, 1211 dc_link_fec_enabled 1212 }; 1213 1214 union dpcd_psr_configuration { 1215 struct { 1216 unsigned char ENABLE : 1; 1217 unsigned char TRANSMITTER_ACTIVE_IN_PSR : 1; 1218 unsigned char CRC_VERIFICATION : 1; 1219 unsigned char FRAME_CAPTURE_INDICATION : 1; 1220 /* For eDP 1.4, PSR v2*/ 1221 unsigned char LINE_CAPTURE_INDICATION : 1; 1222 /* For eDP 1.4, PSR v2*/ 1223 unsigned char IRQ_HPD_WITH_CRC_ERROR : 1; 1224 unsigned char ENABLE_PSR2 : 1; 1225 unsigned char EARLY_TRANSPORT_ENABLE : 1; 1226 } bits; 1227 unsigned char raw; 1228 }; 1229 1230 union replay_enable_and_configuration { 1231 struct { 1232 unsigned char FREESYNC_PANEL_REPLAY_MODE :1; 1233 unsigned char TIMING_DESYNC_ERROR_VERIFICATION :1; 1234 unsigned char STATE_TRANSITION_ERROR_DETECTION :1; 1235 unsigned char RESERVED0 :1; 1236 unsigned char RESERVED1 :4; 1237 } bits; 1238 unsigned char raw; 1239 }; 1240 1241 union dpcd_replay_configuration { 1242 struct { 1243 unsigned char STATE_TRANSITION_ERROR_STATUS : 1; 1244 unsigned char DESYNC_ERROR_STATUS : 1; 1245 unsigned char SINK_DEVICE_REPLAY_STATUS : 3; 1246 unsigned char SINK_FRAME_LOCKED : 2; 1247 unsigned char RESERVED : 1; 1248 } bits; 1249 unsigned char raw; 1250 }; 1251 1252 union dpcd_alpm_configuration { 1253 struct { 1254 unsigned char ENABLE : 1; 1255 unsigned char IRQ_HPD_ENABLE : 1; 1256 unsigned char RESERVED : 6; 1257 } bits; 1258 unsigned char raw; 1259 }; 1260 1261 union dpcd_sink_active_vtotal_control_mode { 1262 struct { 1263 unsigned char ENABLE : 1; 1264 unsigned char RESERVED : 7; 1265 } bits; 1266 unsigned char raw; 1267 }; 1268 1269 union psr_error_status { 1270 struct { 1271 unsigned char LINK_CRC_ERROR :1; 1272 unsigned char RFB_STORAGE_ERROR :1; 1273 unsigned char VSC_SDP_ERROR :1; 1274 unsigned char RESERVED :5; 1275 } bits; 1276 unsigned char raw; 1277 }; 1278 1279 union psr_sink_psr_status { 1280 struct { 1281 unsigned char SINK_SELF_REFRESH_STATUS :3; 1282 unsigned char RESERVED :5; 1283 } bits; 1284 unsigned char raw; 1285 }; 1286 1287 struct edp_trace_power_timestamps { 1288 uint64_t poweroff; 1289 uint64_t poweron; 1290 }; 1291 1292 struct dp_trace_lt_counts { 1293 unsigned int total; 1294 unsigned int fail; 1295 }; 1296 1297 enum link_training_result { 1298 LINK_TRAINING_SUCCESS, 1299 LINK_TRAINING_CR_FAIL_LANE0, 1300 LINK_TRAINING_CR_FAIL_LANE1, 1301 LINK_TRAINING_CR_FAIL_LANE23, 1302 /* CR DONE bit is cleared during EQ step */ 1303 LINK_TRAINING_EQ_FAIL_CR, 1304 /* CR DONE bit is cleared but LANE0_CR_DONE is set during EQ step */ 1305 LINK_TRAINING_EQ_FAIL_CR_PARTIAL, 1306 /* other failure during EQ step */ 1307 LINK_TRAINING_EQ_FAIL_EQ, 1308 LINK_TRAINING_LQA_FAIL, 1309 /* one of the CR,EQ or symbol lock is dropped */ 1310 LINK_TRAINING_LINK_LOSS, 1311 /* Abort link training (because sink unplugged) */ 1312 LINK_TRAINING_ABORT, 1313 DP_128b_132b_LT_FAILED, 1314 DP_128b_132b_MAX_LOOP_COUNT_REACHED, 1315 DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT, 1316 DP_128b_132b_CDS_DONE_TIMEOUT, 1317 }; 1318 1319 struct dp_trace_lt { 1320 struct dp_trace_lt_counts counts; 1321 struct dp_trace_timestamps { 1322 unsigned long long start; 1323 unsigned long long end; 1324 } timestamps; 1325 enum link_training_result result; 1326 bool is_logged; 1327 }; 1328 1329 struct dp_trace { 1330 struct dp_trace_lt detect_lt_trace; 1331 struct dp_trace_lt commit_lt_trace; 1332 unsigned int link_loss_count; 1333 bool is_initialized; 1334 struct edp_trace_power_timestamps edp_trace_power_timestamps; 1335 }; 1336 1337 /* TODO - This is a temporary location for any new DPCD definitions. 1338 * We should move these to drm_dp header. 1339 */ 1340 #ifndef DP_LINK_SQUARE_PATTERN 1341 #define DP_LINK_SQUARE_PATTERN 0x10F 1342 #endif 1343 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX 1344 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX 0x2217 1345 #endif 1346 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 1347 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 0x110 1348 #endif 1349 #ifndef DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 1350 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50 1351 #endif 1352 #ifndef DP_TUNNELING_IRQ 1353 #define DP_TUNNELING_IRQ (1 << 5) 1354 #endif 1355 /** USB4 DPCD BW Allocation Registers Chapter 10.7 **/ 1356 #ifndef DP_TUNNELING_CAPABILITIES 1357 #define DP_TUNNELING_CAPABILITIES 0xE000D /* 1.4a */ 1358 #endif 1359 #ifndef USB4_DRIVER_ID 1360 #define USB4_DRIVER_ID 0xE000F /* 1.4a */ 1361 #endif 1362 #ifndef USB4_DRIVER_BW_CAPABILITY 1363 #define USB4_DRIVER_BW_CAPABILITY 0xE0020 /* 1.4a */ 1364 #endif 1365 #ifndef DP_IN_ADAPTER_TUNNEL_INFO 1366 #define DP_IN_ADAPTER_TUNNEL_INFO 0xE0021 /* 1.4a */ 1367 #endif 1368 #ifndef DP_BW_GRANULALITY 1369 #define DP_BW_GRANULALITY 0xE0022 /* 1.4a */ 1370 #endif 1371 #ifndef ESTIMATED_BW 1372 #define ESTIMATED_BW 0xE0023 /* 1.4a */ 1373 #endif 1374 #ifndef ALLOCATED_BW 1375 #define ALLOCATED_BW 0xE0024 /* 1.4a */ 1376 #endif 1377 #ifndef DP_TUNNELING_STATUS 1378 #define DP_TUNNELING_STATUS 0xE0025 /* 1.4a */ 1379 #endif 1380 #ifndef DPTX_BW_ALLOCATION_MODE_CONTROL 1381 #define DPTX_BW_ALLOCATION_MODE_CONTROL 0xE0030 /* 1.4a */ 1382 #endif 1383 #ifndef REQUESTED_BW 1384 #define REQUESTED_BW 0xE0031 /* 1.4a */ 1385 #endif 1386 #endif /* DC_DP_TYPES_H */ 1387