1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services_types.h" 28 29 #include "amdgpu.h" 30 #include "amdgpu_dm.h" 31 #include "amdgpu_dm_wb.h" 32 #include "amdgpu_display.h" 33 #include "dc.h" 34 35 #include <drm/drm_edid.h> 36 #include <drm/drm_atomic_state_helper.h> 37 #include <drm/drm_modeset_helper_vtables.h> 38 39 static const u32 amdgpu_dm_wb_formats[] = { 40 DRM_FORMAT_XRGB2101010, 41 }; 42 43 static int amdgpu_dm_wb_encoder_atomic_check(struct drm_encoder *encoder, 44 struct drm_crtc_state *crtc_state, 45 struct drm_connector_state *conn_state) 46 { 47 struct drm_framebuffer *fb; 48 const struct drm_display_mode *mode = &crtc_state->mode; 49 bool found = false; 50 uint8_t i; 51 52 if (!conn_state->writeback_job || !conn_state->writeback_job->fb) 53 return 0; 54 55 fb = conn_state->writeback_job->fb; 56 if (fb->width != mode->hdisplay || fb->height != mode->vdisplay) { 57 DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n", 58 fb->width, fb->height); 59 return -EINVAL; 60 } 61 62 for (i = 0; i < sizeof(amdgpu_dm_wb_formats) / sizeof(u32); i++) { 63 if (fb->format->format == amdgpu_dm_wb_formats[i]) 64 found = true; 65 } 66 67 if (!found) { 68 DRM_DEBUG_KMS("Invalid pixel format %p4cc\n", 69 &fb->format->format); 70 return -EINVAL; 71 } 72 73 return 0; 74 } 75 76 77 static int amdgpu_dm_wb_connector_get_modes(struct drm_connector *connector) 78 { 79 struct drm_device *dev = connector->dev; 80 81 return drm_add_modes_noedid(connector, dev->mode_config.max_width, 82 dev->mode_config.max_height); 83 } 84 85 static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector, 86 struct drm_writeback_job *job) 87 { 88 struct amdgpu_framebuffer *afb; 89 struct drm_gem_object *obj; 90 struct amdgpu_device *adev; 91 struct amdgpu_bo *rbo; 92 uint32_t domain; 93 int r; 94 95 if (!job->fb) { 96 DRM_DEBUG_KMS("No FB bound\n"); 97 return 0; 98 } 99 100 afb = to_amdgpu_framebuffer(job->fb); 101 obj = job->fb->obj[0]; 102 rbo = gem_to_amdgpu_bo(obj); 103 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 104 105 r = amdgpu_bo_reserve(rbo, true); 106 if (r) { 107 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 108 return r; 109 } 110 111 r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); 112 if (r) { 113 dev_err(adev->dev, "reserving fence slot failed (%d)\n", r); 114 goto error_unlock; 115 } 116 117 domain = amdgpu_display_supported_domains(adev, rbo->flags); 118 119 r = amdgpu_bo_pin(rbo, domain); 120 if (unlikely(r != 0)) { 121 if (r != -ERESTARTSYS) 122 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 123 goto error_unlock; 124 } 125 126 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 127 if (unlikely(r != 0)) { 128 DRM_ERROR("%p bind failed\n", rbo); 129 goto error_unpin; 130 } 131 132 amdgpu_bo_unreserve(rbo); 133 134 afb->address = amdgpu_bo_gpu_offset(rbo); 135 136 amdgpu_bo_ref(rbo); 137 138 return 0; 139 140 error_unpin: 141 amdgpu_bo_unpin(rbo); 142 143 error_unlock: 144 amdgpu_bo_unreserve(rbo); 145 return r; 146 } 147 148 static void amdgpu_dm_wb_cleanup_job(struct drm_writeback_connector *connector, 149 struct drm_writeback_job *job) 150 { 151 struct amdgpu_bo *rbo; 152 int r; 153 154 if (!job->fb) 155 return; 156 157 rbo = gem_to_amdgpu_bo(job->fb->obj[0]); 158 r = amdgpu_bo_reserve(rbo, false); 159 if (unlikely(r)) { 160 DRM_ERROR("failed to reserve rbo before unpin\n"); 161 return; 162 } 163 164 amdgpu_bo_unpin(rbo); 165 amdgpu_bo_unreserve(rbo); 166 amdgpu_bo_unref(&rbo); 167 } 168 169 static const struct drm_encoder_helper_funcs amdgpu_dm_wb_encoder_helper_funcs = { 170 .atomic_check = amdgpu_dm_wb_encoder_atomic_check, 171 }; 172 173 static const struct drm_connector_funcs amdgpu_dm_wb_connector_funcs = { 174 .fill_modes = drm_helper_probe_single_connector_modes, 175 .destroy = drm_connector_cleanup, 176 .reset = amdgpu_dm_connector_funcs_reset, 177 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 178 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 179 }; 180 181 static const struct drm_connector_helper_funcs amdgpu_dm_wb_conn_helper_funcs = { 182 .get_modes = amdgpu_dm_wb_connector_get_modes, 183 .prepare_writeback_job = amdgpu_dm_wb_prepare_job, 184 .cleanup_writeback_job = amdgpu_dm_wb_cleanup_job, 185 }; 186 187 int amdgpu_dm_wb_connector_init(struct amdgpu_display_manager *dm, 188 struct amdgpu_dm_wb_connector *wbcon, 189 uint32_t link_index) 190 { 191 struct dc *dc = dm->dc; 192 struct dc_link *link = dc_get_link_at_index(dc, link_index); 193 int res = 0; 194 195 wbcon->link = link; 196 197 drm_connector_helper_add(&wbcon->base.base, &amdgpu_dm_wb_conn_helper_funcs); 198 199 res = drm_writeback_connector_init(&dm->adev->ddev, &wbcon->base, 200 &amdgpu_dm_wb_connector_funcs, 201 &amdgpu_dm_wb_encoder_helper_funcs, 202 amdgpu_dm_wb_formats, 203 ARRAY_SIZE(amdgpu_dm_wb_formats), 204 amdgpu_dm_get_encoder_crtc_mask(dm->adev)); 205 206 if (res) 207 return res; 208 /* 209 * Some of the properties below require access to state, like bpc. 210 * Allocate some default initial connector state with our reset helper. 211 */ 212 if (wbcon->base.base.funcs->reset) 213 wbcon->base.base.funcs->reset(&wbcon->base.base); 214 215 return 0; 216 } 217