1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "mmhub_v1_0.h" 25 26 #include "mmhub/mmhub_1_0_offset.h" 27 #include "mmhub/mmhub_1_0_sh_mask.h" 28 #include "mmhub/mmhub_1_0_default.h" 29 #include "athub/athub_1_0_offset.h" 30 #include "athub/athub_1_0_sh_mask.h" 31 #include "vega10_enum.h" 32 33 #include "soc15_common.h" 34 35 #define mmDAGB0_CNTL_MISC2_RV 0x008f 36 #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0 37 38 u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev) 39 { 40 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); 41 42 base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 43 base <<= 24; 44 45 return base; 46 } 47 48 static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) 49 { 50 uint64_t value; 51 52 BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); 53 value = adev->gart.table_addr - adev->gmc.vram_start + 54 adev->vm_manager.vram_base_offset; 55 value &= 0x0000FFFFFFFFF000ULL; 56 value |= 0x1; /* valid bit */ 57 58 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 59 lower_32_bits(value)); 60 61 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 62 upper_32_bits(value)); 63 } 64 65 static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 66 { 67 mmhub_v1_0_init_gart_pt_regs(adev); 68 69 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 70 (u32)(adev->gmc.gart_start >> 12)); 71 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 72 (u32)(adev->gmc.gart_start >> 44)); 73 74 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 75 (u32)(adev->gmc.gart_end >> 12)); 76 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 77 (u32)(adev->gmc.gart_end >> 44)); 78 } 79 80 static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 81 { 82 uint64_t value; 83 uint32_t tmp; 84 85 /* Disable AGP. */ 86 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); 87 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0); 88 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF); 89 90 /* Program the system aperture low logical page number. */ 91 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 92 adev->gmc.vram_start >> 18); 93 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 94 adev->gmc.vram_end >> 18); 95 96 /* Set default page address. */ 97 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 98 adev->vm_manager.vram_base_offset; 99 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 100 (u32)(value >> 12)); 101 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 102 (u32)(value >> 44)); 103 104 /* Program "protection fault". */ 105 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 106 (u32)(adev->dummy_page_addr >> 12)); 107 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 108 (u32)((u64)adev->dummy_page_addr >> 44)); 109 110 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); 111 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, 112 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 113 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp); 114 } 115 116 static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 117 { 118 uint32_t tmp; 119 120 /* Setup TLB control */ 121 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); 122 123 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 124 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 125 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 126 ENABLE_ADVANCED_DRIVER_MODEL, 1); 127 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 128 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 129 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 130 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 131 MTYPE, MTYPE_UC);/* XXX for emulation. */ 132 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); 133 134 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 135 } 136 137 static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 138 { 139 uint32_t tmp; 140 141 /* Setup L2 cache */ 142 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); 143 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 144 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 145 /* XXX for emulation, Refer to closed source code.*/ 146 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 147 0); 148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); 149 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 150 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 151 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); 152 153 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); 154 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 155 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 156 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); 157 158 if (adev->gmc.translate_further) { 159 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 160 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 161 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 162 } else { 163 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 164 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 165 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 166 } 167 168 tmp = mmVM_L2_CNTL4_DEFAULT; 169 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 170 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 171 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp); 172 } 173 174 static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 175 { 176 uint32_t tmp; 177 178 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); 179 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 180 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 181 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp); 182 } 183 184 static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) 185 { 186 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 187 0XFFFFFFFF); 188 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 189 0x0000000F); 190 191 WREG32_SOC15(MMHUB, 0, 192 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 193 WREG32_SOC15(MMHUB, 0, 194 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 195 196 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 197 0); 198 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 199 0); 200 } 201 202 static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) 203 { 204 unsigned num_level, block_size; 205 uint32_t tmp; 206 int i; 207 208 num_level = adev->vm_manager.num_level; 209 block_size = adev->vm_manager.block_size; 210 if (adev->gmc.translate_further) 211 num_level -= 1; 212 else 213 block_size -= 9; 214 215 for (i = 0; i <= 14; i++) { 216 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i); 217 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 218 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 219 num_level); 220 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 221 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 222 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 223 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 224 1); 225 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 226 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 227 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 228 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 229 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 230 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 231 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 232 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 233 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 234 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 235 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 236 PAGE_TABLE_BLOCK_SIZE, 237 block_size); 238 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 239 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 240 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 241 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp); 242 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 243 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 244 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 245 lower_32_bits(adev->vm_manager.max_pfn - 1)); 246 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 247 upper_32_bits(adev->vm_manager.max_pfn - 1)); 248 } 249 } 250 251 static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev) 252 { 253 unsigned i; 254 255 for (i = 0; i < 18; ++i) { 256 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 257 2 * i, 0xffffffff); 258 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 259 2 * i, 0x1f); 260 } 261 } 262 263 struct pctl_data { 264 uint32_t index; 265 uint32_t data; 266 }; 267 268 static const struct pctl_data pctl0_data[] = { 269 {0x0, 0x7a640}, 270 {0x9, 0x2a64a}, 271 {0xd, 0x2a680}, 272 {0x11, 0x6a684}, 273 {0x19, 0xea68e}, 274 {0x29, 0xa69e}, 275 {0x2b, 0x0010a6c0}, 276 {0x3d, 0x83a707}, 277 {0xc2, 0x8a7a4}, 278 {0xcc, 0x1a7b8}, 279 {0xcf, 0xfa7cc}, 280 {0xe0, 0x17a7dd}, 281 {0xf9, 0xa7dc}, 282 {0xfb, 0x12a7f5}, 283 {0x10f, 0xa808}, 284 {0x111, 0x12a810}, 285 {0x125, 0x7a82c} 286 }; 287 #define PCTL0_DATA_LEN (ARRAY_SIZE(pctl0_data)) 288 289 #define PCTL0_RENG_EXEC_END_PTR 0x12d 290 #define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE 0xa640 291 #define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833 292 293 static const struct pctl_data pctl1_data[] = { 294 {0x0, 0x39a000}, 295 {0x3b, 0x44a040}, 296 {0x81, 0x2a08d}, 297 {0x85, 0x6ba094}, 298 {0xf2, 0x18a100}, 299 {0x10c, 0x4a132}, 300 {0x112, 0xca141}, 301 {0x120, 0x2fa158}, 302 {0x151, 0x17a1d0}, 303 {0x16a, 0x1a1e9}, 304 {0x16d, 0x13a1ec}, 305 {0x182, 0x7a201}, 306 {0x18b, 0x3a20a}, 307 {0x190, 0x7a580}, 308 {0x199, 0xa590}, 309 {0x19b, 0x4a594}, 310 {0x1a1, 0x1a59c}, 311 {0x1a4, 0x7a82c}, 312 {0x1ad, 0xfa7cc}, 313 {0x1be, 0x17a7dd}, 314 {0x1d7, 0x12a810}, 315 {0x1eb, 0x4000a7e1}, 316 {0x1ec, 0x5000a7f5}, 317 {0x1ed, 0x4000a7e2}, 318 {0x1ee, 0x5000a7dc}, 319 {0x1ef, 0x4000a7e3}, 320 {0x1f0, 0x5000a7f6}, 321 {0x1f1, 0x5000a7e4} 322 }; 323 #define PCTL1_DATA_LEN (ARRAY_SIZE(pctl1_data)) 324 325 #define PCTL1_RENG_EXEC_END_PTR 0x1f1 326 #define PCTL1_STCTRL_REG_SAVE_RANGE0_BASE 0xa000 327 #define PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa20d 328 #define PCTL1_STCTRL_REG_SAVE_RANGE1_BASE 0xa580 329 #define PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT 0xa59d 330 #define PCTL1_STCTRL_REG_SAVE_RANGE2_BASE 0xa82c 331 #define PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT 0xa833 332 333 static void mmhub_v1_0_power_gating_write_save_ranges(struct amdgpu_device *adev) 334 { 335 uint32_t tmp = 0; 336 337 /* PCTL0_STCTRL_REGISTER_SAVE_RANGE0 */ 338 tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0, 339 STCTRL_REGISTER_SAVE_BASE, 340 PCTL0_STCTRL_REG_SAVE_RANGE0_BASE); 341 tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0, 342 STCTRL_REGISTER_SAVE_LIMIT, 343 PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT); 344 WREG32_SOC15(MMHUB, 0, mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0, tmp); 345 346 /* PCTL1_STCTRL_REGISTER_SAVE_RANGE0 */ 347 tmp = 0; 348 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0, 349 STCTRL_REGISTER_SAVE_BASE, 350 PCTL1_STCTRL_REG_SAVE_RANGE0_BASE); 351 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0, 352 STCTRL_REGISTER_SAVE_LIMIT, 353 PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT); 354 WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0, tmp); 355 356 /* PCTL1_STCTRL_REGISTER_SAVE_RANGE1 */ 357 tmp = 0; 358 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1, 359 STCTRL_REGISTER_SAVE_BASE, 360 PCTL1_STCTRL_REG_SAVE_RANGE1_BASE); 361 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1, 362 STCTRL_REGISTER_SAVE_LIMIT, 363 PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT); 364 WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1, tmp); 365 366 /* PCTL1_STCTRL_REGISTER_SAVE_RANGE2 */ 367 tmp = 0; 368 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2, 369 STCTRL_REGISTER_SAVE_BASE, 370 PCTL1_STCTRL_REG_SAVE_RANGE2_BASE); 371 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2, 372 STCTRL_REGISTER_SAVE_LIMIT, 373 PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT); 374 WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2, tmp); 375 } 376 377 void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev) 378 { 379 uint32_t pctl0_misc = 0; 380 uint32_t pctl0_reng_execute = 0; 381 uint32_t pctl1_misc = 0; 382 uint32_t pctl1_reng_execute = 0; 383 int i = 0; 384 385 if (amdgpu_sriov_vf(adev)) 386 return; 387 388 /****************** pctl0 **********************/ 389 pctl0_misc = RREG32_SOC15(MMHUB, 0, mmPCTL0_MISC); 390 pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE); 391 392 /* Light sleep must be disabled before writing to pctl0 registers */ 393 pctl0_misc &= ~PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK; 394 WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc); 395 396 /* Write data used to access ram of register engine */ 397 for (i = 0; i < PCTL0_DATA_LEN; i++) { 398 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_INDEX, 399 pctl0_data[i].index); 400 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_DATA, 401 pctl0_data[i].data); 402 } 403 404 /* Re-enable light sleep */ 405 pctl0_misc |= PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK; 406 WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc); 407 408 /****************** pctl1 **********************/ 409 pctl1_misc = RREG32_SOC15(MMHUB, 0, mmPCTL1_MISC); 410 pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE); 411 412 /* Light sleep must be disabled before writing to pctl1 registers */ 413 pctl1_misc &= ~PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK; 414 WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc); 415 416 /* Write data used to access ram of register engine */ 417 for (i = 0; i < PCTL1_DATA_LEN; i++) { 418 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_INDEX, 419 pctl1_data[i].index); 420 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_DATA, 421 pctl1_data[i].data); 422 } 423 424 /* Re-enable light sleep */ 425 pctl1_misc |= PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK; 426 WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc); 427 428 mmhub_v1_0_power_gating_write_save_ranges(adev); 429 430 /* Set the reng execute end ptr for pctl0 */ 431 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, 432 PCTL0_RENG_EXECUTE, 433 RENG_EXECUTE_END_PTR, 434 PCTL0_RENG_EXEC_END_PTR); 435 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute); 436 437 /* Set the reng execute end ptr for pctl1 */ 438 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, 439 PCTL1_RENG_EXECUTE, 440 RENG_EXECUTE_END_PTR, 441 PCTL1_RENG_EXEC_END_PTR); 442 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute); 443 } 444 445 void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev, 446 bool enable) 447 { 448 uint32_t pctl0_reng_execute = 0; 449 uint32_t pctl1_reng_execute = 0; 450 451 if (amdgpu_sriov_vf(adev)) 452 return; 453 454 pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE); 455 pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE); 456 457 if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) { 458 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, 459 PCTL0_RENG_EXECUTE, 460 RENG_EXECUTE_ON_PWR_UP, 1); 461 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, 462 PCTL0_RENG_EXECUTE, 463 RENG_EXECUTE_ON_REG_UPDATE, 1); 464 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute); 465 466 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, 467 PCTL1_RENG_EXECUTE, 468 RENG_EXECUTE_ON_PWR_UP, 1); 469 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, 470 PCTL1_RENG_EXECUTE, 471 RENG_EXECUTE_ON_REG_UPDATE, 1); 472 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute); 473 474 if (adev->powerplay.pp_funcs->set_mmhub_powergating_by_smu) 475 amdgpu_dpm_set_mmhub_powergating_by_smu(adev); 476 477 } else { 478 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, 479 PCTL0_RENG_EXECUTE, 480 RENG_EXECUTE_ON_PWR_UP, 0); 481 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, 482 PCTL0_RENG_EXECUTE, 483 RENG_EXECUTE_ON_REG_UPDATE, 0); 484 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute); 485 486 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, 487 PCTL1_RENG_EXECUTE, 488 RENG_EXECUTE_ON_PWR_UP, 0); 489 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, 490 PCTL1_RENG_EXECUTE, 491 RENG_EXECUTE_ON_REG_UPDATE, 0); 492 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute); 493 } 494 } 495 496 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) 497 { 498 if (amdgpu_sriov_vf(adev)) { 499 /* 500 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 501 * VF copy registers so vbios post doesn't program them, for 502 * SRIOV driver need to program them 503 */ 504 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE, 505 adev->gmc.vram_start >> 24); 506 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP, 507 adev->gmc.vram_end >> 24); 508 } 509 510 /* GART Enable. */ 511 mmhub_v1_0_init_gart_aperture_regs(adev); 512 mmhub_v1_0_init_system_aperture_regs(adev); 513 mmhub_v1_0_init_tlb_regs(adev); 514 mmhub_v1_0_init_cache_regs(adev); 515 516 mmhub_v1_0_enable_system_domain(adev); 517 mmhub_v1_0_disable_identity_aperture(adev); 518 mmhub_v1_0_setup_vmid_config(adev); 519 mmhub_v1_0_program_invalidation(adev); 520 521 return 0; 522 } 523 524 void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) 525 { 526 u32 tmp; 527 u32 i; 528 529 /* Disable all tables */ 530 for (i = 0; i < 16; i++) 531 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0); 532 533 /* Setup TLB control */ 534 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); 535 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 536 tmp = REG_SET_FIELD(tmp, 537 MC_VM_MX_L1_TLB_CNTL, 538 ENABLE_ADVANCED_DRIVER_MODEL, 539 0); 540 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 541 542 /* Setup L2 cache */ 543 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); 544 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 545 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); 546 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0); 547 } 548 549 /** 550 * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling 551 * 552 * @adev: amdgpu_device pointer 553 * @value: true redirects VM faults to the default page 554 */ 555 void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 556 { 557 u32 tmp; 558 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 559 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 560 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 561 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 562 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 563 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 564 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 565 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 566 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 567 tmp = REG_SET_FIELD(tmp, 568 VM_L2_PROTECTION_FAULT_CNTL, 569 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 570 value); 571 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 572 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 573 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 574 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 575 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 576 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 577 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 578 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 579 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 580 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 581 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 582 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 583 if (!value) { 584 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 585 CRASH_ON_NO_RETRY_FAULT, 1); 586 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 587 CRASH_ON_RETRY_FAULT, 1); 588 } 589 590 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); 591 } 592 593 void mmhub_v1_0_init(struct amdgpu_device *adev) 594 { 595 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB]; 596 597 hub->ctx0_ptb_addr_lo32 = 598 SOC15_REG_OFFSET(MMHUB, 0, 599 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 600 hub->ctx0_ptb_addr_hi32 = 601 SOC15_REG_OFFSET(MMHUB, 0, 602 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 603 hub->vm_inv_eng0_req = 604 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ); 605 hub->vm_inv_eng0_ack = 606 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK); 607 hub->vm_context0_cntl = 608 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL); 609 hub->vm_l2_pro_fault_status = 610 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS); 611 hub->vm_l2_pro_fault_cntl = 612 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 613 614 } 615 616 static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 617 bool enable) 618 { 619 uint32_t def, data, def1, data1, def2 = 0, data2 = 0; 620 621 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 622 623 if (adev->asic_type != CHIP_RAVEN) { 624 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); 625 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); 626 } else 627 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV); 628 629 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 630 data |= ATC_L2_MISC_CG__ENABLE_MASK; 631 632 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 633 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 634 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 635 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 636 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 637 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 638 639 if (adev->asic_type != CHIP_RAVEN) 640 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 641 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 642 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 643 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 644 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 645 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 646 } else { 647 data &= ~ATC_L2_MISC_CG__ENABLE_MASK; 648 649 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 650 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 651 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 652 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 653 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 654 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 655 656 if (adev->asic_type != CHIP_RAVEN) 657 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 658 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 659 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 660 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 661 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 662 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 663 } 664 665 if (def != data) 666 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); 667 668 if (def1 != data1) { 669 if (adev->asic_type != CHIP_RAVEN) 670 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); 671 else 672 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1); 673 } 674 675 if (adev->asic_type != CHIP_RAVEN && def2 != data2) 676 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); 677 } 678 679 static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev, 680 bool enable) 681 { 682 uint32_t def, data; 683 684 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 685 686 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 687 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK; 688 else 689 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK; 690 691 if (def != data) 692 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); 693 } 694 695 static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 696 bool enable) 697 { 698 uint32_t def, data; 699 700 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 701 702 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 703 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 704 else 705 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 706 707 if (def != data) 708 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); 709 } 710 711 static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev, 712 bool enable) 713 { 714 uint32_t def, data; 715 716 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 717 718 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) && 719 (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 720 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 721 else 722 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; 723 724 if(def != data) 725 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); 726 } 727 728 int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev, 729 enum amd_clockgating_state state) 730 { 731 if (amdgpu_sriov_vf(adev)) 732 return 0; 733 734 switch (adev->asic_type) { 735 case CHIP_VEGA10: 736 case CHIP_VEGA12: 737 case CHIP_RAVEN: 738 mmhub_v1_0_update_medium_grain_clock_gating(adev, 739 state == AMD_CG_STATE_GATE ? true : false); 740 athub_update_medium_grain_clock_gating(adev, 741 state == AMD_CG_STATE_GATE ? true : false); 742 mmhub_v1_0_update_medium_grain_light_sleep(adev, 743 state == AMD_CG_STATE_GATE ? true : false); 744 athub_update_medium_grain_light_sleep(adev, 745 state == AMD_CG_STATE_GATE ? true : false); 746 break; 747 default: 748 break; 749 } 750 751 return 0; 752 } 753 754 void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 755 { 756 int data; 757 758 if (amdgpu_sriov_vf(adev)) 759 *flags = 0; 760 761 /* AMD_CG_SUPPORT_MC_MGCG */ 762 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); 763 if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK) 764 *flags |= AMD_CG_SUPPORT_MC_MGCG; 765 766 /* AMD_CG_SUPPORT_MC_LS */ 767 data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); 768 if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 769 *flags |= AMD_CG_SUPPORT_MC_LS; 770 } 771