1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "vid.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 35 #include "dce/dce_11_0_d.h" 36 #include "dce/dce_11_0_sh_mask.h" 37 #include "dce/dce_11_0_enum.h" 38 #include "oss/oss_3_0_d.h" 39 #include "oss/oss_3_0_sh_mask.h" 40 #include "gmc/gmc_8_1_d.h" 41 #include "gmc/gmc_8_1_sh_mask.h" 42 43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); 44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); 45 46 static const u32 crtc_offsets[] = 47 { 48 CRTC0_REGISTER_OFFSET, 49 CRTC1_REGISTER_OFFSET, 50 CRTC2_REGISTER_OFFSET, 51 CRTC3_REGISTER_OFFSET, 52 CRTC4_REGISTER_OFFSET, 53 CRTC5_REGISTER_OFFSET, 54 CRTC6_REGISTER_OFFSET 55 }; 56 57 static const u32 hpd_offsets[] = 58 { 59 HPD0_REGISTER_OFFSET, 60 HPD1_REGISTER_OFFSET, 61 HPD2_REGISTER_OFFSET, 62 HPD3_REGISTER_OFFSET, 63 HPD4_REGISTER_OFFSET, 64 HPD5_REGISTER_OFFSET 65 }; 66 67 static const uint32_t dig_offsets[] = { 68 DIG0_REGISTER_OFFSET, 69 DIG1_REGISTER_OFFSET, 70 DIG2_REGISTER_OFFSET, 71 DIG3_REGISTER_OFFSET, 72 DIG4_REGISTER_OFFSET, 73 DIG5_REGISTER_OFFSET, 74 DIG6_REGISTER_OFFSET, 75 DIG7_REGISTER_OFFSET, 76 DIG8_REGISTER_OFFSET 77 }; 78 79 static const struct { 80 uint32_t reg; 81 uint32_t vblank; 82 uint32_t vline; 83 uint32_t hpd; 84 85 } interrupt_status_offsets[] = { { 86 .reg = mmDISP_INTERRUPT_STATUS, 87 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 88 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 89 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 90 }, { 91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 93 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 95 }, { 96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 98 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 100 }, { 101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 103 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 105 }, { 106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 108 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 110 }, { 111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 113 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 115 } }; 116 117 static const u32 cz_golden_settings_a11[] = 118 { 119 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 120 mmFBC_MISC, 0x1f311fff, 0x14300000, 121 }; 122 123 static const u32 cz_mgcg_cgcg_init[] = 124 { 125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 127 }; 128 129 static const u32 stoney_golden_settings_a11[] = 130 { 131 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 132 mmFBC_MISC, 0x1f311fff, 0x14302000, 133 }; 134 135 136 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) 137 { 138 switch (adev->asic_type) { 139 case CHIP_CARRIZO: 140 amdgpu_program_register_sequence(adev, 141 cz_mgcg_cgcg_init, 142 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 143 amdgpu_program_register_sequence(adev, 144 cz_golden_settings_a11, 145 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 146 break; 147 case CHIP_STONEY: 148 amdgpu_program_register_sequence(adev, 149 stoney_golden_settings_a11, 150 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 151 break; 152 default: 153 break; 154 } 155 } 156 157 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev, 158 u32 block_offset, u32 reg) 159 { 160 unsigned long flags; 161 u32 r; 162 163 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 164 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 165 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 166 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 167 168 return r; 169 } 170 171 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev, 172 u32 block_offset, u32 reg, u32 v) 173 { 174 unsigned long flags; 175 176 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 177 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 178 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 179 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 180 } 181 182 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 183 { 184 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & 185 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) 186 return true; 187 else 188 return false; 189 } 190 191 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 192 { 193 u32 pos1, pos2; 194 195 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 196 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 197 198 if (pos1 != pos2) 199 return true; 200 else 201 return false; 202 } 203 204 /** 205 * dce_v11_0_vblank_wait - vblank wait asic callback. 206 * 207 * @adev: amdgpu_device pointer 208 * @crtc: crtc to wait for vblank on 209 * 210 * Wait for vblank on the requested crtc (evergreen+). 211 */ 212 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc) 213 { 214 unsigned i = 0; 215 216 if (crtc >= adev->mode_info.num_crtc) 217 return; 218 219 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 220 return; 221 222 /* depending on when we hit vblank, we may be close to active; if so, 223 * wait for another frame. 224 */ 225 while (dce_v11_0_is_in_vblank(adev, crtc)) { 226 if (i++ % 100 == 0) { 227 if (!dce_v11_0_is_counter_moving(adev, crtc)) 228 break; 229 } 230 } 231 232 while (!dce_v11_0_is_in_vblank(adev, crtc)) { 233 if (i++ % 100 == 0) { 234 if (!dce_v11_0_is_counter_moving(adev, crtc)) 235 break; 236 } 237 } 238 } 239 240 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 241 { 242 if (crtc >= adev->mode_info.num_crtc) 243 return 0; 244 else 245 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 246 } 247 248 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev) 249 { 250 unsigned i; 251 252 /* Enable pflip interrupts */ 253 for (i = 0; i < adev->mode_info.num_crtc; i++) 254 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 255 } 256 257 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 258 { 259 unsigned i; 260 261 /* Disable pflip interrupts */ 262 for (i = 0; i < adev->mode_info.num_crtc; i++) 263 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 264 } 265 266 /** 267 * dce_v11_0_page_flip - pageflip callback. 268 * 269 * @adev: amdgpu_device pointer 270 * @crtc_id: crtc to cleanup pageflip on 271 * @crtc_base: new address of the crtc (GPU MC address) 272 * 273 * Triggers the actual pageflip by updating the primary 274 * surface base address. 275 */ 276 static void dce_v11_0_page_flip(struct amdgpu_device *adev, 277 int crtc_id, u64 crtc_base) 278 { 279 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 280 281 /* update the scanout addresses */ 282 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 283 upper_32_bits(crtc_base)); 284 /* writing to the low address triggers the update */ 285 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 286 lower_32_bits(crtc_base)); 287 /* post the write */ 288 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 289 } 290 291 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 292 u32 *vbl, u32 *position) 293 { 294 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 295 return -EINVAL; 296 297 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 298 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 299 300 return 0; 301 } 302 303 /** 304 * dce_v11_0_hpd_sense - hpd sense callback. 305 * 306 * @adev: amdgpu_device pointer 307 * @hpd: hpd (hotplug detect) pin 308 * 309 * Checks if a digital monitor is connected (evergreen+). 310 * Returns true if connected, false if not connected. 311 */ 312 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, 313 enum amdgpu_hpd_id hpd) 314 { 315 int idx; 316 bool connected = false; 317 318 switch (hpd) { 319 case AMDGPU_HPD_1: 320 idx = 0; 321 break; 322 case AMDGPU_HPD_2: 323 idx = 1; 324 break; 325 case AMDGPU_HPD_3: 326 idx = 2; 327 break; 328 case AMDGPU_HPD_4: 329 idx = 3; 330 break; 331 case AMDGPU_HPD_5: 332 idx = 4; 333 break; 334 case AMDGPU_HPD_6: 335 idx = 5; 336 break; 337 default: 338 return connected; 339 } 340 341 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & 342 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 343 connected = true; 344 345 return connected; 346 } 347 348 /** 349 * dce_v11_0_hpd_set_polarity - hpd set polarity callback. 350 * 351 * @adev: amdgpu_device pointer 352 * @hpd: hpd (hotplug detect) pin 353 * 354 * Set the polarity of the hpd pin (evergreen+). 355 */ 356 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev, 357 enum amdgpu_hpd_id hpd) 358 { 359 u32 tmp; 360 bool connected = dce_v11_0_hpd_sense(adev, hpd); 361 int idx; 362 363 switch (hpd) { 364 case AMDGPU_HPD_1: 365 idx = 0; 366 break; 367 case AMDGPU_HPD_2: 368 idx = 1; 369 break; 370 case AMDGPU_HPD_3: 371 idx = 2; 372 break; 373 case AMDGPU_HPD_4: 374 idx = 3; 375 break; 376 case AMDGPU_HPD_5: 377 idx = 4; 378 break; 379 case AMDGPU_HPD_6: 380 idx = 5; 381 break; 382 default: 383 return; 384 } 385 386 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); 387 if (connected) 388 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 389 else 390 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 391 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); 392 } 393 394 /** 395 * dce_v11_0_hpd_init - hpd setup callback. 396 * 397 * @adev: amdgpu_device pointer 398 * 399 * Setup the hpd pins used by the card (evergreen+). 400 * Enable the pin, set the polarity, and enable the hpd interrupts. 401 */ 402 static void dce_v11_0_hpd_init(struct amdgpu_device *adev) 403 { 404 struct drm_device *dev = adev->ddev; 405 struct drm_connector *connector; 406 u32 tmp; 407 int idx; 408 409 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 410 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 411 412 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 413 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 414 /* don't try to enable hpd on eDP or LVDS avoid breaking the 415 * aux dp channel on imac and help (but not completely fix) 416 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 417 * also avoid interrupt storms during dpms. 418 */ 419 continue; 420 } 421 422 switch (amdgpu_connector->hpd.hpd) { 423 case AMDGPU_HPD_1: 424 idx = 0; 425 break; 426 case AMDGPU_HPD_2: 427 idx = 1; 428 break; 429 case AMDGPU_HPD_3: 430 idx = 2; 431 break; 432 case AMDGPU_HPD_4: 433 idx = 3; 434 break; 435 case AMDGPU_HPD_5: 436 idx = 4; 437 break; 438 case AMDGPU_HPD_6: 439 idx = 5; 440 break; 441 default: 442 continue; 443 } 444 445 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 446 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 447 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 448 449 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); 450 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 451 DC_HPD_CONNECT_INT_DELAY, 452 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 453 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 454 DC_HPD_DISCONNECT_INT_DELAY, 455 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 456 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); 457 458 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 459 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 460 } 461 } 462 463 /** 464 * dce_v11_0_hpd_fini - hpd tear down callback. 465 * 466 * @adev: amdgpu_device pointer 467 * 468 * Tear down the hpd pins used by the card (evergreen+). 469 * Disable the hpd interrupts. 470 */ 471 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) 472 { 473 struct drm_device *dev = adev->ddev; 474 struct drm_connector *connector; 475 u32 tmp; 476 int idx; 477 478 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 479 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 480 481 switch (amdgpu_connector->hpd.hpd) { 482 case AMDGPU_HPD_1: 483 idx = 0; 484 break; 485 case AMDGPU_HPD_2: 486 idx = 1; 487 break; 488 case AMDGPU_HPD_3: 489 idx = 2; 490 break; 491 case AMDGPU_HPD_4: 492 idx = 3; 493 break; 494 case AMDGPU_HPD_5: 495 idx = 4; 496 break; 497 case AMDGPU_HPD_6: 498 idx = 5; 499 break; 500 default: 501 continue; 502 } 503 504 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 505 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 506 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 507 508 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 509 } 510 } 511 512 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 513 { 514 return mmDC_GPIO_HPD_A; 515 } 516 517 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev) 518 { 519 u32 crtc_hung = 0; 520 u32 crtc_status[6]; 521 u32 i, j, tmp; 522 523 for (i = 0; i < adev->mode_info.num_crtc; i++) { 524 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 525 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 526 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 527 crtc_hung |= (1 << i); 528 } 529 } 530 531 for (j = 0; j < 10; j++) { 532 for (i = 0; i < adev->mode_info.num_crtc; i++) { 533 if (crtc_hung & (1 << i)) { 534 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 535 if (tmp != crtc_status[i]) 536 crtc_hung &= ~(1 << i); 537 } 538 } 539 if (crtc_hung == 0) 540 return false; 541 udelay(100); 542 } 543 544 return true; 545 } 546 547 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev, 548 struct amdgpu_mode_mc_save *save) 549 { 550 u32 crtc_enabled, tmp; 551 int i; 552 553 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 554 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 555 556 /* disable VGA render */ 557 tmp = RREG32(mmVGA_RENDER_CONTROL); 558 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 559 WREG32(mmVGA_RENDER_CONTROL, tmp); 560 561 /* blank the display controllers */ 562 for (i = 0; i < adev->mode_info.num_crtc; i++) { 563 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 564 CRTC_CONTROL, CRTC_MASTER_EN); 565 if (crtc_enabled) { 566 #if 0 567 u32 frame_count; 568 int j; 569 570 save->crtc_enabled[i] = true; 571 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 572 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { 573 amdgpu_display_vblank_wait(adev, i); 574 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 575 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); 576 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 577 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 578 } 579 /* wait for the next frame */ 580 frame_count = amdgpu_display_vblank_get_counter(adev, i); 581 for (j = 0; j < adev->usec_timeout; j++) { 582 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 583 break; 584 udelay(1); 585 } 586 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 587 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { 588 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); 589 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 590 } 591 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); 592 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { 593 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); 594 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 595 } 596 #else 597 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 598 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 599 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 600 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 601 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 602 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 603 save->crtc_enabled[i] = false; 604 /* ***** */ 605 #endif 606 } else { 607 save->crtc_enabled[i] = false; 608 } 609 } 610 } 611 612 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev, 613 struct amdgpu_mode_mc_save *save) 614 { 615 u32 tmp, frame_count; 616 int i, j; 617 618 /* update crtc base addresses */ 619 for (i = 0; i < adev->mode_info.num_crtc; i++) { 620 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 621 upper_32_bits(adev->mc.vram_start)); 622 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 623 upper_32_bits(adev->mc.vram_start)); 624 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 625 (u32)adev->mc.vram_start); 626 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 627 (u32)adev->mc.vram_start); 628 629 if (save->crtc_enabled[i]) { 630 tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]); 631 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { 632 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); 633 WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); 634 } 635 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 636 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { 637 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); 638 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 639 } 640 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); 641 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { 642 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); 643 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 644 } 645 for (j = 0; j < adev->usec_timeout; j++) { 646 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 647 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) 648 break; 649 udelay(1); 650 } 651 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 652 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); 653 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 654 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 655 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 656 /* wait for the next frame */ 657 frame_count = amdgpu_display_vblank_get_counter(adev, i); 658 for (j = 0; j < adev->usec_timeout; j++) { 659 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 660 break; 661 udelay(1); 662 } 663 } 664 } 665 666 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 667 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); 668 669 /* Unlock vga access */ 670 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 671 mdelay(1); 672 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 673 } 674 675 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev, 676 bool render) 677 { 678 u32 tmp; 679 680 /* Lockout access through VGA aperture*/ 681 tmp = RREG32(mmVGA_HDP_CONTROL); 682 if (render) 683 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 684 else 685 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 686 WREG32(mmVGA_HDP_CONTROL, tmp); 687 688 /* disable VGA render */ 689 tmp = RREG32(mmVGA_RENDER_CONTROL); 690 if (render) 691 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 692 else 693 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 694 WREG32(mmVGA_RENDER_CONTROL, tmp); 695 } 696 697 static void dce_v11_0_program_fmt(struct drm_encoder *encoder) 698 { 699 struct drm_device *dev = encoder->dev; 700 struct amdgpu_device *adev = dev->dev_private; 701 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 702 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 703 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 704 int bpc = 0; 705 u32 tmp = 0; 706 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 707 708 if (connector) { 709 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 710 bpc = amdgpu_connector_get_monitor_bpc(connector); 711 dither = amdgpu_connector->dither; 712 } 713 714 /* LVDS/eDP FMT is set up by atom */ 715 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 716 return; 717 718 /* not needed for analog */ 719 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 720 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 721 return; 722 723 if (bpc == 0) 724 return; 725 726 switch (bpc) { 727 case 6: 728 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 729 /* XXX sort out optimal dither settings */ 730 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 731 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 732 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 733 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 734 } else { 735 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 736 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 737 } 738 break; 739 case 8: 740 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 741 /* XXX sort out optimal dither settings */ 742 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 743 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 744 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 745 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 746 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 747 } else { 748 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 749 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 750 } 751 break; 752 case 10: 753 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 754 /* XXX sort out optimal dither settings */ 755 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 756 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 757 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 758 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 759 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 760 } else { 761 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 762 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 763 } 764 break; 765 default: 766 /* not needed */ 767 break; 768 } 769 770 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 771 } 772 773 774 /* display watermark setup */ 775 /** 776 * dce_v11_0_line_buffer_adjust - Set up the line buffer 777 * 778 * @adev: amdgpu_device pointer 779 * @amdgpu_crtc: the selected display controller 780 * @mode: the current display mode on the selected display 781 * controller 782 * 783 * Setup up the line buffer allocation for 784 * the selected display controller (CIK). 785 * Returns the line buffer size in pixels. 786 */ 787 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, 788 struct amdgpu_crtc *amdgpu_crtc, 789 struct drm_display_mode *mode) 790 { 791 u32 tmp, buffer_alloc, i, mem_cfg; 792 u32 pipe_offset = amdgpu_crtc->crtc_id; 793 /* 794 * Line Buffer Setup 795 * There are 6 line buffers, one for each display controllers. 796 * There are 3 partitions per LB. Select the number of partitions 797 * to enable based on the display width. For display widths larger 798 * than 4096, you need use to use 2 display controllers and combine 799 * them using the stereo blender. 800 */ 801 if (amdgpu_crtc->base.enabled && mode) { 802 if (mode->crtc_hdisplay < 1920) { 803 mem_cfg = 1; 804 buffer_alloc = 2; 805 } else if (mode->crtc_hdisplay < 2560) { 806 mem_cfg = 2; 807 buffer_alloc = 2; 808 } else if (mode->crtc_hdisplay < 4096) { 809 mem_cfg = 0; 810 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 811 } else { 812 DRM_DEBUG_KMS("Mode too big for LB!\n"); 813 mem_cfg = 0; 814 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 815 } 816 } else { 817 mem_cfg = 1; 818 buffer_alloc = 0; 819 } 820 821 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 822 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 823 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 824 825 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 826 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 827 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 828 829 for (i = 0; i < adev->usec_timeout; i++) { 830 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 831 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 832 break; 833 udelay(1); 834 } 835 836 if (amdgpu_crtc->base.enabled && mode) { 837 switch (mem_cfg) { 838 case 0: 839 default: 840 return 4096 * 2; 841 case 1: 842 return 1920 * 2; 843 case 2: 844 return 2560 * 2; 845 } 846 } 847 848 /* controller not enabled, so no lb used */ 849 return 0; 850 } 851 852 /** 853 * cik_get_number_of_dram_channels - get the number of dram channels 854 * 855 * @adev: amdgpu_device pointer 856 * 857 * Look up the number of video ram channels (CIK). 858 * Used for display watermark bandwidth calculations 859 * Returns the number of dram channels 860 */ 861 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 862 { 863 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 864 865 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 866 case 0: 867 default: 868 return 1; 869 case 1: 870 return 2; 871 case 2: 872 return 4; 873 case 3: 874 return 8; 875 case 4: 876 return 3; 877 case 5: 878 return 6; 879 case 6: 880 return 10; 881 case 7: 882 return 12; 883 case 8: 884 return 16; 885 } 886 } 887 888 struct dce10_wm_params { 889 u32 dram_channels; /* number of dram channels */ 890 u32 yclk; /* bandwidth per dram data pin in kHz */ 891 u32 sclk; /* engine clock in kHz */ 892 u32 disp_clk; /* display clock in kHz */ 893 u32 src_width; /* viewport width */ 894 u32 active_time; /* active display time in ns */ 895 u32 blank_time; /* blank time in ns */ 896 bool interlaced; /* mode is interlaced */ 897 fixed20_12 vsc; /* vertical scale ratio */ 898 u32 num_heads; /* number of active crtcs */ 899 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 900 u32 lb_size; /* line buffer allocated to pipe */ 901 u32 vtaps; /* vertical scaler taps */ 902 }; 903 904 /** 905 * dce_v11_0_dram_bandwidth - get the dram bandwidth 906 * 907 * @wm: watermark calculation data 908 * 909 * Calculate the raw dram bandwidth (CIK). 910 * Used for display watermark bandwidth calculations 911 * Returns the dram bandwidth in MBytes/s 912 */ 913 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) 914 { 915 /* Calculate raw DRAM Bandwidth */ 916 fixed20_12 dram_efficiency; /* 0.7 */ 917 fixed20_12 yclk, dram_channels, bandwidth; 918 fixed20_12 a; 919 920 a.full = dfixed_const(1000); 921 yclk.full = dfixed_const(wm->yclk); 922 yclk.full = dfixed_div(yclk, a); 923 dram_channels.full = dfixed_const(wm->dram_channels * 4); 924 a.full = dfixed_const(10); 925 dram_efficiency.full = dfixed_const(7); 926 dram_efficiency.full = dfixed_div(dram_efficiency, a); 927 bandwidth.full = dfixed_mul(dram_channels, yclk); 928 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 929 930 return dfixed_trunc(bandwidth); 931 } 932 933 /** 934 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display 935 * 936 * @wm: watermark calculation data 937 * 938 * Calculate the dram bandwidth used for display (CIK). 939 * Used for display watermark bandwidth calculations 940 * Returns the dram bandwidth for display in MBytes/s 941 */ 942 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 943 { 944 /* Calculate DRAM Bandwidth and the part allocated to display. */ 945 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 946 fixed20_12 yclk, dram_channels, bandwidth; 947 fixed20_12 a; 948 949 a.full = dfixed_const(1000); 950 yclk.full = dfixed_const(wm->yclk); 951 yclk.full = dfixed_div(yclk, a); 952 dram_channels.full = dfixed_const(wm->dram_channels * 4); 953 a.full = dfixed_const(10); 954 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 955 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 956 bandwidth.full = dfixed_mul(dram_channels, yclk); 957 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 958 959 return dfixed_trunc(bandwidth); 960 } 961 962 /** 963 * dce_v11_0_data_return_bandwidth - get the data return bandwidth 964 * 965 * @wm: watermark calculation data 966 * 967 * Calculate the data return bandwidth used for display (CIK). 968 * Used for display watermark bandwidth calculations 969 * Returns the data return bandwidth in MBytes/s 970 */ 971 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) 972 { 973 /* Calculate the display Data return Bandwidth */ 974 fixed20_12 return_efficiency; /* 0.8 */ 975 fixed20_12 sclk, bandwidth; 976 fixed20_12 a; 977 978 a.full = dfixed_const(1000); 979 sclk.full = dfixed_const(wm->sclk); 980 sclk.full = dfixed_div(sclk, a); 981 a.full = dfixed_const(10); 982 return_efficiency.full = dfixed_const(8); 983 return_efficiency.full = dfixed_div(return_efficiency, a); 984 a.full = dfixed_const(32); 985 bandwidth.full = dfixed_mul(a, sclk); 986 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 987 988 return dfixed_trunc(bandwidth); 989 } 990 991 /** 992 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth 993 * 994 * @wm: watermark calculation data 995 * 996 * Calculate the dmif bandwidth used for display (CIK). 997 * Used for display watermark bandwidth calculations 998 * Returns the dmif bandwidth in MBytes/s 999 */ 1000 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 1001 { 1002 /* Calculate the DMIF Request Bandwidth */ 1003 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 1004 fixed20_12 disp_clk, bandwidth; 1005 fixed20_12 a, b; 1006 1007 a.full = dfixed_const(1000); 1008 disp_clk.full = dfixed_const(wm->disp_clk); 1009 disp_clk.full = dfixed_div(disp_clk, a); 1010 a.full = dfixed_const(32); 1011 b.full = dfixed_mul(a, disp_clk); 1012 1013 a.full = dfixed_const(10); 1014 disp_clk_request_efficiency.full = dfixed_const(8); 1015 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 1016 1017 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 1018 1019 return dfixed_trunc(bandwidth); 1020 } 1021 1022 /** 1023 * dce_v11_0_available_bandwidth - get the min available bandwidth 1024 * 1025 * @wm: watermark calculation data 1026 * 1027 * Calculate the min available bandwidth used for display (CIK). 1028 * Used for display watermark bandwidth calculations 1029 * Returns the min available bandwidth in MBytes/s 1030 */ 1031 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm) 1032 { 1033 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 1034 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm); 1035 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm); 1036 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm); 1037 1038 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 1039 } 1040 1041 /** 1042 * dce_v11_0_average_bandwidth - get the average available bandwidth 1043 * 1044 * @wm: watermark calculation data 1045 * 1046 * Calculate the average available bandwidth used for display (CIK). 1047 * Used for display watermark bandwidth calculations 1048 * Returns the average available bandwidth in MBytes/s 1049 */ 1050 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm) 1051 { 1052 /* Calculate the display mode Average Bandwidth 1053 * DisplayMode should contain the source and destination dimensions, 1054 * timing, etc. 1055 */ 1056 fixed20_12 bpp; 1057 fixed20_12 line_time; 1058 fixed20_12 src_width; 1059 fixed20_12 bandwidth; 1060 fixed20_12 a; 1061 1062 a.full = dfixed_const(1000); 1063 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 1064 line_time.full = dfixed_div(line_time, a); 1065 bpp.full = dfixed_const(wm->bytes_per_pixel); 1066 src_width.full = dfixed_const(wm->src_width); 1067 bandwidth.full = dfixed_mul(src_width, bpp); 1068 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 1069 bandwidth.full = dfixed_div(bandwidth, line_time); 1070 1071 return dfixed_trunc(bandwidth); 1072 } 1073 1074 /** 1075 * dce_v11_0_latency_watermark - get the latency watermark 1076 * 1077 * @wm: watermark calculation data 1078 * 1079 * Calculate the latency watermark (CIK). 1080 * Used for display watermark bandwidth calculations 1081 * Returns the latency watermark in ns 1082 */ 1083 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm) 1084 { 1085 /* First calculate the latency in ns */ 1086 u32 mc_latency = 2000; /* 2000 ns. */ 1087 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm); 1088 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 1089 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 1090 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 1091 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 1092 (wm->num_heads * cursor_line_pair_return_time); 1093 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 1094 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 1095 u32 tmp, dmif_size = 12288; 1096 fixed20_12 a, b, c; 1097 1098 if (wm->num_heads == 0) 1099 return 0; 1100 1101 a.full = dfixed_const(2); 1102 b.full = dfixed_const(1); 1103 if ((wm->vsc.full > a.full) || 1104 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 1105 (wm->vtaps >= 5) || 1106 ((wm->vsc.full >= a.full) && wm->interlaced)) 1107 max_src_lines_per_dst_line = 4; 1108 else 1109 max_src_lines_per_dst_line = 2; 1110 1111 a.full = dfixed_const(available_bandwidth); 1112 b.full = dfixed_const(wm->num_heads); 1113 a.full = dfixed_div(a, b); 1114 1115 b.full = dfixed_const(mc_latency + 512); 1116 c.full = dfixed_const(wm->disp_clk); 1117 b.full = dfixed_div(b, c); 1118 1119 c.full = dfixed_const(dmif_size); 1120 b.full = dfixed_div(c, b); 1121 1122 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 1123 1124 b.full = dfixed_const(1000); 1125 c.full = dfixed_const(wm->disp_clk); 1126 b.full = dfixed_div(c, b); 1127 c.full = dfixed_const(wm->bytes_per_pixel); 1128 b.full = dfixed_mul(b, c); 1129 1130 lb_fill_bw = min(tmp, dfixed_trunc(b)); 1131 1132 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1133 b.full = dfixed_const(1000); 1134 c.full = dfixed_const(lb_fill_bw); 1135 b.full = dfixed_div(c, b); 1136 a.full = dfixed_div(a, b); 1137 line_fill_time = dfixed_trunc(a); 1138 1139 if (line_fill_time < wm->active_time) 1140 return latency; 1141 else 1142 return latency + (line_fill_time - wm->active_time); 1143 1144 } 1145 1146 /** 1147 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check 1148 * average and available dram bandwidth 1149 * 1150 * @wm: watermark calculation data 1151 * 1152 * Check if the display average bandwidth fits in the display 1153 * dram bandwidth (CIK). 1154 * Used for display watermark bandwidth calculations 1155 * Returns true if the display fits, false if not. 1156 */ 1157 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 1158 { 1159 if (dce_v11_0_average_bandwidth(wm) <= 1160 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 1161 return true; 1162 else 1163 return false; 1164 } 1165 1166 /** 1167 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check 1168 * average and available bandwidth 1169 * 1170 * @wm: watermark calculation data 1171 * 1172 * Check if the display average bandwidth fits in the display 1173 * available bandwidth (CIK). 1174 * Used for display watermark bandwidth calculations 1175 * Returns true if the display fits, false if not. 1176 */ 1177 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 1178 { 1179 if (dce_v11_0_average_bandwidth(wm) <= 1180 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) 1181 return true; 1182 else 1183 return false; 1184 } 1185 1186 /** 1187 * dce_v11_0_check_latency_hiding - check latency hiding 1188 * 1189 * @wm: watermark calculation data 1190 * 1191 * Check latency hiding (CIK). 1192 * Used for display watermark bandwidth calculations 1193 * Returns true if the display fits, false if not. 1194 */ 1195 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm) 1196 { 1197 u32 lb_partitions = wm->lb_size / wm->src_width; 1198 u32 line_time = wm->active_time + wm->blank_time; 1199 u32 latency_tolerant_lines; 1200 u32 latency_hiding; 1201 fixed20_12 a; 1202 1203 a.full = dfixed_const(1); 1204 if (wm->vsc.full > a.full) 1205 latency_tolerant_lines = 1; 1206 else { 1207 if (lb_partitions <= (wm->vtaps + 1)) 1208 latency_tolerant_lines = 1; 1209 else 1210 latency_tolerant_lines = 2; 1211 } 1212 1213 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1214 1215 if (dce_v11_0_latency_watermark(wm) <= latency_hiding) 1216 return true; 1217 else 1218 return false; 1219 } 1220 1221 /** 1222 * dce_v11_0_program_watermarks - program display watermarks 1223 * 1224 * @adev: amdgpu_device pointer 1225 * @amdgpu_crtc: the selected display controller 1226 * @lb_size: line buffer size 1227 * @num_heads: number of display controllers in use 1228 * 1229 * Calculate and program the display watermarks for the 1230 * selected display controller (CIK). 1231 */ 1232 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, 1233 struct amdgpu_crtc *amdgpu_crtc, 1234 u32 lb_size, u32 num_heads) 1235 { 1236 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1237 struct dce10_wm_params wm_low, wm_high; 1238 u32 pixel_period; 1239 u32 line_time = 0; 1240 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1241 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1242 1243 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1244 pixel_period = 1000000 / (u32)mode->clock; 1245 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1246 1247 /* watermark for high clocks */ 1248 if (adev->pm.dpm_enabled) { 1249 wm_high.yclk = 1250 amdgpu_dpm_get_mclk(adev, false) * 10; 1251 wm_high.sclk = 1252 amdgpu_dpm_get_sclk(adev, false) * 10; 1253 } else { 1254 wm_high.yclk = adev->pm.current_mclk * 10; 1255 wm_high.sclk = adev->pm.current_sclk * 10; 1256 } 1257 1258 wm_high.disp_clk = mode->clock; 1259 wm_high.src_width = mode->crtc_hdisplay; 1260 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1261 wm_high.blank_time = line_time - wm_high.active_time; 1262 wm_high.interlaced = false; 1263 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1264 wm_high.interlaced = true; 1265 wm_high.vsc = amdgpu_crtc->vsc; 1266 wm_high.vtaps = 1; 1267 if (amdgpu_crtc->rmx_type != RMX_OFF) 1268 wm_high.vtaps = 2; 1269 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1270 wm_high.lb_size = lb_size; 1271 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1272 wm_high.num_heads = num_heads; 1273 1274 /* set for high clocks */ 1275 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535); 1276 1277 /* possibly force display priority to high */ 1278 /* should really do this at mode validation time... */ 1279 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1280 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1281 !dce_v11_0_check_latency_hiding(&wm_high) || 1282 (adev->mode_info.disp_priority == 2)) { 1283 DRM_DEBUG_KMS("force priority to high\n"); 1284 } 1285 1286 /* watermark for low clocks */ 1287 if (adev->pm.dpm_enabled) { 1288 wm_low.yclk = 1289 amdgpu_dpm_get_mclk(adev, true) * 10; 1290 wm_low.sclk = 1291 amdgpu_dpm_get_sclk(adev, true) * 10; 1292 } else { 1293 wm_low.yclk = adev->pm.current_mclk * 10; 1294 wm_low.sclk = adev->pm.current_sclk * 10; 1295 } 1296 1297 wm_low.disp_clk = mode->clock; 1298 wm_low.src_width = mode->crtc_hdisplay; 1299 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1300 wm_low.blank_time = line_time - wm_low.active_time; 1301 wm_low.interlaced = false; 1302 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1303 wm_low.interlaced = true; 1304 wm_low.vsc = amdgpu_crtc->vsc; 1305 wm_low.vtaps = 1; 1306 if (amdgpu_crtc->rmx_type != RMX_OFF) 1307 wm_low.vtaps = 2; 1308 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1309 wm_low.lb_size = lb_size; 1310 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1311 wm_low.num_heads = num_heads; 1312 1313 /* set for low clocks */ 1314 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535); 1315 1316 /* possibly force display priority to high */ 1317 /* should really do this at mode validation time... */ 1318 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1319 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1320 !dce_v11_0_check_latency_hiding(&wm_low) || 1321 (adev->mode_info.disp_priority == 2)) { 1322 DRM_DEBUG_KMS("force priority to high\n"); 1323 } 1324 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1325 } 1326 1327 /* select wm A */ 1328 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1329 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1330 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1331 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1332 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1333 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1334 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1335 /* select wm B */ 1336 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1337 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1338 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1339 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); 1340 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1341 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1342 /* restore original selection */ 1343 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1344 1345 /* save values for DPM */ 1346 amdgpu_crtc->line_time = line_time; 1347 amdgpu_crtc->wm_high = latency_watermark_a; 1348 amdgpu_crtc->wm_low = latency_watermark_b; 1349 /* Save number of lines the linebuffer leads before the scanout */ 1350 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1351 } 1352 1353 /** 1354 * dce_v11_0_bandwidth_update - program display watermarks 1355 * 1356 * @adev: amdgpu_device pointer 1357 * 1358 * Calculate and program the display watermarks and line 1359 * buffer allocation (CIK). 1360 */ 1361 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev) 1362 { 1363 struct drm_display_mode *mode = NULL; 1364 u32 num_heads = 0, lb_size; 1365 int i; 1366 1367 amdgpu_update_display_priority(adev); 1368 1369 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1370 if (adev->mode_info.crtcs[i]->base.enabled) 1371 num_heads++; 1372 } 1373 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1374 mode = &adev->mode_info.crtcs[i]->base.mode; 1375 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1376 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1377 lb_size, num_heads); 1378 } 1379 } 1380 1381 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev) 1382 { 1383 int i; 1384 u32 offset, tmp; 1385 1386 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1387 offset = adev->mode_info.audio.pin[i].offset; 1388 tmp = RREG32_AUDIO_ENDPT(offset, 1389 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1390 if (((tmp & 1391 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1392 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1393 adev->mode_info.audio.pin[i].connected = false; 1394 else 1395 adev->mode_info.audio.pin[i].connected = true; 1396 } 1397 } 1398 1399 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev) 1400 { 1401 int i; 1402 1403 dce_v11_0_audio_get_connected_pins(adev); 1404 1405 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1406 if (adev->mode_info.audio.pin[i].connected) 1407 return &adev->mode_info.audio.pin[i]; 1408 } 1409 DRM_ERROR("No connected audio pins found!\n"); 1410 return NULL; 1411 } 1412 1413 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1414 { 1415 struct amdgpu_device *adev = encoder->dev->dev_private; 1416 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1417 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1418 u32 tmp; 1419 1420 if (!dig || !dig->afmt || !dig->afmt->pin) 1421 return; 1422 1423 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1424 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1425 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1426 } 1427 1428 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, 1429 struct drm_display_mode *mode) 1430 { 1431 struct amdgpu_device *adev = encoder->dev->dev_private; 1432 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1433 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1434 struct drm_connector *connector; 1435 struct amdgpu_connector *amdgpu_connector = NULL; 1436 u32 tmp; 1437 int interlace = 0; 1438 1439 if (!dig || !dig->afmt || !dig->afmt->pin) 1440 return; 1441 1442 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1443 if (connector->encoder == encoder) { 1444 amdgpu_connector = to_amdgpu_connector(connector); 1445 break; 1446 } 1447 } 1448 1449 if (!amdgpu_connector) { 1450 DRM_ERROR("Couldn't find encoder's connector\n"); 1451 return; 1452 } 1453 1454 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1455 interlace = 1; 1456 if (connector->latency_present[interlace]) { 1457 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1458 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1459 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1460 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1461 } else { 1462 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1463 VIDEO_LIPSYNC, 0); 1464 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1465 AUDIO_LIPSYNC, 0); 1466 } 1467 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1468 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1469 } 1470 1471 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1472 { 1473 struct amdgpu_device *adev = encoder->dev->dev_private; 1474 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1475 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1476 struct drm_connector *connector; 1477 struct amdgpu_connector *amdgpu_connector = NULL; 1478 u32 tmp; 1479 u8 *sadb = NULL; 1480 int sad_count; 1481 1482 if (!dig || !dig->afmt || !dig->afmt->pin) 1483 return; 1484 1485 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1486 if (connector->encoder == encoder) { 1487 amdgpu_connector = to_amdgpu_connector(connector); 1488 break; 1489 } 1490 } 1491 1492 if (!amdgpu_connector) { 1493 DRM_ERROR("Couldn't find encoder's connector\n"); 1494 return; 1495 } 1496 1497 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1498 if (sad_count < 0) { 1499 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1500 sad_count = 0; 1501 } 1502 1503 /* program the speaker allocation */ 1504 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1505 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1506 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1507 DP_CONNECTION, 0); 1508 /* set HDMI mode */ 1509 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1510 HDMI_CONNECTION, 1); 1511 if (sad_count) 1512 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1513 SPEAKER_ALLOCATION, sadb[0]); 1514 else 1515 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1516 SPEAKER_ALLOCATION, 5); /* stereo */ 1517 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1518 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1519 1520 kfree(sadb); 1521 } 1522 1523 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) 1524 { 1525 struct amdgpu_device *adev = encoder->dev->dev_private; 1526 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1527 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1528 struct drm_connector *connector; 1529 struct amdgpu_connector *amdgpu_connector = NULL; 1530 struct cea_sad *sads; 1531 int i, sad_count; 1532 1533 static const u16 eld_reg_to_type[][2] = { 1534 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1535 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1536 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1537 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1538 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1539 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1540 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1541 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1542 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1543 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1544 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1545 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1546 }; 1547 1548 if (!dig || !dig->afmt || !dig->afmt->pin) 1549 return; 1550 1551 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1552 if (connector->encoder == encoder) { 1553 amdgpu_connector = to_amdgpu_connector(connector); 1554 break; 1555 } 1556 } 1557 1558 if (!amdgpu_connector) { 1559 DRM_ERROR("Couldn't find encoder's connector\n"); 1560 return; 1561 } 1562 1563 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1564 if (sad_count <= 0) { 1565 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1566 return; 1567 } 1568 BUG_ON(!sads); 1569 1570 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1571 u32 tmp = 0; 1572 u8 stereo_freqs = 0; 1573 int max_channels = -1; 1574 int j; 1575 1576 for (j = 0; j < sad_count; j++) { 1577 struct cea_sad *sad = &sads[j]; 1578 1579 if (sad->format == eld_reg_to_type[i][1]) { 1580 if (sad->channels > max_channels) { 1581 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1582 MAX_CHANNELS, sad->channels); 1583 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1584 DESCRIPTOR_BYTE_2, sad->byte2); 1585 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1586 SUPPORTED_FREQUENCIES, sad->freq); 1587 max_channels = sad->channels; 1588 } 1589 1590 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1591 stereo_freqs |= sad->freq; 1592 else 1593 break; 1594 } 1595 } 1596 1597 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1598 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1599 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1600 } 1601 1602 kfree(sads); 1603 } 1604 1605 static void dce_v11_0_audio_enable(struct amdgpu_device *adev, 1606 struct amdgpu_audio_pin *pin, 1607 bool enable) 1608 { 1609 if (!pin) 1610 return; 1611 1612 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1613 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1614 } 1615 1616 static const u32 pin_offsets[] = 1617 { 1618 AUD0_REGISTER_OFFSET, 1619 AUD1_REGISTER_OFFSET, 1620 AUD2_REGISTER_OFFSET, 1621 AUD3_REGISTER_OFFSET, 1622 AUD4_REGISTER_OFFSET, 1623 AUD5_REGISTER_OFFSET, 1624 AUD6_REGISTER_OFFSET, 1625 }; 1626 1627 static int dce_v11_0_audio_init(struct amdgpu_device *adev) 1628 { 1629 int i; 1630 1631 if (!amdgpu_audio) 1632 return 0; 1633 1634 adev->mode_info.audio.enabled = true; 1635 1636 adev->mode_info.audio.num_pins = 7; 1637 1638 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1639 adev->mode_info.audio.pin[i].channels = -1; 1640 adev->mode_info.audio.pin[i].rate = -1; 1641 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1642 adev->mode_info.audio.pin[i].status_bits = 0; 1643 adev->mode_info.audio.pin[i].category_code = 0; 1644 adev->mode_info.audio.pin[i].connected = false; 1645 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1646 adev->mode_info.audio.pin[i].id = i; 1647 /* disable audio. it will be set up later */ 1648 /* XXX remove once we switch to ip funcs */ 1649 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1650 } 1651 1652 return 0; 1653 } 1654 1655 static void dce_v11_0_audio_fini(struct amdgpu_device *adev) 1656 { 1657 int i; 1658 1659 if (!adev->mode_info.audio.enabled) 1660 return; 1661 1662 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1663 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1664 1665 adev->mode_info.audio.enabled = false; 1666 } 1667 1668 /* 1669 * update the N and CTS parameters for a given pixel clock rate 1670 */ 1671 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1672 { 1673 struct drm_device *dev = encoder->dev; 1674 struct amdgpu_device *adev = dev->dev_private; 1675 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1676 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1677 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1678 u32 tmp; 1679 1680 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1681 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1682 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1683 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1684 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1685 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1686 1687 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1688 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1689 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1690 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1691 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1692 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1693 1694 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1695 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1696 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1697 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1698 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1699 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1700 1701 } 1702 1703 /* 1704 * build a HDMI Video Info Frame 1705 */ 1706 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1707 void *buffer, size_t size) 1708 { 1709 struct drm_device *dev = encoder->dev; 1710 struct amdgpu_device *adev = dev->dev_private; 1711 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1712 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1713 uint8_t *frame = buffer + 3; 1714 uint8_t *header = buffer; 1715 1716 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1717 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1718 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1719 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1720 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1721 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1722 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1723 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1724 } 1725 1726 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1727 { 1728 struct drm_device *dev = encoder->dev; 1729 struct amdgpu_device *adev = dev->dev_private; 1730 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1731 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1732 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1733 u32 dto_phase = 24 * 1000; 1734 u32 dto_modulo = clock; 1735 u32 tmp; 1736 1737 if (!dig || !dig->afmt) 1738 return; 1739 1740 /* XXX two dtos; generally use dto0 for hdmi */ 1741 /* Express [24MHz / target pixel clock] as an exact rational 1742 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1743 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1744 */ 1745 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1746 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1747 amdgpu_crtc->crtc_id); 1748 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1749 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1750 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1751 } 1752 1753 /* 1754 * update the info frames with the data from the current display mode 1755 */ 1756 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, 1757 struct drm_display_mode *mode) 1758 { 1759 struct drm_device *dev = encoder->dev; 1760 struct amdgpu_device *adev = dev->dev_private; 1761 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1762 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1763 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1764 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1765 struct hdmi_avi_infoframe frame; 1766 ssize_t err; 1767 u32 tmp; 1768 int bpc = 8; 1769 1770 if (!dig || !dig->afmt) 1771 return; 1772 1773 /* Silent, r600_hdmi_enable will raise WARN for us */ 1774 if (!dig->afmt->enabled) 1775 return; 1776 1777 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1778 if (encoder->crtc) { 1779 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1780 bpc = amdgpu_crtc->bpc; 1781 } 1782 1783 /* disable audio prior to setting up hw */ 1784 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); 1785 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1786 1787 dce_v11_0_audio_set_dto(encoder, mode->clock); 1788 1789 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1790 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1791 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1792 1793 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1794 1795 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1796 switch (bpc) { 1797 case 0: 1798 case 6: 1799 case 8: 1800 case 16: 1801 default: 1802 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1803 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1804 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1805 connector->name, bpc); 1806 break; 1807 case 10: 1808 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1809 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1810 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1811 connector->name); 1812 break; 1813 case 12: 1814 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1815 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1816 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1817 connector->name); 1818 break; 1819 } 1820 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1821 1822 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1823 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1824 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1825 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1826 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1827 1828 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1829 /* enable audio info frames (frames won't be set until audio is enabled) */ 1830 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1831 /* required for audio info values to be updated */ 1832 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1833 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1834 1835 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1836 /* required for audio info values to be updated */ 1837 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1838 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1839 1840 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1841 /* anything other than 0 */ 1842 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1843 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1844 1845 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1846 1847 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1848 /* set the default audio delay */ 1849 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1850 /* should be suffient for all audio modes and small enough for all hblanks */ 1851 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1852 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1853 1854 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1855 /* allow 60958 channel status fields to be updated */ 1856 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1857 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1858 1859 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1860 if (bpc > 8) 1861 /* clear SW CTS value */ 1862 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1863 else 1864 /* select SW CTS value */ 1865 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1866 /* allow hw to sent ACR packets when required */ 1867 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1868 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1869 1870 dce_v11_0_afmt_update_ACR(encoder, mode->clock); 1871 1872 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1873 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1874 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1875 1876 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1877 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1878 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1879 1880 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1881 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1882 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1883 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1884 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1885 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1886 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1887 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1888 1889 dce_v11_0_audio_write_speaker_allocation(encoder); 1890 1891 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1892 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1893 1894 dce_v11_0_afmt_audio_select_pin(encoder); 1895 dce_v11_0_audio_write_sad_regs(encoder); 1896 dce_v11_0_audio_write_latency_fields(encoder, mode); 1897 1898 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1899 if (err < 0) { 1900 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1901 return; 1902 } 1903 1904 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1905 if (err < 0) { 1906 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1907 return; 1908 } 1909 1910 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1911 1912 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1913 /* enable AVI info frames */ 1914 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1915 /* required for audio info values to be updated */ 1916 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1917 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1918 1919 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1920 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1921 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1922 1923 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1924 /* send audio packets */ 1925 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1926 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1927 1928 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1929 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1930 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1931 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1932 1933 /* enable audio after to setting up hw */ 1934 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); 1935 } 1936 1937 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1938 { 1939 struct drm_device *dev = encoder->dev; 1940 struct amdgpu_device *adev = dev->dev_private; 1941 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1942 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1943 1944 if (!dig || !dig->afmt) 1945 return; 1946 1947 /* Silent, r600_hdmi_enable will raise WARN for us */ 1948 if (enable && dig->afmt->enabled) 1949 return; 1950 if (!enable && !dig->afmt->enabled) 1951 return; 1952 1953 if (!enable && dig->afmt->pin) { 1954 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1955 dig->afmt->pin = NULL; 1956 } 1957 1958 dig->afmt->enabled = enable; 1959 1960 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1961 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1962 } 1963 1964 static void dce_v11_0_afmt_init(struct amdgpu_device *adev) 1965 { 1966 int i; 1967 1968 for (i = 0; i < adev->mode_info.num_dig; i++) 1969 adev->mode_info.afmt[i] = NULL; 1970 1971 /* DCE11 has audio blocks tied to DIG encoders */ 1972 for (i = 0; i < adev->mode_info.num_dig; i++) { 1973 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1974 if (adev->mode_info.afmt[i]) { 1975 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1976 adev->mode_info.afmt[i]->id = i; 1977 } 1978 } 1979 } 1980 1981 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev) 1982 { 1983 int i; 1984 1985 for (i = 0; i < adev->mode_info.num_dig; i++) { 1986 kfree(adev->mode_info.afmt[i]); 1987 adev->mode_info.afmt[i] = NULL; 1988 } 1989 } 1990 1991 static const u32 vga_control_regs[6] = 1992 { 1993 mmD1VGA_CONTROL, 1994 mmD2VGA_CONTROL, 1995 mmD3VGA_CONTROL, 1996 mmD4VGA_CONTROL, 1997 mmD5VGA_CONTROL, 1998 mmD6VGA_CONTROL, 1999 }; 2000 2001 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable) 2002 { 2003 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2004 struct drm_device *dev = crtc->dev; 2005 struct amdgpu_device *adev = dev->dev_private; 2006 u32 vga_control; 2007 2008 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 2009 if (enable) 2010 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 2011 else 2012 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 2013 } 2014 2015 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) 2016 { 2017 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2018 struct drm_device *dev = crtc->dev; 2019 struct amdgpu_device *adev = dev->dev_private; 2020 2021 if (enable) 2022 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 2023 else 2024 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 2025 } 2026 2027 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, 2028 struct drm_framebuffer *fb, 2029 int x, int y, int atomic) 2030 { 2031 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2032 struct drm_device *dev = crtc->dev; 2033 struct amdgpu_device *adev = dev->dev_private; 2034 struct amdgpu_framebuffer *amdgpu_fb; 2035 struct drm_framebuffer *target_fb; 2036 struct drm_gem_object *obj; 2037 struct amdgpu_bo *rbo; 2038 uint64_t fb_location, tiling_flags; 2039 uint32_t fb_format, fb_pitch_pixels; 2040 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 2041 u32 pipe_config; 2042 u32 tmp, viewport_w, viewport_h; 2043 int r; 2044 bool bypass_lut = false; 2045 2046 /* no fb bound */ 2047 if (!atomic && !crtc->primary->fb) { 2048 DRM_DEBUG_KMS("No FB bound\n"); 2049 return 0; 2050 } 2051 2052 if (atomic) { 2053 amdgpu_fb = to_amdgpu_framebuffer(fb); 2054 target_fb = fb; 2055 } 2056 else { 2057 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2058 target_fb = crtc->primary->fb; 2059 } 2060 2061 /* If atomic, assume fb object is pinned & idle & fenced and 2062 * just update base pointers 2063 */ 2064 obj = amdgpu_fb->obj; 2065 rbo = gem_to_amdgpu_bo(obj); 2066 r = amdgpu_bo_reserve(rbo, false); 2067 if (unlikely(r != 0)) 2068 return r; 2069 2070 if (atomic) 2071 fb_location = amdgpu_bo_gpu_offset(rbo); 2072 else { 2073 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2074 if (unlikely(r != 0)) { 2075 amdgpu_bo_unreserve(rbo); 2076 return -EINVAL; 2077 } 2078 } 2079 2080 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 2081 amdgpu_bo_unreserve(rbo); 2082 2083 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2084 2085 switch (target_fb->pixel_format) { 2086 case DRM_FORMAT_C8: 2087 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 2088 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2089 break; 2090 case DRM_FORMAT_XRGB4444: 2091 case DRM_FORMAT_ARGB4444: 2092 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2093 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 2094 #ifdef __BIG_ENDIAN 2095 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2096 ENDIAN_8IN16); 2097 #endif 2098 break; 2099 case DRM_FORMAT_XRGB1555: 2100 case DRM_FORMAT_ARGB1555: 2101 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2102 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2103 #ifdef __BIG_ENDIAN 2104 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2105 ENDIAN_8IN16); 2106 #endif 2107 break; 2108 case DRM_FORMAT_BGRX5551: 2109 case DRM_FORMAT_BGRA5551: 2110 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2111 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 2112 #ifdef __BIG_ENDIAN 2113 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2114 ENDIAN_8IN16); 2115 #endif 2116 break; 2117 case DRM_FORMAT_RGB565: 2118 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2119 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2120 #ifdef __BIG_ENDIAN 2121 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2122 ENDIAN_8IN16); 2123 #endif 2124 break; 2125 case DRM_FORMAT_XRGB8888: 2126 case DRM_FORMAT_ARGB8888: 2127 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2128 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2129 #ifdef __BIG_ENDIAN 2130 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2131 ENDIAN_8IN32); 2132 #endif 2133 break; 2134 case DRM_FORMAT_XRGB2101010: 2135 case DRM_FORMAT_ARGB2101010: 2136 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2137 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2138 #ifdef __BIG_ENDIAN 2139 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2140 ENDIAN_8IN32); 2141 #endif 2142 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2143 bypass_lut = true; 2144 break; 2145 case DRM_FORMAT_BGRX1010102: 2146 case DRM_FORMAT_BGRA1010102: 2147 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2148 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 2149 #ifdef __BIG_ENDIAN 2150 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2151 ENDIAN_8IN32); 2152 #endif 2153 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2154 bypass_lut = true; 2155 break; 2156 default: 2157 DRM_ERROR("Unsupported screen format %s\n", 2158 drm_get_format_name(target_fb->pixel_format)); 2159 return -EINVAL; 2160 } 2161 2162 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2163 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2164 2165 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2166 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2167 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2168 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2169 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2170 2171 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 2172 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2173 ARRAY_2D_TILED_THIN1); 2174 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 2175 tile_split); 2176 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 2177 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 2178 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 2179 mtaspect); 2180 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 2181 ADDR_SURF_MICRO_TILING_DISPLAY); 2182 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2183 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2184 ARRAY_1D_TILED_THIN1); 2185 } 2186 2187 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 2188 pipe_config); 2189 2190 dce_v11_0_vga_enable(crtc, false); 2191 2192 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2193 upper_32_bits(fb_location)); 2194 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2195 upper_32_bits(fb_location)); 2196 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2197 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2198 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2199 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2200 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2201 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2202 2203 /* 2204 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2205 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2206 * retain the full precision throughout the pipeline. 2207 */ 2208 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2209 if (bypass_lut) 2210 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2211 else 2212 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2213 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2214 2215 if (bypass_lut) 2216 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2217 2218 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2219 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2220 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2221 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2222 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2223 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2224 2225 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 2226 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2227 2228 dce_v11_0_grph_enable(crtc, true); 2229 2230 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2231 target_fb->height); 2232 2233 x &= ~3; 2234 y &= ~1; 2235 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2236 (x << 16) | y); 2237 viewport_w = crtc->mode.hdisplay; 2238 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2239 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2240 (viewport_w << 16) | viewport_h); 2241 2242 /* pageflip setup */ 2243 /* make sure flip is at vb rather than hb */ 2244 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2245 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 2246 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 2247 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2248 2249 /* set pageflip to happen only at start of vblank interval (front porch) */ 2250 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); 2251 2252 if (!atomic && fb && fb != crtc->primary->fb) { 2253 amdgpu_fb = to_amdgpu_framebuffer(fb); 2254 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2255 r = amdgpu_bo_reserve(rbo, false); 2256 if (unlikely(r != 0)) 2257 return r; 2258 amdgpu_bo_unpin(rbo); 2259 amdgpu_bo_unreserve(rbo); 2260 } 2261 2262 /* Bytes per pixel may have changed */ 2263 dce_v11_0_bandwidth_update(adev); 2264 2265 return 0; 2266 } 2267 2268 static void dce_v11_0_set_interleave(struct drm_crtc *crtc, 2269 struct drm_display_mode *mode) 2270 { 2271 struct drm_device *dev = crtc->dev; 2272 struct amdgpu_device *adev = dev->dev_private; 2273 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2274 u32 tmp; 2275 2276 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2277 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2278 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2279 else 2280 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2281 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2282 } 2283 2284 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc) 2285 { 2286 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2287 struct drm_device *dev = crtc->dev; 2288 struct amdgpu_device *adev = dev->dev_private; 2289 int i; 2290 u32 tmp; 2291 2292 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2293 2294 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2295 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2296 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2297 2298 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2299 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2300 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2301 2302 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2303 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2304 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2305 2306 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2307 2308 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2309 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2310 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2311 2312 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2313 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2314 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2315 2316 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2317 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2318 2319 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2320 for (i = 0; i < 256; i++) { 2321 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2322 (amdgpu_crtc->lut_r[i] << 20) | 2323 (amdgpu_crtc->lut_g[i] << 10) | 2324 (amdgpu_crtc->lut_b[i] << 0)); 2325 } 2326 2327 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2328 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2329 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2330 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); 2331 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2332 2333 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2334 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2335 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2336 2337 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2338 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2339 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2340 2341 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2342 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2343 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2344 2345 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2346 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2347 /* XXX this only needs to be programmed once per crtc at startup, 2348 * not sure where the best place for it is 2349 */ 2350 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2351 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2352 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2353 } 2354 2355 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder) 2356 { 2357 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2358 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2359 2360 switch (amdgpu_encoder->encoder_id) { 2361 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2362 if (dig->linkb) 2363 return 1; 2364 else 2365 return 0; 2366 break; 2367 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2368 if (dig->linkb) 2369 return 3; 2370 else 2371 return 2; 2372 break; 2373 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2374 if (dig->linkb) 2375 return 5; 2376 else 2377 return 4; 2378 break; 2379 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2380 return 6; 2381 break; 2382 default: 2383 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2384 return 0; 2385 } 2386 } 2387 2388 /** 2389 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc. 2390 * 2391 * @crtc: drm crtc 2392 * 2393 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2394 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2395 * monitors a dedicated PPLL must be used. If a particular board has 2396 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2397 * as there is no need to program the PLL itself. If we are not able to 2398 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2399 * avoid messing up an existing monitor. 2400 * 2401 * Asic specific PLL information 2402 * 2403 * DCE 10.x 2404 * Tonga 2405 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2406 * CI 2407 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2408 * 2409 */ 2410 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) 2411 { 2412 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2413 struct drm_device *dev = crtc->dev; 2414 struct amdgpu_device *adev = dev->dev_private; 2415 u32 pll_in_use; 2416 int pll; 2417 2418 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2419 if (adev->clock.dp_extclk) 2420 /* skip PPLL programming if using ext clock */ 2421 return ATOM_PPLL_INVALID; 2422 else { 2423 /* use the same PPLL for all DP monitors */ 2424 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2425 if (pll != ATOM_PPLL_INVALID) 2426 return pll; 2427 } 2428 } else { 2429 /* use the same PPLL for all monitors with the same clock */ 2430 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2431 if (pll != ATOM_PPLL_INVALID) 2432 return pll; 2433 } 2434 2435 /* XXX need to determine what plls are available on each DCE11 part */ 2436 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2437 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) { 2438 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2439 return ATOM_PPLL1; 2440 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2441 return ATOM_PPLL0; 2442 DRM_ERROR("unable to allocate a PPLL\n"); 2443 return ATOM_PPLL_INVALID; 2444 } else { 2445 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2446 return ATOM_PPLL2; 2447 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2448 return ATOM_PPLL1; 2449 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2450 return ATOM_PPLL0; 2451 DRM_ERROR("unable to allocate a PPLL\n"); 2452 return ATOM_PPLL_INVALID; 2453 } 2454 return ATOM_PPLL_INVALID; 2455 } 2456 2457 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2458 { 2459 struct amdgpu_device *adev = crtc->dev->dev_private; 2460 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2461 uint32_t cur_lock; 2462 2463 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2464 if (lock) 2465 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2466 else 2467 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2468 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2469 } 2470 2471 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc) 2472 { 2473 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2474 struct amdgpu_device *adev = crtc->dev->dev_private; 2475 u32 tmp; 2476 2477 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2478 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2479 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2480 } 2481 2482 static void dce_v11_0_show_cursor(struct drm_crtc *crtc) 2483 { 2484 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2485 struct amdgpu_device *adev = crtc->dev->dev_private; 2486 u32 tmp; 2487 2488 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2489 upper_32_bits(amdgpu_crtc->cursor_addr)); 2490 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2491 lower_32_bits(amdgpu_crtc->cursor_addr)); 2492 2493 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2494 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2495 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2496 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2497 } 2498 2499 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, 2500 int x, int y) 2501 { 2502 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2503 struct amdgpu_device *adev = crtc->dev->dev_private; 2504 int xorigin = 0, yorigin = 0; 2505 2506 /* avivo cursor are offset into the total surface */ 2507 x += crtc->x; 2508 y += crtc->y; 2509 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2510 2511 if (x < 0) { 2512 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2513 x = 0; 2514 } 2515 if (y < 0) { 2516 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2517 y = 0; 2518 } 2519 2520 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2521 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2522 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2523 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2524 2525 amdgpu_crtc->cursor_x = x; 2526 amdgpu_crtc->cursor_y = y; 2527 2528 return 0; 2529 } 2530 2531 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, 2532 int x, int y) 2533 { 2534 int ret; 2535 2536 dce_v11_0_lock_cursor(crtc, true); 2537 ret = dce_v11_0_cursor_move_locked(crtc, x, y); 2538 dce_v11_0_lock_cursor(crtc, false); 2539 2540 return ret; 2541 } 2542 2543 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 2544 struct drm_file *file_priv, 2545 uint32_t handle, 2546 uint32_t width, 2547 uint32_t height, 2548 int32_t hot_x, 2549 int32_t hot_y) 2550 { 2551 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2552 struct drm_gem_object *obj; 2553 struct amdgpu_bo *aobj; 2554 int ret; 2555 2556 if (!handle) { 2557 /* turn off cursor */ 2558 dce_v11_0_hide_cursor(crtc); 2559 obj = NULL; 2560 goto unpin; 2561 } 2562 2563 if ((width > amdgpu_crtc->max_cursor_width) || 2564 (height > amdgpu_crtc->max_cursor_height)) { 2565 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2566 return -EINVAL; 2567 } 2568 2569 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 2570 if (!obj) { 2571 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2572 return -ENOENT; 2573 } 2574 2575 aobj = gem_to_amdgpu_bo(obj); 2576 ret = amdgpu_bo_reserve(aobj, false); 2577 if (ret != 0) { 2578 drm_gem_object_unreference_unlocked(obj); 2579 return ret; 2580 } 2581 2582 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2583 amdgpu_bo_unreserve(aobj); 2584 if (ret) { 2585 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2586 drm_gem_object_unreference_unlocked(obj); 2587 return ret; 2588 } 2589 2590 amdgpu_crtc->cursor_width = width; 2591 amdgpu_crtc->cursor_height = height; 2592 2593 dce_v11_0_lock_cursor(crtc, true); 2594 2595 if (hot_x != amdgpu_crtc->cursor_hot_x || 2596 hot_y != amdgpu_crtc->cursor_hot_y) { 2597 int x, y; 2598 2599 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2600 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2601 2602 dce_v11_0_cursor_move_locked(crtc, x, y); 2603 2604 amdgpu_crtc->cursor_hot_x = hot_x; 2605 amdgpu_crtc->cursor_hot_y = hot_y; 2606 } 2607 2608 dce_v11_0_show_cursor(crtc); 2609 dce_v11_0_lock_cursor(crtc, false); 2610 2611 unpin: 2612 if (amdgpu_crtc->cursor_bo) { 2613 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2614 ret = amdgpu_bo_reserve(aobj, false); 2615 if (likely(ret == 0)) { 2616 amdgpu_bo_unpin(aobj); 2617 amdgpu_bo_unreserve(aobj); 2618 } 2619 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 2620 } 2621 2622 amdgpu_crtc->cursor_bo = obj; 2623 return 0; 2624 } 2625 2626 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) 2627 { 2628 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2629 2630 if (amdgpu_crtc->cursor_bo) { 2631 dce_v11_0_lock_cursor(crtc, true); 2632 2633 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2634 amdgpu_crtc->cursor_y); 2635 2636 dce_v11_0_show_cursor(crtc); 2637 2638 dce_v11_0_lock_cursor(crtc, false); 2639 } 2640 } 2641 2642 static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2643 u16 *blue, uint32_t start, uint32_t size) 2644 { 2645 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2646 int end = (start + size > 256) ? 256 : start + size, i; 2647 2648 /* userspace palettes are always correct as is */ 2649 for (i = start; i < end; i++) { 2650 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2651 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2652 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2653 } 2654 dce_v11_0_crtc_load_lut(crtc); 2655 } 2656 2657 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) 2658 { 2659 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2660 2661 drm_crtc_cleanup(crtc); 2662 destroy_workqueue(amdgpu_crtc->pflip_queue); 2663 kfree(amdgpu_crtc); 2664 } 2665 2666 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { 2667 .cursor_set2 = dce_v11_0_crtc_cursor_set2, 2668 .cursor_move = dce_v11_0_crtc_cursor_move, 2669 .gamma_set = dce_v11_0_crtc_gamma_set, 2670 .set_config = amdgpu_crtc_set_config, 2671 .destroy = dce_v11_0_crtc_destroy, 2672 .page_flip = amdgpu_crtc_page_flip, 2673 }; 2674 2675 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2676 { 2677 struct drm_device *dev = crtc->dev; 2678 struct amdgpu_device *adev = dev->dev_private; 2679 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2680 unsigned type; 2681 2682 switch (mode) { 2683 case DRM_MODE_DPMS_ON: 2684 amdgpu_crtc->enabled = true; 2685 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2686 dce_v11_0_vga_enable(crtc, true); 2687 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2688 dce_v11_0_vga_enable(crtc, false); 2689 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2690 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2691 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2692 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2693 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); 2694 dce_v11_0_crtc_load_lut(crtc); 2695 break; 2696 case DRM_MODE_DPMS_STANDBY: 2697 case DRM_MODE_DPMS_SUSPEND: 2698 case DRM_MODE_DPMS_OFF: 2699 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id); 2700 if (amdgpu_crtc->enabled) { 2701 dce_v11_0_vga_enable(crtc, true); 2702 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2703 dce_v11_0_vga_enable(crtc, false); 2704 } 2705 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2706 amdgpu_crtc->enabled = false; 2707 break; 2708 } 2709 /* adjust pm to dpms */ 2710 amdgpu_pm_compute_clocks(adev); 2711 } 2712 2713 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc) 2714 { 2715 /* disable crtc pair power gating before programming */ 2716 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2717 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2718 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2719 } 2720 2721 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc) 2722 { 2723 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2724 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2725 } 2726 2727 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) 2728 { 2729 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2730 struct drm_device *dev = crtc->dev; 2731 struct amdgpu_device *adev = dev->dev_private; 2732 struct amdgpu_atom_ss ss; 2733 int i; 2734 2735 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2736 if (crtc->primary->fb) { 2737 int r; 2738 struct amdgpu_framebuffer *amdgpu_fb; 2739 struct amdgpu_bo *rbo; 2740 2741 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2742 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2743 r = amdgpu_bo_reserve(rbo, false); 2744 if (unlikely(r)) 2745 DRM_ERROR("failed to reserve rbo before unpin\n"); 2746 else { 2747 amdgpu_bo_unpin(rbo); 2748 amdgpu_bo_unreserve(rbo); 2749 } 2750 } 2751 /* disable the GRPH */ 2752 dce_v11_0_grph_enable(crtc, false); 2753 2754 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2755 2756 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2757 if (adev->mode_info.crtcs[i] && 2758 adev->mode_info.crtcs[i]->enabled && 2759 i != amdgpu_crtc->crtc_id && 2760 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2761 /* one other crtc is using this pll don't turn 2762 * off the pll 2763 */ 2764 goto done; 2765 } 2766 } 2767 2768 switch (amdgpu_crtc->pll_id) { 2769 case ATOM_PPLL0: 2770 case ATOM_PPLL1: 2771 case ATOM_PPLL2: 2772 /* disable the ppll */ 2773 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2774 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2775 break; 2776 default: 2777 break; 2778 } 2779 done: 2780 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2781 amdgpu_crtc->adjusted_clock = 0; 2782 amdgpu_crtc->encoder = NULL; 2783 amdgpu_crtc->connector = NULL; 2784 } 2785 2786 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, 2787 struct drm_display_mode *mode, 2788 struct drm_display_mode *adjusted_mode, 2789 int x, int y, struct drm_framebuffer *old_fb) 2790 { 2791 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2792 2793 if (!amdgpu_crtc->adjusted_clock) 2794 return -EINVAL; 2795 2796 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2797 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2798 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2799 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2800 amdgpu_atombios_crtc_scaler_setup(crtc); 2801 dce_v11_0_cursor_reset(crtc); 2802 /* update the hw version fpr dpm */ 2803 amdgpu_crtc->hw_mode = *adjusted_mode; 2804 2805 return 0; 2806 } 2807 2808 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc, 2809 const struct drm_display_mode *mode, 2810 struct drm_display_mode *adjusted_mode) 2811 { 2812 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2813 struct drm_device *dev = crtc->dev; 2814 struct drm_encoder *encoder; 2815 2816 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2817 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2818 if (encoder->crtc == crtc) { 2819 amdgpu_crtc->encoder = encoder; 2820 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2821 break; 2822 } 2823 } 2824 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2825 amdgpu_crtc->encoder = NULL; 2826 amdgpu_crtc->connector = NULL; 2827 return false; 2828 } 2829 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2830 return false; 2831 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2832 return false; 2833 /* pick pll */ 2834 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); 2835 /* if we can't get a PPLL for a non-DP encoder, fail */ 2836 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2837 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2838 return false; 2839 2840 return true; 2841 } 2842 2843 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2844 struct drm_framebuffer *old_fb) 2845 { 2846 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2847 } 2848 2849 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2850 struct drm_framebuffer *fb, 2851 int x, int y, enum mode_set_atomic state) 2852 { 2853 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1); 2854 } 2855 2856 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { 2857 .dpms = dce_v11_0_crtc_dpms, 2858 .mode_fixup = dce_v11_0_crtc_mode_fixup, 2859 .mode_set = dce_v11_0_crtc_mode_set, 2860 .mode_set_base = dce_v11_0_crtc_set_base, 2861 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic, 2862 .prepare = dce_v11_0_crtc_prepare, 2863 .commit = dce_v11_0_crtc_commit, 2864 .load_lut = dce_v11_0_crtc_load_lut, 2865 .disable = dce_v11_0_crtc_disable, 2866 }; 2867 2868 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) 2869 { 2870 struct amdgpu_crtc *amdgpu_crtc; 2871 int i; 2872 2873 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2874 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2875 if (amdgpu_crtc == NULL) 2876 return -ENOMEM; 2877 2878 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); 2879 2880 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2881 amdgpu_crtc->crtc_id = index; 2882 amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue"); 2883 adev->mode_info.crtcs[index] = amdgpu_crtc; 2884 2885 amdgpu_crtc->max_cursor_width = 128; 2886 amdgpu_crtc->max_cursor_height = 128; 2887 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2888 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2889 2890 for (i = 0; i < 256; i++) { 2891 amdgpu_crtc->lut_r[i] = i << 2; 2892 amdgpu_crtc->lut_g[i] = i << 2; 2893 amdgpu_crtc->lut_b[i] = i << 2; 2894 } 2895 2896 switch (amdgpu_crtc->crtc_id) { 2897 case 0: 2898 default: 2899 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2900 break; 2901 case 1: 2902 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2903 break; 2904 case 2: 2905 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2906 break; 2907 case 3: 2908 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2909 break; 2910 case 4: 2911 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2912 break; 2913 case 5: 2914 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2915 break; 2916 } 2917 2918 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2919 amdgpu_crtc->adjusted_clock = 0; 2920 amdgpu_crtc->encoder = NULL; 2921 amdgpu_crtc->connector = NULL; 2922 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); 2923 2924 return 0; 2925 } 2926 2927 static int dce_v11_0_early_init(void *handle) 2928 { 2929 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2930 2931 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; 2932 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; 2933 2934 dce_v11_0_set_display_funcs(adev); 2935 dce_v11_0_set_irq_funcs(adev); 2936 2937 switch (adev->asic_type) { 2938 case CHIP_CARRIZO: 2939 adev->mode_info.num_crtc = 3; 2940 adev->mode_info.num_hpd = 6; 2941 adev->mode_info.num_dig = 9; 2942 break; 2943 case CHIP_STONEY: 2944 adev->mode_info.num_crtc = 2; 2945 adev->mode_info.num_hpd = 6; 2946 adev->mode_info.num_dig = 9; 2947 break; 2948 default: 2949 /* FIXME: not supported yet */ 2950 return -EINVAL; 2951 } 2952 2953 return 0; 2954 } 2955 2956 static int dce_v11_0_sw_init(void *handle) 2957 { 2958 int r, i; 2959 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2960 2961 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2962 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); 2963 if (r) 2964 return r; 2965 } 2966 2967 for (i = 8; i < 20; i += 2) { 2968 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); 2969 if (r) 2970 return r; 2971 } 2972 2973 /* HPD hotplug */ 2974 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); 2975 if (r) 2976 return r; 2977 2978 adev->mode_info.mode_config_initialized = true; 2979 2980 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2981 2982 adev->ddev->mode_config.max_width = 16384; 2983 adev->ddev->mode_config.max_height = 16384; 2984 2985 adev->ddev->mode_config.preferred_depth = 24; 2986 adev->ddev->mode_config.prefer_shadow = 1; 2987 2988 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2989 2990 r = amdgpu_modeset_create_props(adev); 2991 if (r) 2992 return r; 2993 2994 adev->ddev->mode_config.max_width = 16384; 2995 adev->ddev->mode_config.max_height = 16384; 2996 2997 /* allocate crtcs */ 2998 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2999 r = dce_v11_0_crtc_init(adev, i); 3000 if (r) 3001 return r; 3002 } 3003 3004 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 3005 amdgpu_print_display_setup(adev->ddev); 3006 else 3007 return -EINVAL; 3008 3009 /* setup afmt */ 3010 dce_v11_0_afmt_init(adev); 3011 3012 r = dce_v11_0_audio_init(adev); 3013 if (r) 3014 return r; 3015 3016 drm_kms_helper_poll_init(adev->ddev); 3017 3018 return r; 3019 } 3020 3021 static int dce_v11_0_sw_fini(void *handle) 3022 { 3023 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3024 3025 kfree(adev->mode_info.bios_hardcoded_edid); 3026 3027 drm_kms_helper_poll_fini(adev->ddev); 3028 3029 dce_v11_0_audio_fini(adev); 3030 3031 dce_v11_0_afmt_fini(adev); 3032 3033 adev->mode_info.mode_config_initialized = false; 3034 3035 return 0; 3036 } 3037 3038 static int dce_v11_0_hw_init(void *handle) 3039 { 3040 int i; 3041 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3042 3043 dce_v11_0_init_golden_registers(adev); 3044 3045 /* init dig PHYs, disp eng pll */ 3046 amdgpu_atombios_crtc_powergate_init(adev); 3047 amdgpu_atombios_encoder_init_dig(adev); 3048 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 3049 3050 /* initialize hpd */ 3051 dce_v11_0_hpd_init(adev); 3052 3053 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3054 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3055 } 3056 3057 dce_v11_0_pageflip_interrupt_init(adev); 3058 3059 return 0; 3060 } 3061 3062 static int dce_v11_0_hw_fini(void *handle) 3063 { 3064 int i; 3065 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3066 3067 dce_v11_0_hpd_fini(adev); 3068 3069 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3070 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3071 } 3072 3073 dce_v11_0_pageflip_interrupt_fini(adev); 3074 3075 return 0; 3076 } 3077 3078 static int dce_v11_0_suspend(void *handle) 3079 { 3080 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3081 3082 amdgpu_atombios_scratch_regs_save(adev); 3083 3084 return dce_v11_0_hw_fini(handle); 3085 } 3086 3087 static int dce_v11_0_resume(void *handle) 3088 { 3089 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3090 int ret; 3091 3092 ret = dce_v11_0_hw_init(handle); 3093 3094 amdgpu_atombios_scratch_regs_restore(adev); 3095 3096 /* turn on the BL */ 3097 if (adev->mode_info.bl_encoder) { 3098 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3099 adev->mode_info.bl_encoder); 3100 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3101 bl_level); 3102 } 3103 3104 return ret; 3105 } 3106 3107 static bool dce_v11_0_is_idle(void *handle) 3108 { 3109 return true; 3110 } 3111 3112 static int dce_v11_0_wait_for_idle(void *handle) 3113 { 3114 return 0; 3115 } 3116 3117 static void dce_v11_0_print_status(void *handle) 3118 { 3119 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3120 3121 dev_info(adev->dev, "DCE 10.x registers\n"); 3122 /* XXX todo */ 3123 } 3124 3125 static int dce_v11_0_soft_reset(void *handle) 3126 { 3127 u32 srbm_soft_reset = 0, tmp; 3128 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3129 3130 if (dce_v11_0_is_display_hung(adev)) 3131 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3132 3133 if (srbm_soft_reset) { 3134 dce_v11_0_print_status((void *)adev); 3135 3136 tmp = RREG32(mmSRBM_SOFT_RESET); 3137 tmp |= srbm_soft_reset; 3138 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3139 WREG32(mmSRBM_SOFT_RESET, tmp); 3140 tmp = RREG32(mmSRBM_SOFT_RESET); 3141 3142 udelay(50); 3143 3144 tmp &= ~srbm_soft_reset; 3145 WREG32(mmSRBM_SOFT_RESET, tmp); 3146 tmp = RREG32(mmSRBM_SOFT_RESET); 3147 3148 /* Wait a little for things to settle down */ 3149 udelay(50); 3150 dce_v11_0_print_status((void *)adev); 3151 } 3152 return 0; 3153 } 3154 3155 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3156 int crtc, 3157 enum amdgpu_interrupt_state state) 3158 { 3159 u32 lb_interrupt_mask; 3160 3161 if (crtc >= adev->mode_info.num_crtc) { 3162 DRM_DEBUG("invalid crtc %d\n", crtc); 3163 return; 3164 } 3165 3166 switch (state) { 3167 case AMDGPU_IRQ_STATE_DISABLE: 3168 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3169 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3170 VBLANK_INTERRUPT_MASK, 0); 3171 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3172 break; 3173 case AMDGPU_IRQ_STATE_ENABLE: 3174 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3175 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3176 VBLANK_INTERRUPT_MASK, 1); 3177 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3178 break; 3179 default: 3180 break; 3181 } 3182 } 3183 3184 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3185 int crtc, 3186 enum amdgpu_interrupt_state state) 3187 { 3188 u32 lb_interrupt_mask; 3189 3190 if (crtc >= adev->mode_info.num_crtc) { 3191 DRM_DEBUG("invalid crtc %d\n", crtc); 3192 return; 3193 } 3194 3195 switch (state) { 3196 case AMDGPU_IRQ_STATE_DISABLE: 3197 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3198 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3199 VLINE_INTERRUPT_MASK, 0); 3200 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3201 break; 3202 case AMDGPU_IRQ_STATE_ENABLE: 3203 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3204 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3205 VLINE_INTERRUPT_MASK, 1); 3206 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3207 break; 3208 default: 3209 break; 3210 } 3211 } 3212 3213 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev, 3214 struct amdgpu_irq_src *source, 3215 unsigned hpd, 3216 enum amdgpu_interrupt_state state) 3217 { 3218 u32 tmp; 3219 3220 if (hpd >= adev->mode_info.num_hpd) { 3221 DRM_DEBUG("invalid hdp %d\n", hpd); 3222 return 0; 3223 } 3224 3225 switch (state) { 3226 case AMDGPU_IRQ_STATE_DISABLE: 3227 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3228 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3229 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3230 break; 3231 case AMDGPU_IRQ_STATE_ENABLE: 3232 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3233 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3234 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3235 break; 3236 default: 3237 break; 3238 } 3239 3240 return 0; 3241 } 3242 3243 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev, 3244 struct amdgpu_irq_src *source, 3245 unsigned type, 3246 enum amdgpu_interrupt_state state) 3247 { 3248 switch (type) { 3249 case AMDGPU_CRTC_IRQ_VBLANK1: 3250 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3251 break; 3252 case AMDGPU_CRTC_IRQ_VBLANK2: 3253 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3254 break; 3255 case AMDGPU_CRTC_IRQ_VBLANK3: 3256 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3257 break; 3258 case AMDGPU_CRTC_IRQ_VBLANK4: 3259 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3260 break; 3261 case AMDGPU_CRTC_IRQ_VBLANK5: 3262 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3263 break; 3264 case AMDGPU_CRTC_IRQ_VBLANK6: 3265 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3266 break; 3267 case AMDGPU_CRTC_IRQ_VLINE1: 3268 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state); 3269 break; 3270 case AMDGPU_CRTC_IRQ_VLINE2: 3271 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state); 3272 break; 3273 case AMDGPU_CRTC_IRQ_VLINE3: 3274 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state); 3275 break; 3276 case AMDGPU_CRTC_IRQ_VLINE4: 3277 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state); 3278 break; 3279 case AMDGPU_CRTC_IRQ_VLINE5: 3280 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state); 3281 break; 3282 case AMDGPU_CRTC_IRQ_VLINE6: 3283 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state); 3284 break; 3285 default: 3286 break; 3287 } 3288 return 0; 3289 } 3290 3291 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3292 struct amdgpu_irq_src *src, 3293 unsigned type, 3294 enum amdgpu_interrupt_state state) 3295 { 3296 u32 reg; 3297 3298 if (type >= adev->mode_info.num_crtc) { 3299 DRM_ERROR("invalid pageflip crtc %d\n", type); 3300 return -EINVAL; 3301 } 3302 3303 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3304 if (state == AMDGPU_IRQ_STATE_DISABLE) 3305 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3306 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3307 else 3308 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3309 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3310 3311 return 0; 3312 } 3313 3314 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, 3315 struct amdgpu_irq_src *source, 3316 struct amdgpu_iv_entry *entry) 3317 { 3318 unsigned long flags; 3319 unsigned crtc_id; 3320 struct amdgpu_crtc *amdgpu_crtc; 3321 struct amdgpu_flip_work *works; 3322 3323 crtc_id = (entry->src_id - 8) >> 1; 3324 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3325 3326 if (crtc_id >= adev->mode_info.num_crtc) { 3327 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3328 return -EINVAL; 3329 } 3330 3331 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3332 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3333 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3334 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3335 3336 /* IRQ could occur when in initial stage */ 3337 if(amdgpu_crtc == NULL) 3338 return 0; 3339 3340 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3341 works = amdgpu_crtc->pflip_works; 3342 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3343 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3344 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3345 amdgpu_crtc->pflip_status, 3346 AMDGPU_FLIP_SUBMITTED); 3347 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3348 return 0; 3349 } 3350 3351 /* page flip completed. clean up */ 3352 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3353 amdgpu_crtc->pflip_works = NULL; 3354 3355 /* wakeup usersapce */ 3356 if(works->event) 3357 drm_send_vblank_event(adev->ddev, crtc_id, works->event); 3358 3359 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3360 3361 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); 3362 queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work); 3363 3364 return 0; 3365 } 3366 3367 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, 3368 int hpd) 3369 { 3370 u32 tmp; 3371 3372 if (hpd >= adev->mode_info.num_hpd) { 3373 DRM_DEBUG("invalid hdp %d\n", hpd); 3374 return; 3375 } 3376 3377 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3378 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3379 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3380 } 3381 3382 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3383 int crtc) 3384 { 3385 u32 tmp; 3386 3387 if (crtc >= adev->mode_info.num_crtc) { 3388 DRM_DEBUG("invalid crtc %d\n", crtc); 3389 return; 3390 } 3391 3392 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3393 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3394 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3395 } 3396 3397 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3398 int crtc) 3399 { 3400 u32 tmp; 3401 3402 if (crtc >= adev->mode_info.num_crtc) { 3403 DRM_DEBUG("invalid crtc %d\n", crtc); 3404 return; 3405 } 3406 3407 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3408 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3409 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3410 } 3411 3412 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, 3413 struct amdgpu_irq_src *source, 3414 struct amdgpu_iv_entry *entry) 3415 { 3416 unsigned crtc = entry->src_id - 1; 3417 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3418 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3419 3420 switch (entry->src_data) { 3421 case 0: /* vblank */ 3422 if (disp_int & interrupt_status_offsets[crtc].vblank) 3423 dce_v11_0_crtc_vblank_int_ack(adev, crtc); 3424 else 3425 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3426 3427 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3428 drm_handle_vblank(adev->ddev, crtc); 3429 } 3430 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3431 3432 break; 3433 case 1: /* vline */ 3434 if (disp_int & interrupt_status_offsets[crtc].vline) 3435 dce_v11_0_crtc_vline_int_ack(adev, crtc); 3436 else 3437 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3438 3439 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3440 3441 break; 3442 default: 3443 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3444 break; 3445 } 3446 3447 return 0; 3448 } 3449 3450 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, 3451 struct amdgpu_irq_src *source, 3452 struct amdgpu_iv_entry *entry) 3453 { 3454 uint32_t disp_int, mask; 3455 unsigned hpd; 3456 3457 if (entry->src_data >= adev->mode_info.num_hpd) { 3458 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3459 return 0; 3460 } 3461 3462 hpd = entry->src_data; 3463 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3464 mask = interrupt_status_offsets[hpd].hpd; 3465 3466 if (disp_int & mask) { 3467 dce_v11_0_hpd_int_ack(adev, hpd); 3468 schedule_work(&adev->hotplug_work); 3469 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3470 } 3471 3472 return 0; 3473 } 3474 3475 static int dce_v11_0_set_clockgating_state(void *handle, 3476 enum amd_clockgating_state state) 3477 { 3478 return 0; 3479 } 3480 3481 static int dce_v11_0_set_powergating_state(void *handle, 3482 enum amd_powergating_state state) 3483 { 3484 return 0; 3485 } 3486 3487 const struct amd_ip_funcs dce_v11_0_ip_funcs = { 3488 .early_init = dce_v11_0_early_init, 3489 .late_init = NULL, 3490 .sw_init = dce_v11_0_sw_init, 3491 .sw_fini = dce_v11_0_sw_fini, 3492 .hw_init = dce_v11_0_hw_init, 3493 .hw_fini = dce_v11_0_hw_fini, 3494 .suspend = dce_v11_0_suspend, 3495 .resume = dce_v11_0_resume, 3496 .is_idle = dce_v11_0_is_idle, 3497 .wait_for_idle = dce_v11_0_wait_for_idle, 3498 .soft_reset = dce_v11_0_soft_reset, 3499 .print_status = dce_v11_0_print_status, 3500 .set_clockgating_state = dce_v11_0_set_clockgating_state, 3501 .set_powergating_state = dce_v11_0_set_powergating_state, 3502 }; 3503 3504 static void 3505 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder, 3506 struct drm_display_mode *mode, 3507 struct drm_display_mode *adjusted_mode) 3508 { 3509 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3510 3511 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3512 3513 /* need to call this here rather than in prepare() since we need some crtc info */ 3514 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3515 3516 /* set scaler clears this on some chips */ 3517 dce_v11_0_set_interleave(encoder->crtc, mode); 3518 3519 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3520 dce_v11_0_afmt_enable(encoder, true); 3521 dce_v11_0_afmt_setmode(encoder, adjusted_mode); 3522 } 3523 } 3524 3525 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder) 3526 { 3527 struct amdgpu_device *adev = encoder->dev->dev_private; 3528 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3529 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3530 3531 if ((amdgpu_encoder->active_device & 3532 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3533 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3534 ENCODER_OBJECT_ID_NONE)) { 3535 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3536 if (dig) { 3537 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); 3538 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3539 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3540 } 3541 } 3542 3543 amdgpu_atombios_scratch_regs_lock(adev, true); 3544 3545 if (connector) { 3546 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3547 3548 /* select the clock/data port if it uses a router */ 3549 if (amdgpu_connector->router.cd_valid) 3550 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3551 3552 /* turn eDP panel on for mode set */ 3553 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3554 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3555 ATOM_TRANSMITTER_ACTION_POWER_ON); 3556 } 3557 3558 /* this is needed for the pll/ss setup to work correctly in some cases */ 3559 amdgpu_atombios_encoder_set_crtc_source(encoder); 3560 /* set up the FMT blocks */ 3561 dce_v11_0_program_fmt(encoder); 3562 } 3563 3564 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder) 3565 { 3566 struct drm_device *dev = encoder->dev; 3567 struct amdgpu_device *adev = dev->dev_private; 3568 3569 /* need to call this here as we need the crtc set up */ 3570 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3571 amdgpu_atombios_scratch_regs_lock(adev, false); 3572 } 3573 3574 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder) 3575 { 3576 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3577 struct amdgpu_encoder_atom_dig *dig; 3578 3579 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3580 3581 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3582 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3583 dce_v11_0_afmt_enable(encoder, false); 3584 dig = amdgpu_encoder->enc_priv; 3585 dig->dig_encoder = -1; 3586 } 3587 amdgpu_encoder->active_device = 0; 3588 } 3589 3590 /* these are handled by the primary encoders */ 3591 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder) 3592 { 3593 3594 } 3595 3596 static void dce_v11_0_ext_commit(struct drm_encoder *encoder) 3597 { 3598 3599 } 3600 3601 static void 3602 dce_v11_0_ext_mode_set(struct drm_encoder *encoder, 3603 struct drm_display_mode *mode, 3604 struct drm_display_mode *adjusted_mode) 3605 { 3606 3607 } 3608 3609 static void dce_v11_0_ext_disable(struct drm_encoder *encoder) 3610 { 3611 3612 } 3613 3614 static void 3615 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode) 3616 { 3617 3618 } 3619 3620 static bool dce_v11_0_ext_mode_fixup(struct drm_encoder *encoder, 3621 const struct drm_display_mode *mode, 3622 struct drm_display_mode *adjusted_mode) 3623 { 3624 return true; 3625 } 3626 3627 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = { 3628 .dpms = dce_v11_0_ext_dpms, 3629 .mode_fixup = dce_v11_0_ext_mode_fixup, 3630 .prepare = dce_v11_0_ext_prepare, 3631 .mode_set = dce_v11_0_ext_mode_set, 3632 .commit = dce_v11_0_ext_commit, 3633 .disable = dce_v11_0_ext_disable, 3634 /* no detect for TMDS/LVDS yet */ 3635 }; 3636 3637 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = { 3638 .dpms = amdgpu_atombios_encoder_dpms, 3639 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3640 .prepare = dce_v11_0_encoder_prepare, 3641 .mode_set = dce_v11_0_encoder_mode_set, 3642 .commit = dce_v11_0_encoder_commit, 3643 .disable = dce_v11_0_encoder_disable, 3644 .detect = amdgpu_atombios_encoder_dig_detect, 3645 }; 3646 3647 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = { 3648 .dpms = amdgpu_atombios_encoder_dpms, 3649 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3650 .prepare = dce_v11_0_encoder_prepare, 3651 .mode_set = dce_v11_0_encoder_mode_set, 3652 .commit = dce_v11_0_encoder_commit, 3653 .detect = amdgpu_atombios_encoder_dac_detect, 3654 }; 3655 3656 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder) 3657 { 3658 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3659 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3660 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3661 kfree(amdgpu_encoder->enc_priv); 3662 drm_encoder_cleanup(encoder); 3663 kfree(amdgpu_encoder); 3664 } 3665 3666 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = { 3667 .destroy = dce_v11_0_encoder_destroy, 3668 }; 3669 3670 static void dce_v11_0_encoder_add(struct amdgpu_device *adev, 3671 uint32_t encoder_enum, 3672 uint32_t supported_device, 3673 u16 caps) 3674 { 3675 struct drm_device *dev = adev->ddev; 3676 struct drm_encoder *encoder; 3677 struct amdgpu_encoder *amdgpu_encoder; 3678 3679 /* see if we already added it */ 3680 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3681 amdgpu_encoder = to_amdgpu_encoder(encoder); 3682 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3683 amdgpu_encoder->devices |= supported_device; 3684 return; 3685 } 3686 3687 } 3688 3689 /* add a new one */ 3690 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3691 if (!amdgpu_encoder) 3692 return; 3693 3694 encoder = &amdgpu_encoder->base; 3695 switch (adev->mode_info.num_crtc) { 3696 case 1: 3697 encoder->possible_crtcs = 0x1; 3698 break; 3699 case 2: 3700 default: 3701 encoder->possible_crtcs = 0x3; 3702 break; 3703 case 4: 3704 encoder->possible_crtcs = 0xf; 3705 break; 3706 case 6: 3707 encoder->possible_crtcs = 0x3f; 3708 break; 3709 } 3710 3711 amdgpu_encoder->enc_priv = NULL; 3712 3713 amdgpu_encoder->encoder_enum = encoder_enum; 3714 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3715 amdgpu_encoder->devices = supported_device; 3716 amdgpu_encoder->rmx_type = RMX_OFF; 3717 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3718 amdgpu_encoder->is_ext_encoder = false; 3719 amdgpu_encoder->caps = caps; 3720 3721 switch (amdgpu_encoder->encoder_id) { 3722 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3723 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3724 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3725 DRM_MODE_ENCODER_DAC); 3726 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); 3727 break; 3728 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3729 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3730 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3731 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3732 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3733 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3734 amdgpu_encoder->rmx_type = RMX_FULL; 3735 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3736 DRM_MODE_ENCODER_LVDS); 3737 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3738 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3739 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3740 DRM_MODE_ENCODER_DAC); 3741 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3742 } else { 3743 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3744 DRM_MODE_ENCODER_TMDS); 3745 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3746 } 3747 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); 3748 break; 3749 case ENCODER_OBJECT_ID_SI170B: 3750 case ENCODER_OBJECT_ID_CH7303: 3751 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3752 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3753 case ENCODER_OBJECT_ID_TITFP513: 3754 case ENCODER_OBJECT_ID_VT1623: 3755 case ENCODER_OBJECT_ID_HDMI_SI1930: 3756 case ENCODER_OBJECT_ID_TRAVIS: 3757 case ENCODER_OBJECT_ID_NUTMEG: 3758 /* these are handled by the primary encoders */ 3759 amdgpu_encoder->is_ext_encoder = true; 3760 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3761 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3762 DRM_MODE_ENCODER_LVDS); 3763 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3764 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3765 DRM_MODE_ENCODER_DAC); 3766 else 3767 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3768 DRM_MODE_ENCODER_TMDS); 3769 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs); 3770 break; 3771 } 3772 } 3773 3774 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { 3775 .set_vga_render_state = &dce_v11_0_set_vga_render_state, 3776 .bandwidth_update = &dce_v11_0_bandwidth_update, 3777 .vblank_get_counter = &dce_v11_0_vblank_get_counter, 3778 .vblank_wait = &dce_v11_0_vblank_wait, 3779 .is_display_hung = &dce_v11_0_is_display_hung, 3780 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3781 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3782 .hpd_sense = &dce_v11_0_hpd_sense, 3783 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity, 3784 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg, 3785 .page_flip = &dce_v11_0_page_flip, 3786 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos, 3787 .add_encoder = &dce_v11_0_encoder_add, 3788 .add_connector = &amdgpu_connector_add, 3789 .stop_mc_access = &dce_v11_0_stop_mc_access, 3790 .resume_mc_access = &dce_v11_0_resume_mc_access, 3791 }; 3792 3793 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev) 3794 { 3795 if (adev->mode_info.funcs == NULL) 3796 adev->mode_info.funcs = &dce_v11_0_display_funcs; 3797 } 3798 3799 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = { 3800 .set = dce_v11_0_set_crtc_irq_state, 3801 .process = dce_v11_0_crtc_irq, 3802 }; 3803 3804 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = { 3805 .set = dce_v11_0_set_pageflip_irq_state, 3806 .process = dce_v11_0_pageflip_irq, 3807 }; 3808 3809 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { 3810 .set = dce_v11_0_set_hpd_irq_state, 3811 .process = dce_v11_0_hpd_irq, 3812 }; 3813 3814 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) 3815 { 3816 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3817 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; 3818 3819 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3820 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; 3821 3822 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3823 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; 3824 } 3825