1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/drm_debugfs.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu_sched.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 47 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 48 { 49 struct amdgpu_gpu_instance *gpu_instance; 50 int i; 51 52 mutex_lock(&mgpu_info.mutex); 53 54 for (i = 0; i < mgpu_info.num_gpu; i++) { 55 gpu_instance = &(mgpu_info.gpu_ins[i]); 56 if (gpu_instance->adev == adev) { 57 mgpu_info.gpu_ins[i] = 58 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 59 mgpu_info.num_gpu--; 60 if (adev->flags & AMD_IS_APU) 61 mgpu_info.num_apu--; 62 else 63 mgpu_info.num_dgpu--; 64 break; 65 } 66 } 67 68 mutex_unlock(&mgpu_info.mutex); 69 } 70 71 /** 72 * amdgpu_driver_unload_kms - Main unload function for KMS. 73 * 74 * @dev: drm dev pointer 75 * 76 * This is the main unload function for KMS (all asics). 77 * Returns 0 on success. 78 */ 79 void amdgpu_driver_unload_kms(struct drm_device *dev) 80 { 81 struct amdgpu_device *adev = dev->dev_private; 82 83 if (adev == NULL) 84 return; 85 86 amdgpu_unregister_gpu_instance(adev); 87 88 if (adev->rmmio == NULL) 89 goto done_free; 90 91 if (adev->runpm) { 92 pm_runtime_get_sync(dev->dev); 93 pm_runtime_forbid(dev->dev); 94 } 95 96 amdgpu_acpi_fini(adev); 97 98 amdgpu_device_fini(adev); 99 100 done_free: 101 kfree(adev); 102 dev->dev_private = NULL; 103 } 104 105 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 106 { 107 struct amdgpu_gpu_instance *gpu_instance; 108 109 mutex_lock(&mgpu_info.mutex); 110 111 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 112 DRM_ERROR("Cannot register more gpu instance\n"); 113 mutex_unlock(&mgpu_info.mutex); 114 return; 115 } 116 117 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 118 gpu_instance->adev = adev; 119 gpu_instance->mgpu_fan_enabled = 0; 120 121 mgpu_info.num_gpu++; 122 if (adev->flags & AMD_IS_APU) 123 mgpu_info.num_apu++; 124 else 125 mgpu_info.num_dgpu++; 126 127 mutex_unlock(&mgpu_info.mutex); 128 } 129 130 /** 131 * amdgpu_driver_load_kms - Main load function for KMS. 132 * 133 * @dev: drm dev pointer 134 * @flags: device flags 135 * 136 * This is the main load function for KMS (all asics). 137 * Returns 0 on success, error on failure. 138 */ 139 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 140 { 141 struct amdgpu_device *adev; 142 int r, acpi_status; 143 144 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 145 if (adev == NULL) { 146 return -ENOMEM; 147 } 148 dev->dev_private = (void *)adev; 149 150 if (amdgpu_has_atpx() && 151 (amdgpu_is_atpx_hybrid() || 152 amdgpu_has_atpx_dgpu_power_cntl()) && 153 ((flags & AMD_IS_APU) == 0) && 154 !pci_is_thunderbolt_attached(dev->pdev)) 155 flags |= AMD_IS_PX; 156 157 /* amdgpu_device_init should report only fatal error 158 * like memory allocation failure or iomapping failure, 159 * or memory manager initialization failure, it must 160 * properly initialize the GPU MC controller and permit 161 * VRAM allocation 162 */ 163 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 164 if (r) { 165 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 166 goto out; 167 } 168 169 if (amdgpu_device_supports_boco(dev) && 170 (amdgpu_runtime_pm != 0)) /* enable runpm by default for boco */ 171 adev->runpm = true; 172 else if (amdgpu_device_supports_baco(dev) && 173 (amdgpu_runtime_pm != 0) && 174 (adev->asic_type >= CHIP_TOPAZ) && 175 (adev->asic_type != CHIP_VEGA10) && 176 (adev->asic_type != CHIP_VEGA20) && 177 (adev->asic_type != CHIP_ARCTURUS)) /* enable runpm on VI+ */ 178 adev->runpm = true; 179 else if (amdgpu_device_supports_baco(dev) && 180 (amdgpu_runtime_pm > 0)) /* enable runpm if runpm=1 on CI */ 181 adev->runpm = true; 182 183 /* Call ACPI methods: require modeset init 184 * but failure is not fatal 185 */ 186 187 acpi_status = amdgpu_acpi_init(adev); 188 if (acpi_status) 189 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n"); 190 191 if (adev->runpm) { 192 /* only need to skip on ATPX */ 193 if (amdgpu_device_supports_boco(dev) && 194 !amdgpu_is_atpx_hybrid()) 195 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 196 pm_runtime_use_autosuspend(dev->dev); 197 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 198 pm_runtime_allow(dev->dev); 199 pm_runtime_mark_last_busy(dev->dev); 200 pm_runtime_put_autosuspend(dev->dev); 201 } 202 203 out: 204 if (r) { 205 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 206 if (adev->rmmio && adev->runpm) 207 pm_runtime_put_noidle(dev->dev); 208 amdgpu_driver_unload_kms(dev); 209 } 210 211 return r; 212 } 213 214 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 215 struct drm_amdgpu_query_fw *query_fw, 216 struct amdgpu_device *adev) 217 { 218 switch (query_fw->fw_type) { 219 case AMDGPU_INFO_FW_VCE: 220 fw_info->ver = adev->vce.fw_version; 221 fw_info->feature = adev->vce.fb_version; 222 break; 223 case AMDGPU_INFO_FW_UVD: 224 fw_info->ver = adev->uvd.fw_version; 225 fw_info->feature = 0; 226 break; 227 case AMDGPU_INFO_FW_VCN: 228 fw_info->ver = adev->vcn.fw_version; 229 fw_info->feature = 0; 230 break; 231 case AMDGPU_INFO_FW_GMC: 232 fw_info->ver = adev->gmc.fw_version; 233 fw_info->feature = 0; 234 break; 235 case AMDGPU_INFO_FW_GFX_ME: 236 fw_info->ver = adev->gfx.me_fw_version; 237 fw_info->feature = adev->gfx.me_feature_version; 238 break; 239 case AMDGPU_INFO_FW_GFX_PFP: 240 fw_info->ver = adev->gfx.pfp_fw_version; 241 fw_info->feature = adev->gfx.pfp_feature_version; 242 break; 243 case AMDGPU_INFO_FW_GFX_CE: 244 fw_info->ver = adev->gfx.ce_fw_version; 245 fw_info->feature = adev->gfx.ce_feature_version; 246 break; 247 case AMDGPU_INFO_FW_GFX_RLC: 248 fw_info->ver = adev->gfx.rlc_fw_version; 249 fw_info->feature = adev->gfx.rlc_feature_version; 250 break; 251 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 252 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 253 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 254 break; 255 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 256 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 257 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 258 break; 259 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 260 fw_info->ver = adev->gfx.rlc_srls_fw_version; 261 fw_info->feature = adev->gfx.rlc_srls_feature_version; 262 break; 263 case AMDGPU_INFO_FW_GFX_MEC: 264 if (query_fw->index == 0) { 265 fw_info->ver = adev->gfx.mec_fw_version; 266 fw_info->feature = adev->gfx.mec_feature_version; 267 } else if (query_fw->index == 1) { 268 fw_info->ver = adev->gfx.mec2_fw_version; 269 fw_info->feature = adev->gfx.mec2_feature_version; 270 } else 271 return -EINVAL; 272 break; 273 case AMDGPU_INFO_FW_SMC: 274 fw_info->ver = adev->pm.fw_version; 275 fw_info->feature = 0; 276 break; 277 case AMDGPU_INFO_FW_TA: 278 if (query_fw->index > 1) 279 return -EINVAL; 280 if (query_fw->index == 0) { 281 fw_info->ver = adev->psp.ta_fw_version; 282 fw_info->feature = adev->psp.ta_xgmi_ucode_version; 283 } else { 284 fw_info->ver = adev->psp.ta_fw_version; 285 fw_info->feature = adev->psp.ta_ras_ucode_version; 286 } 287 break; 288 case AMDGPU_INFO_FW_SDMA: 289 if (query_fw->index >= adev->sdma.num_instances) 290 return -EINVAL; 291 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 292 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 293 break; 294 case AMDGPU_INFO_FW_SOS: 295 fw_info->ver = adev->psp.sos_fw_version; 296 fw_info->feature = adev->psp.sos_feature_version; 297 break; 298 case AMDGPU_INFO_FW_ASD: 299 fw_info->ver = adev->psp.asd_fw_version; 300 fw_info->feature = adev->psp.asd_feature_version; 301 break; 302 case AMDGPU_INFO_FW_DMCU: 303 fw_info->ver = adev->dm.dmcu_fw_version; 304 fw_info->feature = 0; 305 break; 306 case AMDGPU_INFO_FW_DMCUB: 307 fw_info->ver = adev->dm.dmcub_fw_version; 308 fw_info->feature = 0; 309 break; 310 default: 311 return -EINVAL; 312 } 313 return 0; 314 } 315 316 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 317 struct drm_amdgpu_info *info, 318 struct drm_amdgpu_info_hw_ip *result) 319 { 320 uint32_t ib_start_alignment = 0; 321 uint32_t ib_size_alignment = 0; 322 enum amd_ip_block_type type; 323 unsigned int num_rings = 0; 324 unsigned int i, j; 325 326 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 327 return -EINVAL; 328 329 switch (info->query_hw_ip.type) { 330 case AMDGPU_HW_IP_GFX: 331 type = AMD_IP_BLOCK_TYPE_GFX; 332 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 333 if (adev->gfx.gfx_ring[i].sched.ready) 334 ++num_rings; 335 ib_start_alignment = 32; 336 ib_size_alignment = 32; 337 break; 338 case AMDGPU_HW_IP_COMPUTE: 339 type = AMD_IP_BLOCK_TYPE_GFX; 340 for (i = 0; i < adev->gfx.num_compute_rings; i++) 341 if (adev->gfx.compute_ring[i].sched.ready) 342 ++num_rings; 343 ib_start_alignment = 32; 344 ib_size_alignment = 32; 345 break; 346 case AMDGPU_HW_IP_DMA: 347 type = AMD_IP_BLOCK_TYPE_SDMA; 348 for (i = 0; i < adev->sdma.num_instances; i++) 349 if (adev->sdma.instance[i].ring.sched.ready) 350 ++num_rings; 351 ib_start_alignment = 256; 352 ib_size_alignment = 4; 353 break; 354 case AMDGPU_HW_IP_UVD: 355 type = AMD_IP_BLOCK_TYPE_UVD; 356 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 357 if (adev->uvd.harvest_config & (1 << i)) 358 continue; 359 360 if (adev->uvd.inst[i].ring.sched.ready) 361 ++num_rings; 362 } 363 ib_start_alignment = 64; 364 ib_size_alignment = 64; 365 break; 366 case AMDGPU_HW_IP_VCE: 367 type = AMD_IP_BLOCK_TYPE_VCE; 368 for (i = 0; i < adev->vce.num_rings; i++) 369 if (adev->vce.ring[i].sched.ready) 370 ++num_rings; 371 ib_start_alignment = 4; 372 ib_size_alignment = 1; 373 break; 374 case AMDGPU_HW_IP_UVD_ENC: 375 type = AMD_IP_BLOCK_TYPE_UVD; 376 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 377 if (adev->uvd.harvest_config & (1 << i)) 378 continue; 379 380 for (j = 0; j < adev->uvd.num_enc_rings; j++) 381 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 382 ++num_rings; 383 } 384 ib_start_alignment = 64; 385 ib_size_alignment = 64; 386 break; 387 case AMDGPU_HW_IP_VCN_DEC: 388 type = AMD_IP_BLOCK_TYPE_VCN; 389 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 390 if (adev->uvd.harvest_config & (1 << i)) 391 continue; 392 393 if (adev->vcn.inst[i].ring_dec.sched.ready) 394 ++num_rings; 395 } 396 ib_start_alignment = 16; 397 ib_size_alignment = 16; 398 break; 399 case AMDGPU_HW_IP_VCN_ENC: 400 type = AMD_IP_BLOCK_TYPE_VCN; 401 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 402 if (adev->uvd.harvest_config & (1 << i)) 403 continue; 404 405 for (j = 0; j < adev->vcn.num_enc_rings; j++) 406 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 407 ++num_rings; 408 } 409 ib_start_alignment = 64; 410 ib_size_alignment = 1; 411 break; 412 case AMDGPU_HW_IP_VCN_JPEG: 413 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 414 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 415 416 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 417 if (adev->jpeg.harvest_config & (1 << i)) 418 continue; 419 420 if (adev->jpeg.inst[i].ring_dec.sched.ready) 421 ++num_rings; 422 } 423 ib_start_alignment = 16; 424 ib_size_alignment = 16; 425 break; 426 default: 427 return -EINVAL; 428 } 429 430 for (i = 0; i < adev->num_ip_blocks; i++) 431 if (adev->ip_blocks[i].version->type == type && 432 adev->ip_blocks[i].status.valid) 433 break; 434 435 if (i == adev->num_ip_blocks) 436 return 0; 437 438 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 439 num_rings); 440 441 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 442 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 443 result->capabilities_flags = 0; 444 result->available_rings = (1 << num_rings) - 1; 445 result->ib_start_alignment = ib_start_alignment; 446 result->ib_size_alignment = ib_size_alignment; 447 return 0; 448 } 449 450 /* 451 * Userspace get information ioctl 452 */ 453 /** 454 * amdgpu_info_ioctl - answer a device specific request. 455 * 456 * @adev: amdgpu device pointer 457 * @data: request object 458 * @filp: drm filp 459 * 460 * This function is used to pass device specific parameters to the userspace 461 * drivers. Examples include: pci device id, pipeline parms, tiling params, 462 * etc. (all asics). 463 * Returns 0 on success, -EINVAL on failure. 464 */ 465 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 466 { 467 struct amdgpu_device *adev = dev->dev_private; 468 struct drm_amdgpu_info *info = data; 469 struct amdgpu_mode_info *minfo = &adev->mode_info; 470 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 471 uint32_t size = info->return_size; 472 struct drm_crtc *crtc; 473 uint32_t ui32 = 0; 474 uint64_t ui64 = 0; 475 int i, found; 476 int ui32_size = sizeof(ui32); 477 478 if (!info->return_size || !info->return_pointer) 479 return -EINVAL; 480 481 switch (info->query) { 482 case AMDGPU_INFO_ACCEL_WORKING: 483 ui32 = adev->accel_working; 484 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 485 case AMDGPU_INFO_CRTC_FROM_ID: 486 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 487 crtc = (struct drm_crtc *)minfo->crtcs[i]; 488 if (crtc && crtc->base.id == info->mode_crtc.id) { 489 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 490 ui32 = amdgpu_crtc->crtc_id; 491 found = 1; 492 break; 493 } 494 } 495 if (!found) { 496 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 497 return -EINVAL; 498 } 499 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 500 case AMDGPU_INFO_HW_IP_INFO: { 501 struct drm_amdgpu_info_hw_ip ip = {}; 502 int ret; 503 504 ret = amdgpu_hw_ip_info(adev, info, &ip); 505 if (ret) 506 return ret; 507 508 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 509 return ret ? -EFAULT : 0; 510 } 511 case AMDGPU_INFO_HW_IP_COUNT: { 512 enum amd_ip_block_type type; 513 uint32_t count = 0; 514 515 switch (info->query_hw_ip.type) { 516 case AMDGPU_HW_IP_GFX: 517 type = AMD_IP_BLOCK_TYPE_GFX; 518 break; 519 case AMDGPU_HW_IP_COMPUTE: 520 type = AMD_IP_BLOCK_TYPE_GFX; 521 break; 522 case AMDGPU_HW_IP_DMA: 523 type = AMD_IP_BLOCK_TYPE_SDMA; 524 break; 525 case AMDGPU_HW_IP_UVD: 526 type = AMD_IP_BLOCK_TYPE_UVD; 527 break; 528 case AMDGPU_HW_IP_VCE: 529 type = AMD_IP_BLOCK_TYPE_VCE; 530 break; 531 case AMDGPU_HW_IP_UVD_ENC: 532 type = AMD_IP_BLOCK_TYPE_UVD; 533 break; 534 case AMDGPU_HW_IP_VCN_DEC: 535 case AMDGPU_HW_IP_VCN_ENC: 536 type = AMD_IP_BLOCK_TYPE_VCN; 537 break; 538 case AMDGPU_HW_IP_VCN_JPEG: 539 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 540 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 541 break; 542 default: 543 return -EINVAL; 544 } 545 546 for (i = 0; i < adev->num_ip_blocks; i++) 547 if (adev->ip_blocks[i].version->type == type && 548 adev->ip_blocks[i].status.valid && 549 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 550 count++; 551 552 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 553 } 554 case AMDGPU_INFO_TIMESTAMP: 555 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 556 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 557 case AMDGPU_INFO_FW_VERSION: { 558 struct drm_amdgpu_info_firmware fw_info; 559 int ret; 560 561 /* We only support one instance of each IP block right now. */ 562 if (info->query_fw.ip_instance != 0) 563 return -EINVAL; 564 565 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 566 if (ret) 567 return ret; 568 569 return copy_to_user(out, &fw_info, 570 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 571 } 572 case AMDGPU_INFO_NUM_BYTES_MOVED: 573 ui64 = atomic64_read(&adev->num_bytes_moved); 574 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 575 case AMDGPU_INFO_NUM_EVICTIONS: 576 ui64 = atomic64_read(&adev->num_evictions); 577 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 578 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 579 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 580 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 581 case AMDGPU_INFO_VRAM_USAGE: 582 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 583 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 584 case AMDGPU_INFO_VIS_VRAM_USAGE: 585 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 586 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 587 case AMDGPU_INFO_GTT_USAGE: 588 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 589 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 590 case AMDGPU_INFO_GDS_CONFIG: { 591 struct drm_amdgpu_info_gds gds_info; 592 593 memset(&gds_info, 0, sizeof(gds_info)); 594 gds_info.compute_partition_size = adev->gds.gds_size; 595 gds_info.gds_total_size = adev->gds.gds_size; 596 gds_info.gws_per_compute_partition = adev->gds.gws_size; 597 gds_info.oa_per_compute_partition = adev->gds.oa_size; 598 return copy_to_user(out, &gds_info, 599 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 600 } 601 case AMDGPU_INFO_VRAM_GTT: { 602 struct drm_amdgpu_info_vram_gtt vram_gtt; 603 604 vram_gtt.vram_size = adev->gmc.real_vram_size - 605 atomic64_read(&adev->vram_pin_size) - 606 AMDGPU_VM_RESERVED_VRAM; 607 vram_gtt.vram_cpu_accessible_size = 608 min(adev->gmc.visible_vram_size - 609 atomic64_read(&adev->visible_pin_size), 610 vram_gtt.vram_size); 611 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; 612 vram_gtt.gtt_size *= PAGE_SIZE; 613 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 614 return copy_to_user(out, &vram_gtt, 615 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 616 } 617 case AMDGPU_INFO_MEMORY: { 618 struct drm_amdgpu_memory_info mem; 619 620 memset(&mem, 0, sizeof(mem)); 621 mem.vram.total_heap_size = adev->gmc.real_vram_size; 622 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 623 atomic64_read(&adev->vram_pin_size) - 624 AMDGPU_VM_RESERVED_VRAM; 625 mem.vram.heap_usage = 626 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 627 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 628 629 mem.cpu_accessible_vram.total_heap_size = 630 adev->gmc.visible_vram_size; 631 mem.cpu_accessible_vram.usable_heap_size = 632 min(adev->gmc.visible_vram_size - 633 atomic64_read(&adev->visible_pin_size), 634 mem.vram.usable_heap_size); 635 mem.cpu_accessible_vram.heap_usage = 636 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 637 mem.cpu_accessible_vram.max_allocation = 638 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 639 640 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size; 641 mem.gtt.total_heap_size *= PAGE_SIZE; 642 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 643 atomic64_read(&adev->gart_pin_size); 644 mem.gtt.heap_usage = 645 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); 646 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 647 648 return copy_to_user(out, &mem, 649 min((size_t)size, sizeof(mem))) 650 ? -EFAULT : 0; 651 } 652 case AMDGPU_INFO_READ_MMR_REG: { 653 unsigned n, alloc_size; 654 uint32_t *regs; 655 unsigned se_num = (info->read_mmr_reg.instance >> 656 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 657 AMDGPU_INFO_MMR_SE_INDEX_MASK; 658 unsigned sh_num = (info->read_mmr_reg.instance >> 659 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 660 AMDGPU_INFO_MMR_SH_INDEX_MASK; 661 662 /* set full masks if the userspace set all bits 663 * in the bitfields */ 664 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 665 se_num = 0xffffffff; 666 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 667 sh_num = 0xffffffff; 668 669 if (info->read_mmr_reg.count > 128) 670 return -EINVAL; 671 672 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 673 if (!regs) 674 return -ENOMEM; 675 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 676 677 amdgpu_gfx_off_ctrl(adev, false); 678 for (i = 0; i < info->read_mmr_reg.count; i++) { 679 if (amdgpu_asic_read_register(adev, se_num, sh_num, 680 info->read_mmr_reg.dword_offset + i, 681 ®s[i])) { 682 DRM_DEBUG_KMS("unallowed offset %#x\n", 683 info->read_mmr_reg.dword_offset + i); 684 kfree(regs); 685 amdgpu_gfx_off_ctrl(adev, true); 686 return -EFAULT; 687 } 688 } 689 amdgpu_gfx_off_ctrl(adev, true); 690 n = copy_to_user(out, regs, min(size, alloc_size)); 691 kfree(regs); 692 return n ? -EFAULT : 0; 693 } 694 case AMDGPU_INFO_DEV_INFO: { 695 struct drm_amdgpu_info_device dev_info; 696 uint64_t vm_size; 697 698 memset(&dev_info, 0, sizeof(dev_info)); 699 dev_info.device_id = dev->pdev->device; 700 dev_info.chip_rev = adev->rev_id; 701 dev_info.external_rev = adev->external_rev_id; 702 dev_info.pci_rev = dev->pdev->revision; 703 dev_info.family = adev->family; 704 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 705 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 706 /* return all clocks in KHz */ 707 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 708 if (adev->pm.dpm_enabled) { 709 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 710 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 711 } else { 712 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 713 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 714 } 715 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 716 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 717 adev->gfx.config.max_shader_engines; 718 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 719 dev_info._pad = 0; 720 dev_info.ids_flags = 0; 721 if (adev->flags & AMD_IS_APU) 722 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 723 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 724 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 725 726 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 727 vm_size -= AMDGPU_VA_RESERVED_SIZE; 728 729 /* Older VCE FW versions are buggy and can handle only 40bits */ 730 if (adev->vce.fw_version && 731 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 732 vm_size = min(vm_size, 1ULL << 40); 733 734 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 735 dev_info.virtual_address_max = 736 min(vm_size, AMDGPU_GMC_HOLE_START); 737 738 if (vm_size > AMDGPU_GMC_HOLE_START) { 739 dev_info.high_va_offset = AMDGPU_GMC_HOLE_END; 740 dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 741 } 742 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 743 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 744 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 745 dev_info.cu_active_number = adev->gfx.cu_info.number; 746 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 747 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 748 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 749 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 750 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 751 sizeof(adev->gfx.cu_info.bitmap)); 752 dev_info.vram_type = adev->gmc.vram_type; 753 dev_info.vram_bit_width = adev->gmc.vram_width; 754 dev_info.vce_harvest_config = adev->vce.harvest_config; 755 dev_info.gc_double_offchip_lds_buf = 756 adev->gfx.config.double_offchip_lds_buf; 757 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 758 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 759 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 760 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 761 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 762 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 763 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 764 765 if (adev->family >= AMDGPU_FAMILY_NV) 766 dev_info.pa_sc_tile_steering_override = 767 adev->gfx.config.pa_sc_tile_steering_override; 768 769 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 770 771 return copy_to_user(out, &dev_info, 772 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 773 } 774 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 775 unsigned i; 776 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 777 struct amd_vce_state *vce_state; 778 779 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 780 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 781 if (vce_state) { 782 vce_clk_table.entries[i].sclk = vce_state->sclk; 783 vce_clk_table.entries[i].mclk = vce_state->mclk; 784 vce_clk_table.entries[i].eclk = vce_state->evclk; 785 vce_clk_table.num_valid_entries++; 786 } 787 } 788 789 return copy_to_user(out, &vce_clk_table, 790 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 791 } 792 case AMDGPU_INFO_VBIOS: { 793 uint32_t bios_size = adev->bios_size; 794 795 switch (info->vbios_info.type) { 796 case AMDGPU_INFO_VBIOS_SIZE: 797 return copy_to_user(out, &bios_size, 798 min((size_t)size, sizeof(bios_size))) 799 ? -EFAULT : 0; 800 case AMDGPU_INFO_VBIOS_IMAGE: { 801 uint8_t *bios; 802 uint32_t bios_offset = info->vbios_info.offset; 803 804 if (bios_offset >= bios_size) 805 return -EINVAL; 806 807 bios = adev->bios + bios_offset; 808 return copy_to_user(out, bios, 809 min((size_t)size, (size_t)(bios_size - bios_offset))) 810 ? -EFAULT : 0; 811 } 812 default: 813 DRM_DEBUG_KMS("Invalid request %d\n", 814 info->vbios_info.type); 815 return -EINVAL; 816 } 817 } 818 case AMDGPU_INFO_NUM_HANDLES: { 819 struct drm_amdgpu_info_num_handles handle; 820 821 switch (info->query_hw_ip.type) { 822 case AMDGPU_HW_IP_UVD: 823 /* Starting Polaris, we support unlimited UVD handles */ 824 if (adev->asic_type < CHIP_POLARIS10) { 825 handle.uvd_max_handles = adev->uvd.max_handles; 826 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 827 828 return copy_to_user(out, &handle, 829 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 830 } else { 831 return -ENODATA; 832 } 833 834 break; 835 default: 836 return -EINVAL; 837 } 838 } 839 case AMDGPU_INFO_SENSOR: { 840 if (!adev->pm.dpm_enabled) 841 return -ENOENT; 842 843 switch (info->sensor_info.type) { 844 case AMDGPU_INFO_SENSOR_GFX_SCLK: 845 /* get sclk in Mhz */ 846 if (amdgpu_dpm_read_sensor(adev, 847 AMDGPU_PP_SENSOR_GFX_SCLK, 848 (void *)&ui32, &ui32_size)) { 849 return -EINVAL; 850 } 851 ui32 /= 100; 852 break; 853 case AMDGPU_INFO_SENSOR_GFX_MCLK: 854 /* get mclk in Mhz */ 855 if (amdgpu_dpm_read_sensor(adev, 856 AMDGPU_PP_SENSOR_GFX_MCLK, 857 (void *)&ui32, &ui32_size)) { 858 return -EINVAL; 859 } 860 ui32 /= 100; 861 break; 862 case AMDGPU_INFO_SENSOR_GPU_TEMP: 863 /* get temperature in millidegrees C */ 864 if (amdgpu_dpm_read_sensor(adev, 865 AMDGPU_PP_SENSOR_GPU_TEMP, 866 (void *)&ui32, &ui32_size)) { 867 return -EINVAL; 868 } 869 break; 870 case AMDGPU_INFO_SENSOR_GPU_LOAD: 871 /* get GPU load */ 872 if (amdgpu_dpm_read_sensor(adev, 873 AMDGPU_PP_SENSOR_GPU_LOAD, 874 (void *)&ui32, &ui32_size)) { 875 return -EINVAL; 876 } 877 break; 878 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 879 /* get average GPU power */ 880 if (amdgpu_dpm_read_sensor(adev, 881 AMDGPU_PP_SENSOR_GPU_POWER, 882 (void *)&ui32, &ui32_size)) { 883 return -EINVAL; 884 } 885 ui32 >>= 8; 886 break; 887 case AMDGPU_INFO_SENSOR_VDDNB: 888 /* get VDDNB in millivolts */ 889 if (amdgpu_dpm_read_sensor(adev, 890 AMDGPU_PP_SENSOR_VDDNB, 891 (void *)&ui32, &ui32_size)) { 892 return -EINVAL; 893 } 894 break; 895 case AMDGPU_INFO_SENSOR_VDDGFX: 896 /* get VDDGFX in millivolts */ 897 if (amdgpu_dpm_read_sensor(adev, 898 AMDGPU_PP_SENSOR_VDDGFX, 899 (void *)&ui32, &ui32_size)) { 900 return -EINVAL; 901 } 902 break; 903 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 904 /* get stable pstate sclk in Mhz */ 905 if (amdgpu_dpm_read_sensor(adev, 906 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 907 (void *)&ui32, &ui32_size)) { 908 return -EINVAL; 909 } 910 ui32 /= 100; 911 break; 912 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 913 /* get stable pstate mclk in Mhz */ 914 if (amdgpu_dpm_read_sensor(adev, 915 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 916 (void *)&ui32, &ui32_size)) { 917 return -EINVAL; 918 } 919 ui32 /= 100; 920 break; 921 default: 922 DRM_DEBUG_KMS("Invalid request %d\n", 923 info->sensor_info.type); 924 return -EINVAL; 925 } 926 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 927 } 928 case AMDGPU_INFO_VRAM_LOST_COUNTER: 929 ui32 = atomic_read(&adev->vram_lost_counter); 930 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 931 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 932 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 933 uint64_t ras_mask; 934 935 if (!ras) 936 return -EINVAL; 937 ras_mask = (uint64_t)ras->supported << 32 | ras->features; 938 939 return copy_to_user(out, &ras_mask, 940 min_t(u64, size, sizeof(ras_mask))) ? 941 -EFAULT : 0; 942 } 943 default: 944 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 945 return -EINVAL; 946 } 947 return 0; 948 } 949 950 951 /* 952 * Outdated mess for old drm with Xorg being in charge (void function now). 953 */ 954 /** 955 * amdgpu_driver_lastclose_kms - drm callback for last close 956 * 957 * @dev: drm dev pointer 958 * 959 * Switch vga_switcheroo state after last close (all asics). 960 */ 961 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 962 { 963 drm_fb_helper_lastclose(dev); 964 vga_switcheroo_process_delayed_switch(); 965 } 966 967 /** 968 * amdgpu_driver_open_kms - drm callback for open 969 * 970 * @dev: drm dev pointer 971 * @file_priv: drm file 972 * 973 * On device open, init vm on cayman+ (all asics). 974 * Returns 0 on success, error on failure. 975 */ 976 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 977 { 978 struct amdgpu_device *adev = dev->dev_private; 979 struct amdgpu_fpriv *fpriv; 980 int r, pasid; 981 982 /* Ensure IB tests are run on ring */ 983 flush_delayed_work(&adev->delayed_init_work); 984 985 986 if (amdgpu_ras_intr_triggered()) { 987 DRM_ERROR("RAS Intr triggered, device disabled!!"); 988 return -EHWPOISON; 989 } 990 991 file_priv->driver_priv = NULL; 992 993 r = pm_runtime_get_sync(dev->dev); 994 if (r < 0) 995 return r; 996 997 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 998 if (unlikely(!fpriv)) { 999 r = -ENOMEM; 1000 goto out_suspend; 1001 } 1002 1003 pasid = amdgpu_pasid_alloc(16); 1004 if (pasid < 0) { 1005 dev_warn(adev->dev, "No more PASIDs available!"); 1006 pasid = 0; 1007 } 1008 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 1009 if (r) 1010 goto error_pasid; 1011 1012 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1013 if (!fpriv->prt_va) { 1014 r = -ENOMEM; 1015 goto error_vm; 1016 } 1017 1018 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1019 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1020 1021 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1022 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1023 if (r) 1024 goto error_vm; 1025 } 1026 1027 mutex_init(&fpriv->bo_list_lock); 1028 idr_init(&fpriv->bo_list_handles); 1029 1030 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1031 1032 file_priv->driver_priv = fpriv; 1033 goto out_suspend; 1034 1035 error_vm: 1036 amdgpu_vm_fini(adev, &fpriv->vm); 1037 1038 error_pasid: 1039 if (pasid) 1040 amdgpu_pasid_free(pasid); 1041 1042 kfree(fpriv); 1043 1044 out_suspend: 1045 pm_runtime_mark_last_busy(dev->dev); 1046 pm_runtime_put_autosuspend(dev->dev); 1047 1048 return r; 1049 } 1050 1051 /** 1052 * amdgpu_driver_postclose_kms - drm callback for post close 1053 * 1054 * @dev: drm dev pointer 1055 * @file_priv: drm file 1056 * 1057 * On device post close, tear down vm on cayman+ (all asics). 1058 */ 1059 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1060 struct drm_file *file_priv) 1061 { 1062 struct amdgpu_device *adev = dev->dev_private; 1063 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1064 struct amdgpu_bo_list *list; 1065 struct amdgpu_bo *pd; 1066 unsigned int pasid; 1067 int handle; 1068 1069 if (!fpriv) 1070 return; 1071 1072 pm_runtime_get_sync(dev->dev); 1073 1074 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1075 amdgpu_uvd_free_handles(adev, file_priv); 1076 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1077 amdgpu_vce_free_handles(adev, file_priv); 1078 1079 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1080 1081 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1082 /* TODO: how to handle reserve failure */ 1083 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1084 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1085 fpriv->csa_va = NULL; 1086 amdgpu_bo_unreserve(adev->virt.csa_obj); 1087 } 1088 1089 pasid = fpriv->vm.pasid; 1090 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 1091 1092 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1093 amdgpu_vm_fini(adev, &fpriv->vm); 1094 1095 if (pasid) 1096 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1097 amdgpu_bo_unref(&pd); 1098 1099 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1100 amdgpu_bo_list_put(list); 1101 1102 idr_destroy(&fpriv->bo_list_handles); 1103 mutex_destroy(&fpriv->bo_list_lock); 1104 1105 kfree(fpriv); 1106 file_priv->driver_priv = NULL; 1107 1108 pm_runtime_mark_last_busy(dev->dev); 1109 pm_runtime_put_autosuspend(dev->dev); 1110 } 1111 1112 /* 1113 * VBlank related functions. 1114 */ 1115 /** 1116 * amdgpu_get_vblank_counter_kms - get frame count 1117 * 1118 * @crtc: crtc to get the frame count from 1119 * 1120 * Gets the frame count on the requested crtc (all asics). 1121 * Returns frame count on success, -EINVAL on failure. 1122 */ 1123 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1124 { 1125 struct drm_device *dev = crtc->dev; 1126 unsigned int pipe = crtc->index; 1127 struct amdgpu_device *adev = dev->dev_private; 1128 int vpos, hpos, stat; 1129 u32 count; 1130 1131 if (pipe >= adev->mode_info.num_crtc) { 1132 DRM_ERROR("Invalid crtc %u\n", pipe); 1133 return -EINVAL; 1134 } 1135 1136 /* The hw increments its frame counter at start of vsync, not at start 1137 * of vblank, as is required by DRM core vblank counter handling. 1138 * Cook the hw count here to make it appear to the caller as if it 1139 * incremented at start of vblank. We measure distance to start of 1140 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1141 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1142 * result by 1 to give the proper appearance to caller. 1143 */ 1144 if (adev->mode_info.crtcs[pipe]) { 1145 /* Repeat readout if needed to provide stable result if 1146 * we cross start of vsync during the queries. 1147 */ 1148 do { 1149 count = amdgpu_display_vblank_get_counter(adev, pipe); 1150 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1151 * vpos as distance to start of vblank, instead of 1152 * regular vertical scanout pos. 1153 */ 1154 stat = amdgpu_display_get_crtc_scanoutpos( 1155 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1156 &vpos, &hpos, NULL, NULL, 1157 &adev->mode_info.crtcs[pipe]->base.hwmode); 1158 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1159 1160 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1161 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1162 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1163 } else { 1164 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1165 pipe, vpos); 1166 1167 /* Bump counter if we are at >= leading edge of vblank, 1168 * but before vsync where vpos would turn negative and 1169 * the hw counter really increments. 1170 */ 1171 if (vpos >= 0) 1172 count++; 1173 } 1174 } else { 1175 /* Fallback to use value as is. */ 1176 count = amdgpu_display_vblank_get_counter(adev, pipe); 1177 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1178 } 1179 1180 return count; 1181 } 1182 1183 /** 1184 * amdgpu_enable_vblank_kms - enable vblank interrupt 1185 * 1186 * @crtc: crtc to enable vblank interrupt for 1187 * 1188 * Enable the interrupt on the requested crtc (all asics). 1189 * Returns 0 on success, -EINVAL on failure. 1190 */ 1191 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1192 { 1193 struct drm_device *dev = crtc->dev; 1194 unsigned int pipe = crtc->index; 1195 struct amdgpu_device *adev = dev->dev_private; 1196 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1197 1198 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1199 } 1200 1201 /** 1202 * amdgpu_disable_vblank_kms - disable vblank interrupt 1203 * 1204 * @crtc: crtc to disable vblank interrupt for 1205 * 1206 * Disable the interrupt on the requested crtc (all asics). 1207 */ 1208 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1209 { 1210 struct drm_device *dev = crtc->dev; 1211 unsigned int pipe = crtc->index; 1212 struct amdgpu_device *adev = dev->dev_private; 1213 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1214 1215 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1216 } 1217 1218 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1219 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1220 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1221 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1222 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1223 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1224 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1225 /* KMS */ 1226 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1227 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1228 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1229 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1230 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1231 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1232 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1233 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1234 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1235 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 1236 }; 1237 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1238 1239 /* 1240 * Debugfs info 1241 */ 1242 #if defined(CONFIG_DEBUG_FS) 1243 1244 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1245 { 1246 struct drm_info_node *node = (struct drm_info_node *) m->private; 1247 struct drm_device *dev = node->minor->dev; 1248 struct amdgpu_device *adev = dev->dev_private; 1249 struct drm_amdgpu_info_firmware fw_info; 1250 struct drm_amdgpu_query_fw query_fw; 1251 struct atom_context *ctx = adev->mode_info.atom_context; 1252 int ret, i; 1253 1254 /* VCE */ 1255 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1256 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1257 if (ret) 1258 return ret; 1259 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1260 fw_info.feature, fw_info.ver); 1261 1262 /* UVD */ 1263 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1264 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1265 if (ret) 1266 return ret; 1267 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1268 fw_info.feature, fw_info.ver); 1269 1270 /* GMC */ 1271 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1272 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1273 if (ret) 1274 return ret; 1275 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1276 fw_info.feature, fw_info.ver); 1277 1278 /* ME */ 1279 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1280 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1281 if (ret) 1282 return ret; 1283 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1284 fw_info.feature, fw_info.ver); 1285 1286 /* PFP */ 1287 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1288 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1289 if (ret) 1290 return ret; 1291 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1292 fw_info.feature, fw_info.ver); 1293 1294 /* CE */ 1295 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1296 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1297 if (ret) 1298 return ret; 1299 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1300 fw_info.feature, fw_info.ver); 1301 1302 /* RLC */ 1303 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1304 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1305 if (ret) 1306 return ret; 1307 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1308 fw_info.feature, fw_info.ver); 1309 1310 /* RLC SAVE RESTORE LIST CNTL */ 1311 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1312 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1313 if (ret) 1314 return ret; 1315 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1316 fw_info.feature, fw_info.ver); 1317 1318 /* RLC SAVE RESTORE LIST GPM MEM */ 1319 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1320 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1321 if (ret) 1322 return ret; 1323 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1324 fw_info.feature, fw_info.ver); 1325 1326 /* RLC SAVE RESTORE LIST SRM MEM */ 1327 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1328 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1329 if (ret) 1330 return ret; 1331 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1332 fw_info.feature, fw_info.ver); 1333 1334 /* MEC */ 1335 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1336 query_fw.index = 0; 1337 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1338 if (ret) 1339 return ret; 1340 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1341 fw_info.feature, fw_info.ver); 1342 1343 /* MEC2 */ 1344 if (adev->asic_type == CHIP_KAVERI || 1345 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { 1346 query_fw.index = 1; 1347 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1348 if (ret) 1349 return ret; 1350 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1351 fw_info.feature, fw_info.ver); 1352 } 1353 1354 /* PSP SOS */ 1355 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1356 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1357 if (ret) 1358 return ret; 1359 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1360 fw_info.feature, fw_info.ver); 1361 1362 1363 /* PSP ASD */ 1364 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1365 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1366 if (ret) 1367 return ret; 1368 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1369 fw_info.feature, fw_info.ver); 1370 1371 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1372 for (i = 0; i < 2; i++) { 1373 query_fw.index = i; 1374 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1375 if (ret) 1376 continue; 1377 seq_printf(m, "TA %s feature version: %u, firmware version: 0x%08x\n", 1378 i ? "RAS" : "XGMI", fw_info.feature, fw_info.ver); 1379 } 1380 1381 /* SMC */ 1382 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1383 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1384 if (ret) 1385 return ret; 1386 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1387 fw_info.feature, fw_info.ver); 1388 1389 /* SDMA */ 1390 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1391 for (i = 0; i < adev->sdma.num_instances; i++) { 1392 query_fw.index = i; 1393 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1394 if (ret) 1395 return ret; 1396 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1397 i, fw_info.feature, fw_info.ver); 1398 } 1399 1400 /* VCN */ 1401 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1402 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1403 if (ret) 1404 return ret; 1405 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1406 fw_info.feature, fw_info.ver); 1407 1408 /* DMCU */ 1409 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1410 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1411 if (ret) 1412 return ret; 1413 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1414 fw_info.feature, fw_info.ver); 1415 1416 /* DMCUB */ 1417 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1418 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1419 if (ret) 1420 return ret; 1421 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1422 fw_info.feature, fw_info.ver); 1423 1424 1425 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1426 1427 return 0; 1428 } 1429 1430 static const struct drm_info_list amdgpu_firmware_info_list[] = { 1431 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1432 }; 1433 #endif 1434 1435 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1436 { 1437 #if defined(CONFIG_DEBUG_FS) 1438 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1439 ARRAY_SIZE(amdgpu_firmware_info_list)); 1440 #else 1441 return 0; 1442 #endif 1443 } 1444