1 /* 2 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems) 3 * 4 * Copyright (C) 2014 Atmel Corporation 5 * 6 * Author: Ludovic Desroches <ludovic.desroches@atmel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include <asm/barrier.h> 22 #include <dt-bindings/dma/at91.h> 23 #include <linux/clk.h> 24 #include <linux/dmaengine.h> 25 #include <linux/dmapool.h> 26 #include <linux/interrupt.h> 27 #include <linux/irq.h> 28 #include <linux/kernel.h> 29 #include <linux/list.h> 30 #include <linux/module.h> 31 #include <linux/of_dma.h> 32 #include <linux/of_platform.h> 33 #include <linux/platform_device.h> 34 #include <linux/pm.h> 35 36 #include "dmaengine.h" 37 38 /* Global registers */ 39 #define AT_XDMAC_GTYPE 0x00 /* Global Type Register */ 40 #define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */ 41 #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */ 42 #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */ 43 #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */ 44 #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */ 45 #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */ 46 #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */ 47 #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */ 48 #define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */ 49 #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */ 50 #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */ 51 #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */ 52 #define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */ 53 #define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */ 54 #define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */ 55 #define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */ 56 #define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */ 57 #define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */ 58 #define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */ 59 #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */ 60 61 /* Channel relative registers offsets */ 62 #define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */ 63 #define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */ 64 #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */ 65 #define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */ 66 #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */ 67 #define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */ 68 #define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */ 69 #define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */ 70 #define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */ 71 #define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */ 72 #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */ 73 #define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */ 74 #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */ 75 #define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */ 76 #define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */ 77 #define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */ 78 #define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */ 79 #define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */ 80 #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */ 81 #define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */ 82 #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */ 83 #define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */ 84 #define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */ 85 #define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */ 86 #define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */ 87 #define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */ 88 #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */ 89 #define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */ 90 #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */ 91 #define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */ 92 #define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */ 93 #define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */ 94 #define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */ 95 #define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */ 96 #define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */ 97 #define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */ 98 #define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */ 99 #define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */ 100 #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */ 101 #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */ 102 #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */ 103 #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */ 104 #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */ 105 #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */ 106 #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */ 107 #define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */ 108 #define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */ 109 #define AT_XDMAC_CC 0x28 /* Channel Configuration Register */ 110 #define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */ 111 #define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */ 112 #define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */ 113 #define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1) 114 #define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1) 115 #define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1) 116 #define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1) 117 #define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1) 118 #define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */ 119 #define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4) 120 #define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4) 121 #define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */ 122 #define AT_XDMAC_CC_PROT_SEC (0x0 << 5) 123 #define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5) 124 #define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */ 125 #define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6) 126 #define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6) 127 #define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */ 128 #define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7) 129 #define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7) 130 #define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */ 131 #define AT_XDMAC_CC_DWIDTH_OFFSET 11 132 #define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET) 133 #define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */ 134 #define AT_XDMAC_CC_DWIDTH_BYTE 0x0 135 #define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1 136 #define AT_XDMAC_CC_DWIDTH_WORD 0x2 137 #define AT_XDMAC_CC_DWIDTH_DWORD 0x3 138 #define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */ 139 #define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */ 140 #define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */ 141 #define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16) 142 #define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16) 143 #define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16) 144 #define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16) 145 #define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */ 146 #define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18) 147 #define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18) 148 #define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18) 149 #define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18) 150 #define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */ 151 #define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21) 152 #define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21) 153 #define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */ 154 #define AT_XDMAC_CC_RDIP_DONE (0x0 << 22) 155 #define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22) 156 #define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */ 157 #define AT_XDMAC_CC_WRIP_DONE (0x0 << 23) 158 #define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23) 159 #define AT_XDMAC_CC_PERID(i) (0x7f & (i) << 24) /* Channel Peripheral Identifier */ 160 #define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */ 161 #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */ 162 #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */ 163 164 #define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */ 165 166 /* Microblock control members */ 167 #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */ 168 #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */ 169 #define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */ 170 #define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */ 171 #define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */ 172 #define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */ 173 #define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */ 174 #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */ 175 176 #define AT_XDMAC_MAX_CHAN 0x20 177 #define AT_XDMAC_MAX_CSIZE 16 /* 16 data */ 178 #define AT_XDMAC_MAX_DWIDTH 8 /* 64 bits */ 179 #define AT_XDMAC_RESIDUE_MAX_RETRIES 5 180 181 #define AT_XDMAC_DMA_BUSWIDTHS\ 182 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\ 183 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\ 184 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\ 185 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\ 186 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) 187 188 enum atc_status { 189 AT_XDMAC_CHAN_IS_CYCLIC = 0, 190 AT_XDMAC_CHAN_IS_PAUSED, 191 }; 192 193 /* ----- Channels ----- */ 194 struct at_xdmac_chan { 195 struct dma_chan chan; 196 void __iomem *ch_regs; 197 u32 mask; /* Channel Mask */ 198 u32 cfg; /* Channel Configuration Register */ 199 u8 perid; /* Peripheral ID */ 200 u8 perif; /* Peripheral Interface */ 201 u8 memif; /* Memory Interface */ 202 u32 save_cc; 203 u32 save_cim; 204 u32 save_cnda; 205 u32 save_cndc; 206 u32 irq_status; 207 unsigned long status; 208 struct tasklet_struct tasklet; 209 struct dma_slave_config sconfig; 210 211 spinlock_t lock; 212 213 struct list_head xfers_list; 214 struct list_head free_descs_list; 215 }; 216 217 218 /* ----- Controller ----- */ 219 struct at_xdmac { 220 struct dma_device dma; 221 void __iomem *regs; 222 int irq; 223 struct clk *clk; 224 u32 save_gim; 225 struct dma_pool *at_xdmac_desc_pool; 226 struct at_xdmac_chan chan[0]; 227 }; 228 229 230 /* ----- Descriptors ----- */ 231 232 /* Linked List Descriptor */ 233 struct at_xdmac_lld { 234 dma_addr_t mbr_nda; /* Next Descriptor Member */ 235 u32 mbr_ubc; /* Microblock Control Member */ 236 dma_addr_t mbr_sa; /* Source Address Member */ 237 dma_addr_t mbr_da; /* Destination Address Member */ 238 u32 mbr_cfg; /* Configuration Register */ 239 u32 mbr_bc; /* Block Control Register */ 240 u32 mbr_ds; /* Data Stride Register */ 241 u32 mbr_sus; /* Source Microblock Stride Register */ 242 u32 mbr_dus; /* Destination Microblock Stride Register */ 243 }; 244 245 /* 64-bit alignment needed to update CNDA and CUBC registers in an atomic way. */ 246 struct at_xdmac_desc { 247 struct at_xdmac_lld lld; 248 enum dma_transfer_direction direction; 249 struct dma_async_tx_descriptor tx_dma_desc; 250 struct list_head desc_node; 251 /* Following members are only used by the first descriptor */ 252 bool active_xfer; 253 unsigned int xfer_size; 254 struct list_head descs_list; 255 struct list_head xfer_node; 256 } __aligned(sizeof(u64)); 257 258 static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb) 259 { 260 return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40); 261 } 262 263 #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg)) 264 #define at_xdmac_write(atxdmac, reg, value) \ 265 writel_relaxed((value), (atxdmac)->regs + (reg)) 266 267 #define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg)) 268 #define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg)) 269 270 static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan) 271 { 272 return container_of(dchan, struct at_xdmac_chan, chan); 273 } 274 275 static struct device *chan2dev(struct dma_chan *chan) 276 { 277 return &chan->dev->device; 278 } 279 280 static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev) 281 { 282 return container_of(ddev, struct at_xdmac, dma); 283 } 284 285 static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd) 286 { 287 return container_of(txd, struct at_xdmac_desc, tx_dma_desc); 288 } 289 290 static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan) 291 { 292 return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status); 293 } 294 295 static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan) 296 { 297 return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); 298 } 299 300 static inline int at_xdmac_csize(u32 maxburst) 301 { 302 int csize; 303 304 csize = ffs(maxburst) - 1; 305 if (csize > 4) 306 csize = -EINVAL; 307 308 return csize; 309 }; 310 311 static inline bool at_xdmac_chan_is_peripheral_xfer(u32 cfg) 312 { 313 return cfg & AT_XDMAC_CC_TYPE_PER_TRAN; 314 } 315 316 static inline u8 at_xdmac_get_dwidth(u32 cfg) 317 { 318 return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET; 319 }; 320 321 static unsigned int init_nr_desc_per_channel = 64; 322 module_param(init_nr_desc_per_channel, uint, 0644); 323 MODULE_PARM_DESC(init_nr_desc_per_channel, 324 "initial descriptors per channel (default: 64)"); 325 326 327 static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan) 328 { 329 return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask; 330 } 331 332 static void at_xdmac_off(struct at_xdmac *atxdmac) 333 { 334 at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L); 335 336 /* Wait that all chans are disabled. */ 337 while (at_xdmac_read(atxdmac, AT_XDMAC_GS)) 338 cpu_relax(); 339 340 at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L); 341 } 342 343 /* Call with lock hold. */ 344 static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan, 345 struct at_xdmac_desc *first) 346 { 347 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); 348 u32 reg; 349 350 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first); 351 352 if (at_xdmac_chan_is_enabled(atchan)) 353 return; 354 355 /* Set transfer as active to not try to start it again. */ 356 first->active_xfer = true; 357 358 /* Tell xdmac where to get the first descriptor. */ 359 reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys) 360 | AT_XDMAC_CNDA_NDAIF(atchan->memif); 361 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg); 362 363 /* 364 * When doing non cyclic transfer we need to use the next 365 * descriptor view 2 since some fields of the configuration register 366 * depend on transfer size and src/dest addresses. 367 */ 368 if (at_xdmac_chan_is_cyclic(atchan)) 369 reg = AT_XDMAC_CNDC_NDVIEW_NDV1; 370 else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3) 371 reg = AT_XDMAC_CNDC_NDVIEW_NDV3; 372 else 373 reg = AT_XDMAC_CNDC_NDVIEW_NDV2; 374 /* 375 * Even if the register will be updated from the configuration in the 376 * descriptor when using view 2 or higher, the PROT bit won't be set 377 * properly. This bit can be modified only by using the channel 378 * configuration register. 379 */ 380 at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg); 381 382 reg |= AT_XDMAC_CNDC_NDDUP 383 | AT_XDMAC_CNDC_NDSUP 384 | AT_XDMAC_CNDC_NDE; 385 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg); 386 387 dev_vdbg(chan2dev(&atchan->chan), 388 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", 389 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC), 390 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), 391 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC), 392 at_xdmac_chan_read(atchan, AT_XDMAC_CSA), 393 at_xdmac_chan_read(atchan, AT_XDMAC_CDA), 394 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC)); 395 396 at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff); 397 reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE; 398 /* 399 * Request Overflow Error is only for peripheral synchronized transfers 400 */ 401 if (at_xdmac_chan_is_peripheral_xfer(first->lld.mbr_cfg)) 402 reg |= AT_XDMAC_CIE_ROIE; 403 404 /* 405 * There is no end of list when doing cyclic dma, we need to get 406 * an interrupt after each periods. 407 */ 408 if (at_xdmac_chan_is_cyclic(atchan)) 409 at_xdmac_chan_write(atchan, AT_XDMAC_CIE, 410 reg | AT_XDMAC_CIE_BIE); 411 else 412 at_xdmac_chan_write(atchan, AT_XDMAC_CIE, 413 reg | AT_XDMAC_CIE_LIE); 414 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask); 415 dev_vdbg(chan2dev(&atchan->chan), 416 "%s: enable channel (0x%08x)\n", __func__, atchan->mask); 417 wmb(); 418 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); 419 420 dev_vdbg(chan2dev(&atchan->chan), 421 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", 422 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC), 423 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), 424 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC), 425 at_xdmac_chan_read(atchan, AT_XDMAC_CSA), 426 at_xdmac_chan_read(atchan, AT_XDMAC_CDA), 427 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC)); 428 429 } 430 431 static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx) 432 { 433 struct at_xdmac_desc *desc = txd_to_at_desc(tx); 434 struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan); 435 dma_cookie_t cookie; 436 unsigned long irqflags; 437 438 spin_lock_irqsave(&atchan->lock, irqflags); 439 cookie = dma_cookie_assign(tx); 440 441 dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n", 442 __func__, atchan, desc); 443 list_add_tail(&desc->xfer_node, &atchan->xfers_list); 444 if (list_is_singular(&atchan->xfers_list)) 445 at_xdmac_start_xfer(atchan, desc); 446 447 spin_unlock_irqrestore(&atchan->lock, irqflags); 448 return cookie; 449 } 450 451 static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan, 452 gfp_t gfp_flags) 453 { 454 struct at_xdmac_desc *desc; 455 struct at_xdmac *atxdmac = to_at_xdmac(chan->device); 456 dma_addr_t phys; 457 458 desc = dma_pool_zalloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys); 459 if (desc) { 460 INIT_LIST_HEAD(&desc->descs_list); 461 dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan); 462 desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit; 463 desc->tx_dma_desc.phys = phys; 464 } 465 466 return desc; 467 } 468 469 static void at_xdmac_init_used_desc(struct at_xdmac_desc *desc) 470 { 471 memset(&desc->lld, 0, sizeof(desc->lld)); 472 INIT_LIST_HEAD(&desc->descs_list); 473 desc->direction = DMA_TRANS_NONE; 474 desc->xfer_size = 0; 475 desc->active_xfer = false; 476 } 477 478 /* Call must be protected by lock. */ 479 static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan) 480 { 481 struct at_xdmac_desc *desc; 482 483 if (list_empty(&atchan->free_descs_list)) { 484 desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT); 485 } else { 486 desc = list_first_entry(&atchan->free_descs_list, 487 struct at_xdmac_desc, desc_node); 488 list_del(&desc->desc_node); 489 at_xdmac_init_used_desc(desc); 490 } 491 492 return desc; 493 } 494 495 static void at_xdmac_queue_desc(struct dma_chan *chan, 496 struct at_xdmac_desc *prev, 497 struct at_xdmac_desc *desc) 498 { 499 if (!prev || !desc) 500 return; 501 502 prev->lld.mbr_nda = desc->tx_dma_desc.phys; 503 prev->lld.mbr_ubc |= AT_XDMAC_MBR_UBC_NDE; 504 505 dev_dbg(chan2dev(chan), "%s: chain lld: prev=0x%p, mbr_nda=%pad\n", 506 __func__, prev, &prev->lld.mbr_nda); 507 } 508 509 static inline void at_xdmac_increment_block_count(struct dma_chan *chan, 510 struct at_xdmac_desc *desc) 511 { 512 if (!desc) 513 return; 514 515 desc->lld.mbr_bc++; 516 517 dev_dbg(chan2dev(chan), 518 "%s: incrementing the block count of the desc 0x%p\n", 519 __func__, desc); 520 } 521 522 static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec, 523 struct of_dma *of_dma) 524 { 525 struct at_xdmac *atxdmac = of_dma->of_dma_data; 526 struct at_xdmac_chan *atchan; 527 struct dma_chan *chan; 528 struct device *dev = atxdmac->dma.dev; 529 530 if (dma_spec->args_count != 1) { 531 dev_err(dev, "dma phandler args: bad number of args\n"); 532 return NULL; 533 } 534 535 chan = dma_get_any_slave_channel(&atxdmac->dma); 536 if (!chan) { 537 dev_err(dev, "can't get a dma channel\n"); 538 return NULL; 539 } 540 541 atchan = to_at_xdmac_chan(chan); 542 atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]); 543 atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]); 544 atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]); 545 dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n", 546 atchan->memif, atchan->perif, atchan->perid); 547 548 return chan; 549 } 550 551 static int at_xdmac_compute_chan_conf(struct dma_chan *chan, 552 enum dma_transfer_direction direction) 553 { 554 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 555 int csize, dwidth; 556 557 if (direction == DMA_DEV_TO_MEM) { 558 atchan->cfg = 559 AT91_XDMAC_DT_PERID(atchan->perid) 560 | AT_XDMAC_CC_DAM_INCREMENTED_AM 561 | AT_XDMAC_CC_SAM_FIXED_AM 562 | AT_XDMAC_CC_DIF(atchan->memif) 563 | AT_XDMAC_CC_SIF(atchan->perif) 564 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED 565 | AT_XDMAC_CC_DSYNC_PER2MEM 566 | AT_XDMAC_CC_MBSIZE_SIXTEEN 567 | AT_XDMAC_CC_TYPE_PER_TRAN; 568 csize = ffs(atchan->sconfig.src_maxburst) - 1; 569 if (csize < 0) { 570 dev_err(chan2dev(chan), "invalid src maxburst value\n"); 571 return -EINVAL; 572 } 573 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize); 574 dwidth = ffs(atchan->sconfig.src_addr_width) - 1; 575 if (dwidth < 0) { 576 dev_err(chan2dev(chan), "invalid src addr width value\n"); 577 return -EINVAL; 578 } 579 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth); 580 } else if (direction == DMA_MEM_TO_DEV) { 581 atchan->cfg = 582 AT91_XDMAC_DT_PERID(atchan->perid) 583 | AT_XDMAC_CC_DAM_FIXED_AM 584 | AT_XDMAC_CC_SAM_INCREMENTED_AM 585 | AT_XDMAC_CC_DIF(atchan->perif) 586 | AT_XDMAC_CC_SIF(atchan->memif) 587 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED 588 | AT_XDMAC_CC_DSYNC_MEM2PER 589 | AT_XDMAC_CC_MBSIZE_SIXTEEN 590 | AT_XDMAC_CC_TYPE_PER_TRAN; 591 csize = ffs(atchan->sconfig.dst_maxburst) - 1; 592 if (csize < 0) { 593 dev_err(chan2dev(chan), "invalid src maxburst value\n"); 594 return -EINVAL; 595 } 596 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize); 597 dwidth = ffs(atchan->sconfig.dst_addr_width) - 1; 598 if (dwidth < 0) { 599 dev_err(chan2dev(chan), "invalid dst addr width value\n"); 600 return -EINVAL; 601 } 602 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth); 603 } 604 605 dev_dbg(chan2dev(chan), "%s: cfg=0x%08x\n", __func__, atchan->cfg); 606 607 return 0; 608 } 609 610 /* 611 * Only check that maxburst and addr width values are supported by the 612 * the controller but not that the configuration is good to perform the 613 * transfer since we don't know the direction at this stage. 614 */ 615 static int at_xdmac_check_slave_config(struct dma_slave_config *sconfig) 616 { 617 if ((sconfig->src_maxburst > AT_XDMAC_MAX_CSIZE) 618 || (sconfig->dst_maxburst > AT_XDMAC_MAX_CSIZE)) 619 return -EINVAL; 620 621 if ((sconfig->src_addr_width > AT_XDMAC_MAX_DWIDTH) 622 || (sconfig->dst_addr_width > AT_XDMAC_MAX_DWIDTH)) 623 return -EINVAL; 624 625 return 0; 626 } 627 628 static int at_xdmac_set_slave_config(struct dma_chan *chan, 629 struct dma_slave_config *sconfig) 630 { 631 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 632 633 if (at_xdmac_check_slave_config(sconfig)) { 634 dev_err(chan2dev(chan), "invalid slave configuration\n"); 635 return -EINVAL; 636 } 637 638 memcpy(&atchan->sconfig, sconfig, sizeof(atchan->sconfig)); 639 640 return 0; 641 } 642 643 static struct dma_async_tx_descriptor * 644 at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 645 unsigned int sg_len, enum dma_transfer_direction direction, 646 unsigned long flags, void *context) 647 { 648 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 649 struct at_xdmac_desc *first = NULL, *prev = NULL; 650 struct scatterlist *sg; 651 int i; 652 unsigned int xfer_size = 0; 653 unsigned long irqflags; 654 struct dma_async_tx_descriptor *ret = NULL; 655 656 if (!sgl) 657 return NULL; 658 659 if (!is_slave_direction(direction)) { 660 dev_err(chan2dev(chan), "invalid DMA direction\n"); 661 return NULL; 662 } 663 664 dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n", 665 __func__, sg_len, 666 direction == DMA_MEM_TO_DEV ? "to device" : "from device", 667 flags); 668 669 /* Protect dma_sconfig field that can be modified by set_slave_conf. */ 670 spin_lock_irqsave(&atchan->lock, irqflags); 671 672 if (at_xdmac_compute_chan_conf(chan, direction)) 673 goto spin_unlock; 674 675 /* Prepare descriptors. */ 676 for_each_sg(sgl, sg, sg_len, i) { 677 struct at_xdmac_desc *desc = NULL; 678 u32 len, mem, dwidth, fixed_dwidth; 679 680 len = sg_dma_len(sg); 681 mem = sg_dma_address(sg); 682 if (unlikely(!len)) { 683 dev_err(chan2dev(chan), "sg data length is zero\n"); 684 goto spin_unlock; 685 } 686 dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n", 687 __func__, i, len, mem); 688 689 desc = at_xdmac_get_desc(atchan); 690 if (!desc) { 691 dev_err(chan2dev(chan), "can't get descriptor\n"); 692 if (first) 693 list_splice_init(&first->descs_list, &atchan->free_descs_list); 694 goto spin_unlock; 695 } 696 697 /* Linked list descriptor setup. */ 698 if (direction == DMA_DEV_TO_MEM) { 699 desc->lld.mbr_sa = atchan->sconfig.src_addr; 700 desc->lld.mbr_da = mem; 701 } else { 702 desc->lld.mbr_sa = mem; 703 desc->lld.mbr_da = atchan->sconfig.dst_addr; 704 } 705 dwidth = at_xdmac_get_dwidth(atchan->cfg); 706 fixed_dwidth = IS_ALIGNED(len, 1 << dwidth) 707 ? dwidth 708 : AT_XDMAC_CC_DWIDTH_BYTE; 709 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */ 710 | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */ 711 | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */ 712 | (len >> fixed_dwidth); /* microblock length */ 713 desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) | 714 AT_XDMAC_CC_DWIDTH(fixed_dwidth); 715 dev_dbg(chan2dev(chan), 716 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", 717 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc); 718 719 /* Chain lld. */ 720 if (prev) 721 at_xdmac_queue_desc(chan, prev, desc); 722 723 prev = desc; 724 if (!first) 725 first = desc; 726 727 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", 728 __func__, desc, first); 729 list_add_tail(&desc->desc_node, &first->descs_list); 730 xfer_size += len; 731 } 732 733 734 first->tx_dma_desc.flags = flags; 735 first->xfer_size = xfer_size; 736 first->direction = direction; 737 ret = &first->tx_dma_desc; 738 739 spin_unlock: 740 spin_unlock_irqrestore(&atchan->lock, irqflags); 741 return ret; 742 } 743 744 static struct dma_async_tx_descriptor * 745 at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, 746 size_t buf_len, size_t period_len, 747 enum dma_transfer_direction direction, 748 unsigned long flags) 749 { 750 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 751 struct at_xdmac_desc *first = NULL, *prev = NULL; 752 unsigned int periods = buf_len / period_len; 753 int i; 754 unsigned long irqflags; 755 756 dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n", 757 __func__, &buf_addr, buf_len, period_len, 758 direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags); 759 760 if (!is_slave_direction(direction)) { 761 dev_err(chan2dev(chan), "invalid DMA direction\n"); 762 return NULL; 763 } 764 765 if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) { 766 dev_err(chan2dev(chan), "channel currently used\n"); 767 return NULL; 768 } 769 770 if (at_xdmac_compute_chan_conf(chan, direction)) 771 return NULL; 772 773 for (i = 0; i < periods; i++) { 774 struct at_xdmac_desc *desc = NULL; 775 776 spin_lock_irqsave(&atchan->lock, irqflags); 777 desc = at_xdmac_get_desc(atchan); 778 if (!desc) { 779 dev_err(chan2dev(chan), "can't get descriptor\n"); 780 if (first) 781 list_splice_init(&first->descs_list, &atchan->free_descs_list); 782 spin_unlock_irqrestore(&atchan->lock, irqflags); 783 return NULL; 784 } 785 spin_unlock_irqrestore(&atchan->lock, irqflags); 786 dev_dbg(chan2dev(chan), 787 "%s: desc=0x%p, tx_dma_desc.phys=%pad\n", 788 __func__, desc, &desc->tx_dma_desc.phys); 789 790 if (direction == DMA_DEV_TO_MEM) { 791 desc->lld.mbr_sa = atchan->sconfig.src_addr; 792 desc->lld.mbr_da = buf_addr + i * period_len; 793 } else { 794 desc->lld.mbr_sa = buf_addr + i * period_len; 795 desc->lld.mbr_da = atchan->sconfig.dst_addr; 796 } 797 desc->lld.mbr_cfg = atchan->cfg; 798 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1 799 | AT_XDMAC_MBR_UBC_NDEN 800 | AT_XDMAC_MBR_UBC_NSEN 801 | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg); 802 803 dev_dbg(chan2dev(chan), 804 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", 805 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc); 806 807 /* Chain lld. */ 808 if (prev) 809 at_xdmac_queue_desc(chan, prev, desc); 810 811 prev = desc; 812 if (!first) 813 first = desc; 814 815 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", 816 __func__, desc, first); 817 list_add_tail(&desc->desc_node, &first->descs_list); 818 } 819 820 at_xdmac_queue_desc(chan, prev, first); 821 first->tx_dma_desc.flags = flags; 822 first->xfer_size = buf_len; 823 first->direction = direction; 824 825 return &first->tx_dma_desc; 826 } 827 828 static inline u32 at_xdmac_align_width(struct dma_chan *chan, dma_addr_t addr) 829 { 830 u32 width; 831 832 /* 833 * Check address alignment to select the greater data width we 834 * can use. 835 * 836 * Some XDMAC implementations don't provide dword transfer, in 837 * this case selecting dword has the same behavior as 838 * selecting word transfers. 839 */ 840 if (!(addr & 7)) { 841 width = AT_XDMAC_CC_DWIDTH_DWORD; 842 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__); 843 } else if (!(addr & 3)) { 844 width = AT_XDMAC_CC_DWIDTH_WORD; 845 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__); 846 } else if (!(addr & 1)) { 847 width = AT_XDMAC_CC_DWIDTH_HALFWORD; 848 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__); 849 } else { 850 width = AT_XDMAC_CC_DWIDTH_BYTE; 851 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__); 852 } 853 854 return width; 855 } 856 857 static struct at_xdmac_desc * 858 at_xdmac_interleaved_queue_desc(struct dma_chan *chan, 859 struct at_xdmac_chan *atchan, 860 struct at_xdmac_desc *prev, 861 dma_addr_t src, dma_addr_t dst, 862 struct dma_interleaved_template *xt, 863 struct data_chunk *chunk) 864 { 865 struct at_xdmac_desc *desc; 866 u32 dwidth; 867 unsigned long flags; 868 size_t ublen; 869 /* 870 * WARNING: The channel configuration is set here since there is no 871 * dmaengine_slave_config call in this case. Moreover we don't know the 872 * direction, it involves we can't dynamically set the source and dest 873 * interface so we have to use the same one. Only interface 0 allows EBI 874 * access. Hopefully we can access DDR through both ports (at least on 875 * SAMA5D4x), so we can use the same interface for source and dest, 876 * that solves the fact we don't know the direction. 877 * ERRATA: Even if useless for memory transfers, the PERID has to not 878 * match the one of another channel. If not, it could lead to spurious 879 * flag status. 880 */ 881 u32 chan_cc = AT_XDMAC_CC_PERID(0x3f) 882 | AT_XDMAC_CC_DIF(0) 883 | AT_XDMAC_CC_SIF(0) 884 | AT_XDMAC_CC_MBSIZE_SIXTEEN 885 | AT_XDMAC_CC_TYPE_MEM_TRAN; 886 887 dwidth = at_xdmac_align_width(chan, src | dst | chunk->size); 888 if (chunk->size >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) { 889 dev_dbg(chan2dev(chan), 890 "%s: chunk too big (%zu, max size %lu)...\n", 891 __func__, chunk->size, 892 AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth); 893 return NULL; 894 } 895 896 if (prev) 897 dev_dbg(chan2dev(chan), 898 "Adding items at the end of desc 0x%p\n", prev); 899 900 if (xt->src_inc) { 901 if (xt->src_sgl) 902 chan_cc |= AT_XDMAC_CC_SAM_UBS_AM; 903 else 904 chan_cc |= AT_XDMAC_CC_SAM_INCREMENTED_AM; 905 } 906 907 if (xt->dst_inc) { 908 if (xt->dst_sgl) 909 chan_cc |= AT_XDMAC_CC_DAM_UBS_AM; 910 else 911 chan_cc |= AT_XDMAC_CC_DAM_INCREMENTED_AM; 912 } 913 914 spin_lock_irqsave(&atchan->lock, flags); 915 desc = at_xdmac_get_desc(atchan); 916 spin_unlock_irqrestore(&atchan->lock, flags); 917 if (!desc) { 918 dev_err(chan2dev(chan), "can't get descriptor\n"); 919 return NULL; 920 } 921 922 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth); 923 924 ublen = chunk->size >> dwidth; 925 926 desc->lld.mbr_sa = src; 927 desc->lld.mbr_da = dst; 928 desc->lld.mbr_sus = dmaengine_get_src_icg(xt, chunk); 929 desc->lld.mbr_dus = dmaengine_get_dst_icg(xt, chunk); 930 931 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3 932 | AT_XDMAC_MBR_UBC_NDEN 933 | AT_XDMAC_MBR_UBC_NSEN 934 | ublen; 935 desc->lld.mbr_cfg = chan_cc; 936 937 dev_dbg(chan2dev(chan), 938 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n", 939 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, 940 desc->lld.mbr_ubc, desc->lld.mbr_cfg); 941 942 /* Chain lld. */ 943 if (prev) 944 at_xdmac_queue_desc(chan, prev, desc); 945 946 return desc; 947 } 948 949 static struct dma_async_tx_descriptor * 950 at_xdmac_prep_interleaved(struct dma_chan *chan, 951 struct dma_interleaved_template *xt, 952 unsigned long flags) 953 { 954 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 955 struct at_xdmac_desc *prev = NULL, *first = NULL; 956 dma_addr_t dst_addr, src_addr; 957 size_t src_skip = 0, dst_skip = 0, len = 0; 958 struct data_chunk *chunk; 959 int i; 960 961 if (!xt || !xt->numf || (xt->dir != DMA_MEM_TO_MEM)) 962 return NULL; 963 964 /* 965 * TODO: Handle the case where we have to repeat a chain of 966 * descriptors... 967 */ 968 if ((xt->numf > 1) && (xt->frame_size > 1)) 969 return NULL; 970 971 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, numf=%zu, frame_size=%zu, flags=0x%lx\n", 972 __func__, &xt->src_start, &xt->dst_start, xt->numf, 973 xt->frame_size, flags); 974 975 src_addr = xt->src_start; 976 dst_addr = xt->dst_start; 977 978 if (xt->numf > 1) { 979 first = at_xdmac_interleaved_queue_desc(chan, atchan, 980 NULL, 981 src_addr, dst_addr, 982 xt, xt->sgl); 983 984 /* Length of the block is (BLEN+1) microblocks. */ 985 for (i = 0; i < xt->numf - 1; i++) 986 at_xdmac_increment_block_count(chan, first); 987 988 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", 989 __func__, first, first); 990 list_add_tail(&first->desc_node, &first->descs_list); 991 } else { 992 for (i = 0; i < xt->frame_size; i++) { 993 size_t src_icg = 0, dst_icg = 0; 994 struct at_xdmac_desc *desc; 995 996 chunk = xt->sgl + i; 997 998 dst_icg = dmaengine_get_dst_icg(xt, chunk); 999 src_icg = dmaengine_get_src_icg(xt, chunk); 1000 1001 src_skip = chunk->size + src_icg; 1002 dst_skip = chunk->size + dst_icg; 1003 1004 dev_dbg(chan2dev(chan), 1005 "%s: chunk size=%zu, src icg=%zu, dst icg=%zu\n", 1006 __func__, chunk->size, src_icg, dst_icg); 1007 1008 desc = at_xdmac_interleaved_queue_desc(chan, atchan, 1009 prev, 1010 src_addr, dst_addr, 1011 xt, chunk); 1012 if (!desc) { 1013 list_splice_init(&first->descs_list, 1014 &atchan->free_descs_list); 1015 return NULL; 1016 } 1017 1018 if (!first) 1019 first = desc; 1020 1021 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", 1022 __func__, desc, first); 1023 list_add_tail(&desc->desc_node, &first->descs_list); 1024 1025 if (xt->src_sgl) 1026 src_addr += src_skip; 1027 1028 if (xt->dst_sgl) 1029 dst_addr += dst_skip; 1030 1031 len += chunk->size; 1032 prev = desc; 1033 } 1034 } 1035 1036 first->tx_dma_desc.cookie = -EBUSY; 1037 first->tx_dma_desc.flags = flags; 1038 first->xfer_size = len; 1039 1040 return &first->tx_dma_desc; 1041 } 1042 1043 static struct dma_async_tx_descriptor * 1044 at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 1045 size_t len, unsigned long flags) 1046 { 1047 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 1048 struct at_xdmac_desc *first = NULL, *prev = NULL; 1049 size_t remaining_size = len, xfer_size = 0, ublen; 1050 dma_addr_t src_addr = src, dst_addr = dest; 1051 u32 dwidth; 1052 /* 1053 * WARNING: We don't know the direction, it involves we can't 1054 * dynamically set the source and dest interface so we have to use the 1055 * same one. Only interface 0 allows EBI access. Hopefully we can 1056 * access DDR through both ports (at least on SAMA5D4x), so we can use 1057 * the same interface for source and dest, that solves the fact we 1058 * don't know the direction. 1059 * ERRATA: Even if useless for memory transfers, the PERID has to not 1060 * match the one of another channel. If not, it could lead to spurious 1061 * flag status. 1062 */ 1063 u32 chan_cc = AT_XDMAC_CC_PERID(0x3f) 1064 | AT_XDMAC_CC_DAM_INCREMENTED_AM 1065 | AT_XDMAC_CC_SAM_INCREMENTED_AM 1066 | AT_XDMAC_CC_DIF(0) 1067 | AT_XDMAC_CC_SIF(0) 1068 | AT_XDMAC_CC_MBSIZE_SIXTEEN 1069 | AT_XDMAC_CC_TYPE_MEM_TRAN; 1070 unsigned long irqflags; 1071 1072 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n", 1073 __func__, &src, &dest, len, flags); 1074 1075 if (unlikely(!len)) 1076 return NULL; 1077 1078 dwidth = at_xdmac_align_width(chan, src_addr | dst_addr); 1079 1080 /* Prepare descriptors. */ 1081 while (remaining_size) { 1082 struct at_xdmac_desc *desc = NULL; 1083 1084 dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size); 1085 1086 spin_lock_irqsave(&atchan->lock, irqflags); 1087 desc = at_xdmac_get_desc(atchan); 1088 spin_unlock_irqrestore(&atchan->lock, irqflags); 1089 if (!desc) { 1090 dev_err(chan2dev(chan), "can't get descriptor\n"); 1091 if (first) 1092 list_splice_init(&first->descs_list, &atchan->free_descs_list); 1093 return NULL; 1094 } 1095 1096 /* Update src and dest addresses. */ 1097 src_addr += xfer_size; 1098 dst_addr += xfer_size; 1099 1100 if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth) 1101 xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth; 1102 else 1103 xfer_size = remaining_size; 1104 1105 dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size); 1106 1107 /* Check remaining length and change data width if needed. */ 1108 dwidth = at_xdmac_align_width(chan, 1109 src_addr | dst_addr | xfer_size); 1110 chan_cc &= ~AT_XDMAC_CC_DWIDTH_MASK; 1111 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth); 1112 1113 ublen = xfer_size >> dwidth; 1114 remaining_size -= xfer_size; 1115 1116 desc->lld.mbr_sa = src_addr; 1117 desc->lld.mbr_da = dst_addr; 1118 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 1119 | AT_XDMAC_MBR_UBC_NDEN 1120 | AT_XDMAC_MBR_UBC_NSEN 1121 | ublen; 1122 desc->lld.mbr_cfg = chan_cc; 1123 1124 dev_dbg(chan2dev(chan), 1125 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n", 1126 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg); 1127 1128 /* Chain lld. */ 1129 if (prev) 1130 at_xdmac_queue_desc(chan, prev, desc); 1131 1132 prev = desc; 1133 if (!first) 1134 first = desc; 1135 1136 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", 1137 __func__, desc, first); 1138 list_add_tail(&desc->desc_node, &first->descs_list); 1139 } 1140 1141 first->tx_dma_desc.flags = flags; 1142 first->xfer_size = len; 1143 1144 return &first->tx_dma_desc; 1145 } 1146 1147 static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan, 1148 struct at_xdmac_chan *atchan, 1149 dma_addr_t dst_addr, 1150 size_t len, 1151 int value) 1152 { 1153 struct at_xdmac_desc *desc; 1154 unsigned long flags; 1155 size_t ublen; 1156 u32 dwidth; 1157 /* 1158 * WARNING: The channel configuration is set here since there is no 1159 * dmaengine_slave_config call in this case. Moreover we don't know the 1160 * direction, it involves we can't dynamically set the source and dest 1161 * interface so we have to use the same one. Only interface 0 allows EBI 1162 * access. Hopefully we can access DDR through both ports (at least on 1163 * SAMA5D4x), so we can use the same interface for source and dest, 1164 * that solves the fact we don't know the direction. 1165 * ERRATA: Even if useless for memory transfers, the PERID has to not 1166 * match the one of another channel. If not, it could lead to spurious 1167 * flag status. 1168 */ 1169 u32 chan_cc = AT_XDMAC_CC_PERID(0x3f) 1170 | AT_XDMAC_CC_DAM_UBS_AM 1171 | AT_XDMAC_CC_SAM_INCREMENTED_AM 1172 | AT_XDMAC_CC_DIF(0) 1173 | AT_XDMAC_CC_SIF(0) 1174 | AT_XDMAC_CC_MBSIZE_SIXTEEN 1175 | AT_XDMAC_CC_MEMSET_HW_MODE 1176 | AT_XDMAC_CC_TYPE_MEM_TRAN; 1177 1178 dwidth = at_xdmac_align_width(chan, dst_addr); 1179 1180 if (len >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) { 1181 dev_err(chan2dev(chan), 1182 "%s: Transfer too large, aborting...\n", 1183 __func__); 1184 return NULL; 1185 } 1186 1187 spin_lock_irqsave(&atchan->lock, flags); 1188 desc = at_xdmac_get_desc(atchan); 1189 spin_unlock_irqrestore(&atchan->lock, flags); 1190 if (!desc) { 1191 dev_err(chan2dev(chan), "can't get descriptor\n"); 1192 return NULL; 1193 } 1194 1195 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth); 1196 1197 ublen = len >> dwidth; 1198 1199 desc->lld.mbr_da = dst_addr; 1200 desc->lld.mbr_ds = value; 1201 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3 1202 | AT_XDMAC_MBR_UBC_NDEN 1203 | AT_XDMAC_MBR_UBC_NSEN 1204 | ublen; 1205 desc->lld.mbr_cfg = chan_cc; 1206 1207 dev_dbg(chan2dev(chan), 1208 "%s: lld: mbr_da=%pad, mbr_ds=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n", 1209 __func__, &desc->lld.mbr_da, desc->lld.mbr_ds, desc->lld.mbr_ubc, 1210 desc->lld.mbr_cfg); 1211 1212 return desc; 1213 } 1214 1215 static struct dma_async_tx_descriptor * 1216 at_xdmac_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value, 1217 size_t len, unsigned long flags) 1218 { 1219 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 1220 struct at_xdmac_desc *desc; 1221 1222 dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%zu, pattern=0x%x, flags=0x%lx\n", 1223 __func__, &dest, len, value, flags); 1224 1225 if (unlikely(!len)) 1226 return NULL; 1227 1228 desc = at_xdmac_memset_create_desc(chan, atchan, dest, len, value); 1229 list_add_tail(&desc->desc_node, &desc->descs_list); 1230 1231 desc->tx_dma_desc.cookie = -EBUSY; 1232 desc->tx_dma_desc.flags = flags; 1233 desc->xfer_size = len; 1234 1235 return &desc->tx_dma_desc; 1236 } 1237 1238 static struct dma_async_tx_descriptor * 1239 at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct scatterlist *sgl, 1240 unsigned int sg_len, int value, 1241 unsigned long flags) 1242 { 1243 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 1244 struct at_xdmac_desc *desc, *pdesc = NULL, 1245 *ppdesc = NULL, *first = NULL; 1246 struct scatterlist *sg, *psg = NULL, *ppsg = NULL; 1247 size_t stride = 0, pstride = 0, len = 0; 1248 int i; 1249 1250 if (!sgl) 1251 return NULL; 1252 1253 dev_dbg(chan2dev(chan), "%s: sg_len=%d, value=0x%x, flags=0x%lx\n", 1254 __func__, sg_len, value, flags); 1255 1256 /* Prepare descriptors. */ 1257 for_each_sg(sgl, sg, sg_len, i) { 1258 dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%d, pattern=0x%x, flags=0x%lx\n", 1259 __func__, &sg_dma_address(sg), sg_dma_len(sg), 1260 value, flags); 1261 desc = at_xdmac_memset_create_desc(chan, atchan, 1262 sg_dma_address(sg), 1263 sg_dma_len(sg), 1264 value); 1265 if (!desc && first) 1266 list_splice_init(&first->descs_list, 1267 &atchan->free_descs_list); 1268 1269 if (!first) 1270 first = desc; 1271 1272 /* Update our strides */ 1273 pstride = stride; 1274 if (psg) 1275 stride = sg_dma_address(sg) - 1276 (sg_dma_address(psg) + sg_dma_len(psg)); 1277 1278 /* 1279 * The scatterlist API gives us only the address and 1280 * length of each elements. 1281 * 1282 * Unfortunately, we don't have the stride, which we 1283 * will need to compute. 1284 * 1285 * That make us end up in a situation like this one: 1286 * len stride len stride len 1287 * +-------+ +-------+ +-------+ 1288 * | N-2 | | N-1 | | N | 1289 * +-------+ +-------+ +-------+ 1290 * 1291 * We need all these three elements (N-2, N-1 and N) 1292 * to actually take the decision on whether we need to 1293 * queue N-1 or reuse N-2. 1294 * 1295 * We will only consider N if it is the last element. 1296 */ 1297 if (ppdesc && pdesc) { 1298 if ((stride == pstride) && 1299 (sg_dma_len(ppsg) == sg_dma_len(psg))) { 1300 dev_dbg(chan2dev(chan), 1301 "%s: desc 0x%p can be merged with desc 0x%p\n", 1302 __func__, pdesc, ppdesc); 1303 1304 /* 1305 * Increment the block count of the 1306 * N-2 descriptor 1307 */ 1308 at_xdmac_increment_block_count(chan, ppdesc); 1309 ppdesc->lld.mbr_dus = stride; 1310 1311 /* 1312 * Put back the N-1 descriptor in the 1313 * free descriptor list 1314 */ 1315 list_add_tail(&pdesc->desc_node, 1316 &atchan->free_descs_list); 1317 1318 /* 1319 * Make our N-1 descriptor pointer 1320 * point to the N-2 since they were 1321 * actually merged. 1322 */ 1323 pdesc = ppdesc; 1324 1325 /* 1326 * Rule out the case where we don't have 1327 * pstride computed yet (our second sg 1328 * element) 1329 * 1330 * We also want to catch the case where there 1331 * would be a negative stride, 1332 */ 1333 } else if (pstride || 1334 sg_dma_address(sg) < sg_dma_address(psg)) { 1335 /* 1336 * Queue the N-1 descriptor after the 1337 * N-2 1338 */ 1339 at_xdmac_queue_desc(chan, ppdesc, pdesc); 1340 1341 /* 1342 * Add the N-1 descriptor to the list 1343 * of the descriptors used for this 1344 * transfer 1345 */ 1346 list_add_tail(&desc->desc_node, 1347 &first->descs_list); 1348 dev_dbg(chan2dev(chan), 1349 "%s: add desc 0x%p to descs_list 0x%p\n", 1350 __func__, desc, first); 1351 } 1352 } 1353 1354 /* 1355 * If we are the last element, just see if we have the 1356 * same size than the previous element. 1357 * 1358 * If so, we can merge it with the previous descriptor 1359 * since we don't care about the stride anymore. 1360 */ 1361 if ((i == (sg_len - 1)) && 1362 sg_dma_len(psg) == sg_dma_len(sg)) { 1363 dev_dbg(chan2dev(chan), 1364 "%s: desc 0x%p can be merged with desc 0x%p\n", 1365 __func__, desc, pdesc); 1366 1367 /* 1368 * Increment the block count of the N-1 1369 * descriptor 1370 */ 1371 at_xdmac_increment_block_count(chan, pdesc); 1372 pdesc->lld.mbr_dus = stride; 1373 1374 /* 1375 * Put back the N descriptor in the free 1376 * descriptor list 1377 */ 1378 list_add_tail(&desc->desc_node, 1379 &atchan->free_descs_list); 1380 } 1381 1382 /* Update our descriptors */ 1383 ppdesc = pdesc; 1384 pdesc = desc; 1385 1386 /* Update our scatter pointers */ 1387 ppsg = psg; 1388 psg = sg; 1389 1390 len += sg_dma_len(sg); 1391 } 1392 1393 first->tx_dma_desc.cookie = -EBUSY; 1394 first->tx_dma_desc.flags = flags; 1395 first->xfer_size = len; 1396 1397 return &first->tx_dma_desc; 1398 } 1399 1400 static enum dma_status 1401 at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 1402 struct dma_tx_state *txstate) 1403 { 1404 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 1405 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); 1406 struct at_xdmac_desc *desc, *_desc; 1407 struct list_head *descs_list; 1408 enum dma_status ret; 1409 int residue, retry; 1410 u32 cur_nda, check_nda, cur_ubc, mask, value; 1411 u8 dwidth = 0; 1412 unsigned long flags; 1413 bool initd; 1414 1415 ret = dma_cookie_status(chan, cookie, txstate); 1416 if (ret == DMA_COMPLETE) 1417 return ret; 1418 1419 if (!txstate) 1420 return ret; 1421 1422 spin_lock_irqsave(&atchan->lock, flags); 1423 1424 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node); 1425 1426 /* 1427 * If the transfer has not been started yet, don't need to compute the 1428 * residue, it's the transfer length. 1429 */ 1430 if (!desc->active_xfer) { 1431 dma_set_residue(txstate, desc->xfer_size); 1432 goto spin_unlock; 1433 } 1434 1435 residue = desc->xfer_size; 1436 /* 1437 * Flush FIFO: only relevant when the transfer is source peripheral 1438 * synchronized. Flush is needed before reading CUBC because data in 1439 * the FIFO are not reported by CUBC. Reporting a residue of the 1440 * transfer length while we have data in FIFO can cause issue. 1441 * Usecase: atmel USART has a timeout which means I have received 1442 * characters but there is no more character received for a while. On 1443 * timeout, it requests the residue. If the data are in the DMA FIFO, 1444 * we will return a residue of the transfer length. It means no data 1445 * received. If an application is waiting for these data, it will hang 1446 * since we won't have another USART timeout without receiving new 1447 * data. 1448 */ 1449 mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC; 1450 value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM; 1451 if ((desc->lld.mbr_cfg & mask) == value) { 1452 at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask); 1453 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS)) 1454 cpu_relax(); 1455 } 1456 1457 /* 1458 * The easiest way to compute the residue should be to pause the DMA 1459 * but doing this can lead to miss some data as some devices don't 1460 * have FIFO. 1461 * We need to read several registers because: 1462 * - DMA is running therefore a descriptor change is possible while 1463 * reading these registers 1464 * - When the block transfer is done, the value of the CUBC register 1465 * is set to its initial value until the fetch of the next descriptor. 1466 * This value will corrupt the residue calculation so we have to skip 1467 * it. 1468 * 1469 * INITD -------- ------------ 1470 * |____________________| 1471 * _______________________ _______________ 1472 * NDA @desc2 \/ @desc3 1473 * _______________________/\_______________ 1474 * __________ ___________ _______________ 1475 * CUBC 0 \/ MAX desc1 \/ MAX desc2 1476 * __________/\___________/\_______________ 1477 * 1478 * Since descriptors are aligned on 64 bits, we can assume that 1479 * the update of NDA and CUBC is atomic. 1480 * Memory barriers are used to ensure the read order of the registers. 1481 * A max number of retries is set because unlikely it could never ends. 1482 */ 1483 for (retry = 0; retry < AT_XDMAC_RESIDUE_MAX_RETRIES; retry++) { 1484 check_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc; 1485 rmb(); 1486 cur_ubc = at_xdmac_chan_read(atchan, AT_XDMAC_CUBC); 1487 rmb(); 1488 initd = !!(at_xdmac_chan_read(atchan, AT_XDMAC_CC) & AT_XDMAC_CC_INITD); 1489 rmb(); 1490 cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc; 1491 rmb(); 1492 1493 if ((check_nda == cur_nda) && initd) 1494 break; 1495 } 1496 1497 if (unlikely(retry >= AT_XDMAC_RESIDUE_MAX_RETRIES)) { 1498 ret = DMA_ERROR; 1499 goto spin_unlock; 1500 } 1501 1502 /* 1503 * Flush FIFO: only relevant when the transfer is source peripheral 1504 * synchronized. Another flush is needed here because CUBC is updated 1505 * when the controller sends the data write command. It can lead to 1506 * report data that are not written in the memory or the device. The 1507 * FIFO flush ensures that data are really written. 1508 */ 1509 if ((desc->lld.mbr_cfg & mask) == value) { 1510 at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask); 1511 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS)) 1512 cpu_relax(); 1513 } 1514 1515 /* 1516 * Remove size of all microblocks already transferred and the current 1517 * one. Then add the remaining size to transfer of the current 1518 * microblock. 1519 */ 1520 descs_list = &desc->descs_list; 1521 list_for_each_entry_safe(desc, _desc, descs_list, desc_node) { 1522 dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg); 1523 residue -= (desc->lld.mbr_ubc & 0xffffff) << dwidth; 1524 if ((desc->lld.mbr_nda & 0xfffffffc) == cur_nda) 1525 break; 1526 } 1527 residue += cur_ubc << dwidth; 1528 1529 dma_set_residue(txstate, residue); 1530 1531 dev_dbg(chan2dev(chan), 1532 "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n", 1533 __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue); 1534 1535 spin_unlock: 1536 spin_unlock_irqrestore(&atchan->lock, flags); 1537 return ret; 1538 } 1539 1540 /* Call must be protected by lock. */ 1541 static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan, 1542 struct at_xdmac_desc *desc) 1543 { 1544 dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); 1545 1546 /* 1547 * Remove the transfer from the transfer list then move the transfer 1548 * descriptors into the free descriptors list. 1549 */ 1550 list_del(&desc->xfer_node); 1551 list_splice_init(&desc->descs_list, &atchan->free_descs_list); 1552 } 1553 1554 static void at_xdmac_advance_work(struct at_xdmac_chan *atchan) 1555 { 1556 struct at_xdmac_desc *desc; 1557 unsigned long flags; 1558 1559 spin_lock_irqsave(&atchan->lock, flags); 1560 1561 /* 1562 * If channel is enabled, do nothing, advance_work will be triggered 1563 * after the interruption. 1564 */ 1565 if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) { 1566 desc = list_first_entry(&atchan->xfers_list, 1567 struct at_xdmac_desc, 1568 xfer_node); 1569 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); 1570 if (!desc->active_xfer) 1571 at_xdmac_start_xfer(atchan, desc); 1572 } 1573 1574 spin_unlock_irqrestore(&atchan->lock, flags); 1575 } 1576 1577 static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan) 1578 { 1579 struct at_xdmac_desc *desc; 1580 struct dma_async_tx_descriptor *txd; 1581 1582 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node); 1583 txd = &desc->tx_dma_desc; 1584 1585 if (txd->flags & DMA_PREP_INTERRUPT) 1586 dmaengine_desc_get_callback_invoke(txd, NULL); 1587 } 1588 1589 static void at_xdmac_handle_error(struct at_xdmac_chan *atchan) 1590 { 1591 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); 1592 struct at_xdmac_desc *bad_desc; 1593 1594 /* 1595 * The descriptor currently at the head of the active list is 1596 * broken. Since we don't have any way to report errors, we'll 1597 * just have to scream loudly and try to continue with other 1598 * descriptors queued (if any). 1599 */ 1600 if (atchan->irq_status & AT_XDMAC_CIS_RBEIS) 1601 dev_err(chan2dev(&atchan->chan), "read bus error!!!"); 1602 if (atchan->irq_status & AT_XDMAC_CIS_WBEIS) 1603 dev_err(chan2dev(&atchan->chan), "write bus error!!!"); 1604 if (atchan->irq_status & AT_XDMAC_CIS_ROIS) 1605 dev_err(chan2dev(&atchan->chan), "request overflow error!!!"); 1606 1607 spin_lock_bh(&atchan->lock); 1608 1609 /* Channel must be disabled first as it's not done automatically */ 1610 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); 1611 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask) 1612 cpu_relax(); 1613 1614 bad_desc = list_first_entry(&atchan->xfers_list, 1615 struct at_xdmac_desc, 1616 xfer_node); 1617 1618 spin_unlock_bh(&atchan->lock); 1619 1620 /* Print bad descriptor's details if needed */ 1621 dev_dbg(chan2dev(&atchan->chan), 1622 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", 1623 __func__, &bad_desc->lld.mbr_sa, &bad_desc->lld.mbr_da, 1624 bad_desc->lld.mbr_ubc); 1625 1626 /* Then continue with usual descriptor management */ 1627 } 1628 1629 static void at_xdmac_tasklet(unsigned long data) 1630 { 1631 struct at_xdmac_chan *atchan = (struct at_xdmac_chan *)data; 1632 struct at_xdmac_desc *desc; 1633 u32 error_mask; 1634 1635 dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08x\n", 1636 __func__, atchan->irq_status); 1637 1638 error_mask = AT_XDMAC_CIS_RBEIS 1639 | AT_XDMAC_CIS_WBEIS 1640 | AT_XDMAC_CIS_ROIS; 1641 1642 if (at_xdmac_chan_is_cyclic(atchan)) { 1643 at_xdmac_handle_cyclic(atchan); 1644 } else if ((atchan->irq_status & AT_XDMAC_CIS_LIS) 1645 || (atchan->irq_status & error_mask)) { 1646 struct dma_async_tx_descriptor *txd; 1647 1648 if (atchan->irq_status & error_mask) 1649 at_xdmac_handle_error(atchan); 1650 1651 spin_lock(&atchan->lock); 1652 desc = list_first_entry(&atchan->xfers_list, 1653 struct at_xdmac_desc, 1654 xfer_node); 1655 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); 1656 if (!desc->active_xfer) { 1657 dev_err(chan2dev(&atchan->chan), "Xfer not active: exiting"); 1658 spin_unlock(&atchan->lock); 1659 return; 1660 } 1661 1662 txd = &desc->tx_dma_desc; 1663 1664 at_xdmac_remove_xfer(atchan, desc); 1665 spin_unlock(&atchan->lock); 1666 1667 if (!at_xdmac_chan_is_cyclic(atchan)) { 1668 dma_cookie_complete(txd); 1669 if (txd->flags & DMA_PREP_INTERRUPT) 1670 dmaengine_desc_get_callback_invoke(txd, NULL); 1671 } 1672 1673 dma_run_dependencies(txd); 1674 1675 at_xdmac_advance_work(atchan); 1676 } 1677 } 1678 1679 static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id) 1680 { 1681 struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id; 1682 struct at_xdmac_chan *atchan; 1683 u32 imr, status, pending; 1684 u32 chan_imr, chan_status; 1685 int i, ret = IRQ_NONE; 1686 1687 do { 1688 imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM); 1689 status = at_xdmac_read(atxdmac, AT_XDMAC_GIS); 1690 pending = status & imr; 1691 1692 dev_vdbg(atxdmac->dma.dev, 1693 "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n", 1694 __func__, status, imr, pending); 1695 1696 if (!pending) 1697 break; 1698 1699 /* We have to find which channel has generated the interrupt. */ 1700 for (i = 0; i < atxdmac->dma.chancnt; i++) { 1701 if (!((1 << i) & pending)) 1702 continue; 1703 1704 atchan = &atxdmac->chan[i]; 1705 chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM); 1706 chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS); 1707 atchan->irq_status = chan_status & chan_imr; 1708 dev_vdbg(atxdmac->dma.dev, 1709 "%s: chan%d: imr=0x%x, status=0x%x\n", 1710 __func__, i, chan_imr, chan_status); 1711 dev_vdbg(chan2dev(&atchan->chan), 1712 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", 1713 __func__, 1714 at_xdmac_chan_read(atchan, AT_XDMAC_CC), 1715 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), 1716 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC), 1717 at_xdmac_chan_read(atchan, AT_XDMAC_CSA), 1718 at_xdmac_chan_read(atchan, AT_XDMAC_CDA), 1719 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC)); 1720 1721 if (atchan->irq_status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS)) 1722 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); 1723 1724 tasklet_schedule(&atchan->tasklet); 1725 ret = IRQ_HANDLED; 1726 } 1727 1728 } while (pending); 1729 1730 return ret; 1731 } 1732 1733 static void at_xdmac_issue_pending(struct dma_chan *chan) 1734 { 1735 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 1736 1737 dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__); 1738 1739 if (!at_xdmac_chan_is_cyclic(atchan)) 1740 at_xdmac_advance_work(atchan); 1741 1742 return; 1743 } 1744 1745 static int at_xdmac_device_config(struct dma_chan *chan, 1746 struct dma_slave_config *config) 1747 { 1748 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 1749 int ret; 1750 unsigned long flags; 1751 1752 dev_dbg(chan2dev(chan), "%s\n", __func__); 1753 1754 spin_lock_irqsave(&atchan->lock, flags); 1755 ret = at_xdmac_set_slave_config(chan, config); 1756 spin_unlock_irqrestore(&atchan->lock, flags); 1757 1758 return ret; 1759 } 1760 1761 static int at_xdmac_device_pause(struct dma_chan *chan) 1762 { 1763 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 1764 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); 1765 unsigned long flags; 1766 1767 dev_dbg(chan2dev(chan), "%s\n", __func__); 1768 1769 if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status)) 1770 return 0; 1771 1772 spin_lock_irqsave(&atchan->lock, flags); 1773 at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask); 1774 while (at_xdmac_chan_read(atchan, AT_XDMAC_CC) 1775 & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP)) 1776 cpu_relax(); 1777 spin_unlock_irqrestore(&atchan->lock, flags); 1778 1779 return 0; 1780 } 1781 1782 static int at_xdmac_device_resume(struct dma_chan *chan) 1783 { 1784 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 1785 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); 1786 unsigned long flags; 1787 1788 dev_dbg(chan2dev(chan), "%s\n", __func__); 1789 1790 spin_lock_irqsave(&atchan->lock, flags); 1791 if (!at_xdmac_chan_is_paused(atchan)) { 1792 spin_unlock_irqrestore(&atchan->lock, flags); 1793 return 0; 1794 } 1795 1796 at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask); 1797 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); 1798 spin_unlock_irqrestore(&atchan->lock, flags); 1799 1800 return 0; 1801 } 1802 1803 static int at_xdmac_device_terminate_all(struct dma_chan *chan) 1804 { 1805 struct at_xdmac_desc *desc, *_desc; 1806 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 1807 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); 1808 unsigned long flags; 1809 1810 dev_dbg(chan2dev(chan), "%s\n", __func__); 1811 1812 spin_lock_irqsave(&atchan->lock, flags); 1813 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); 1814 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask) 1815 cpu_relax(); 1816 1817 /* Cancel all pending transfers. */ 1818 list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node) 1819 at_xdmac_remove_xfer(atchan, desc); 1820 1821 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); 1822 clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status); 1823 spin_unlock_irqrestore(&atchan->lock, flags); 1824 1825 return 0; 1826 } 1827 1828 static int at_xdmac_alloc_chan_resources(struct dma_chan *chan) 1829 { 1830 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 1831 struct at_xdmac_desc *desc; 1832 int i; 1833 unsigned long flags; 1834 1835 spin_lock_irqsave(&atchan->lock, flags); 1836 1837 if (at_xdmac_chan_is_enabled(atchan)) { 1838 dev_err(chan2dev(chan), 1839 "can't allocate channel resources (channel enabled)\n"); 1840 i = -EIO; 1841 goto spin_unlock; 1842 } 1843 1844 if (!list_empty(&atchan->free_descs_list)) { 1845 dev_err(chan2dev(chan), 1846 "can't allocate channel resources (channel not free from a previous use)\n"); 1847 i = -EIO; 1848 goto spin_unlock; 1849 } 1850 1851 for (i = 0; i < init_nr_desc_per_channel; i++) { 1852 desc = at_xdmac_alloc_desc(chan, GFP_ATOMIC); 1853 if (!desc) { 1854 dev_warn(chan2dev(chan), 1855 "only %d descriptors have been allocated\n", i); 1856 break; 1857 } 1858 list_add_tail(&desc->desc_node, &atchan->free_descs_list); 1859 } 1860 1861 dma_cookie_init(chan); 1862 1863 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); 1864 1865 spin_unlock: 1866 spin_unlock_irqrestore(&atchan->lock, flags); 1867 return i; 1868 } 1869 1870 static void at_xdmac_free_chan_resources(struct dma_chan *chan) 1871 { 1872 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 1873 struct at_xdmac *atxdmac = to_at_xdmac(chan->device); 1874 struct at_xdmac_desc *desc, *_desc; 1875 1876 list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) { 1877 dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc); 1878 list_del(&desc->desc_node); 1879 dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys); 1880 } 1881 1882 return; 1883 } 1884 1885 #ifdef CONFIG_PM 1886 static int atmel_xdmac_prepare(struct device *dev) 1887 { 1888 struct at_xdmac *atxdmac = dev_get_drvdata(dev); 1889 struct dma_chan *chan, *_chan; 1890 1891 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) { 1892 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 1893 1894 /* Wait for transfer completion, except in cyclic case. */ 1895 if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan)) 1896 return -EAGAIN; 1897 } 1898 return 0; 1899 } 1900 #else 1901 # define atmel_xdmac_prepare NULL 1902 #endif 1903 1904 #ifdef CONFIG_PM_SLEEP 1905 static int atmel_xdmac_suspend(struct device *dev) 1906 { 1907 struct at_xdmac *atxdmac = dev_get_drvdata(dev); 1908 struct dma_chan *chan, *_chan; 1909 1910 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) { 1911 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); 1912 1913 atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC); 1914 if (at_xdmac_chan_is_cyclic(atchan)) { 1915 if (!at_xdmac_chan_is_paused(atchan)) 1916 at_xdmac_device_pause(chan); 1917 atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM); 1918 atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA); 1919 atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC); 1920 } 1921 } 1922 atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM); 1923 1924 at_xdmac_off(atxdmac); 1925 clk_disable_unprepare(atxdmac->clk); 1926 return 0; 1927 } 1928 1929 static int atmel_xdmac_resume(struct device *dev) 1930 { 1931 struct at_xdmac *atxdmac = dev_get_drvdata(dev); 1932 struct at_xdmac_chan *atchan; 1933 struct dma_chan *chan, *_chan; 1934 int i; 1935 int ret; 1936 1937 ret = clk_prepare_enable(atxdmac->clk); 1938 if (ret) 1939 return ret; 1940 1941 /* Clear pending interrupts. */ 1942 for (i = 0; i < atxdmac->dma.chancnt; i++) { 1943 atchan = &atxdmac->chan[i]; 1944 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS)) 1945 cpu_relax(); 1946 } 1947 1948 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim); 1949 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) { 1950 atchan = to_at_xdmac_chan(chan); 1951 at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc); 1952 if (at_xdmac_chan_is_cyclic(atchan)) { 1953 if (at_xdmac_chan_is_paused(atchan)) 1954 at_xdmac_device_resume(chan); 1955 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda); 1956 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc); 1957 at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim); 1958 wmb(); 1959 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); 1960 } 1961 } 1962 return 0; 1963 } 1964 #endif /* CONFIG_PM_SLEEP */ 1965 1966 static int at_xdmac_probe(struct platform_device *pdev) 1967 { 1968 struct resource *res; 1969 struct at_xdmac *atxdmac; 1970 int irq, size, nr_channels, i, ret; 1971 void __iomem *base; 1972 u32 reg; 1973 1974 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1975 if (!res) 1976 return -EINVAL; 1977 1978 irq = platform_get_irq(pdev, 0); 1979 if (irq < 0) 1980 return irq; 1981 1982 base = devm_ioremap_resource(&pdev->dev, res); 1983 if (IS_ERR(base)) 1984 return PTR_ERR(base); 1985 1986 /* 1987 * Read number of xdmac channels, read helper function can't be used 1988 * since atxdmac is not yet allocated and we need to know the number 1989 * of channels to do the allocation. 1990 */ 1991 reg = readl_relaxed(base + AT_XDMAC_GTYPE); 1992 nr_channels = AT_XDMAC_NB_CH(reg); 1993 if (nr_channels > AT_XDMAC_MAX_CHAN) { 1994 dev_err(&pdev->dev, "invalid number of channels (%u)\n", 1995 nr_channels); 1996 return -EINVAL; 1997 } 1998 1999 size = sizeof(*atxdmac); 2000 size += nr_channels * sizeof(struct at_xdmac_chan); 2001 atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); 2002 if (!atxdmac) { 2003 dev_err(&pdev->dev, "can't allocate at_xdmac structure\n"); 2004 return -ENOMEM; 2005 } 2006 2007 atxdmac->regs = base; 2008 atxdmac->irq = irq; 2009 2010 atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk"); 2011 if (IS_ERR(atxdmac->clk)) { 2012 dev_err(&pdev->dev, "can't get dma_clk\n"); 2013 return PTR_ERR(atxdmac->clk); 2014 } 2015 2016 /* Do not use dev res to prevent races with tasklet */ 2017 ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac); 2018 if (ret) { 2019 dev_err(&pdev->dev, "can't request irq\n"); 2020 return ret; 2021 } 2022 2023 ret = clk_prepare_enable(atxdmac->clk); 2024 if (ret) { 2025 dev_err(&pdev->dev, "can't prepare or enable clock\n"); 2026 goto err_free_irq; 2027 } 2028 2029 atxdmac->at_xdmac_desc_pool = 2030 dmam_pool_create(dev_name(&pdev->dev), &pdev->dev, 2031 sizeof(struct at_xdmac_desc), 4, 0); 2032 if (!atxdmac->at_xdmac_desc_pool) { 2033 dev_err(&pdev->dev, "no memory for descriptors dma pool\n"); 2034 ret = -ENOMEM; 2035 goto err_clk_disable; 2036 } 2037 2038 dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask); 2039 dma_cap_set(DMA_INTERLEAVE, atxdmac->dma.cap_mask); 2040 dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask); 2041 dma_cap_set(DMA_MEMSET, atxdmac->dma.cap_mask); 2042 dma_cap_set(DMA_MEMSET_SG, atxdmac->dma.cap_mask); 2043 dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask); 2044 /* 2045 * Without DMA_PRIVATE the driver is not able to allocate more than 2046 * one channel, second allocation fails in private_candidate. 2047 */ 2048 dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask); 2049 atxdmac->dma.dev = &pdev->dev; 2050 atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources; 2051 atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources; 2052 atxdmac->dma.device_tx_status = at_xdmac_tx_status; 2053 atxdmac->dma.device_issue_pending = at_xdmac_issue_pending; 2054 atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic; 2055 atxdmac->dma.device_prep_interleaved_dma = at_xdmac_prep_interleaved; 2056 atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy; 2057 atxdmac->dma.device_prep_dma_memset = at_xdmac_prep_dma_memset; 2058 atxdmac->dma.device_prep_dma_memset_sg = at_xdmac_prep_dma_memset_sg; 2059 atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg; 2060 atxdmac->dma.device_config = at_xdmac_device_config; 2061 atxdmac->dma.device_pause = at_xdmac_device_pause; 2062 atxdmac->dma.device_resume = at_xdmac_device_resume; 2063 atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all; 2064 atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS; 2065 atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS; 2066 atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 2067 atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 2068 2069 /* Disable all chans and interrupts. */ 2070 at_xdmac_off(atxdmac); 2071 2072 /* Init channels. */ 2073 INIT_LIST_HEAD(&atxdmac->dma.channels); 2074 for (i = 0; i < nr_channels; i++) { 2075 struct at_xdmac_chan *atchan = &atxdmac->chan[i]; 2076 2077 atchan->chan.device = &atxdmac->dma; 2078 list_add_tail(&atchan->chan.device_node, 2079 &atxdmac->dma.channels); 2080 2081 atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i); 2082 atchan->mask = 1 << i; 2083 2084 spin_lock_init(&atchan->lock); 2085 INIT_LIST_HEAD(&atchan->xfers_list); 2086 INIT_LIST_HEAD(&atchan->free_descs_list); 2087 tasklet_init(&atchan->tasklet, at_xdmac_tasklet, 2088 (unsigned long)atchan); 2089 2090 /* Clear pending interrupts. */ 2091 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS)) 2092 cpu_relax(); 2093 } 2094 platform_set_drvdata(pdev, atxdmac); 2095 2096 ret = dma_async_device_register(&atxdmac->dma); 2097 if (ret) { 2098 dev_err(&pdev->dev, "fail to register DMA engine device\n"); 2099 goto err_clk_disable; 2100 } 2101 2102 ret = of_dma_controller_register(pdev->dev.of_node, 2103 at_xdmac_xlate, atxdmac); 2104 if (ret) { 2105 dev_err(&pdev->dev, "could not register of dma controller\n"); 2106 goto err_dma_unregister; 2107 } 2108 2109 dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n", 2110 nr_channels, atxdmac->regs); 2111 2112 return 0; 2113 2114 err_dma_unregister: 2115 dma_async_device_unregister(&atxdmac->dma); 2116 err_clk_disable: 2117 clk_disable_unprepare(atxdmac->clk); 2118 err_free_irq: 2119 free_irq(atxdmac->irq, atxdmac); 2120 return ret; 2121 } 2122 2123 static int at_xdmac_remove(struct platform_device *pdev) 2124 { 2125 struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev); 2126 int i; 2127 2128 at_xdmac_off(atxdmac); 2129 of_dma_controller_free(pdev->dev.of_node); 2130 dma_async_device_unregister(&atxdmac->dma); 2131 clk_disable_unprepare(atxdmac->clk); 2132 2133 free_irq(atxdmac->irq, atxdmac); 2134 2135 for (i = 0; i < atxdmac->dma.chancnt; i++) { 2136 struct at_xdmac_chan *atchan = &atxdmac->chan[i]; 2137 2138 tasklet_kill(&atchan->tasklet); 2139 at_xdmac_free_chan_resources(&atchan->chan); 2140 } 2141 2142 return 0; 2143 } 2144 2145 static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = { 2146 .prepare = atmel_xdmac_prepare, 2147 SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume) 2148 }; 2149 2150 static const struct of_device_id atmel_xdmac_dt_ids[] = { 2151 { 2152 .compatible = "atmel,sama5d4-dma", 2153 }, { 2154 /* sentinel */ 2155 } 2156 }; 2157 MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids); 2158 2159 static struct platform_driver at_xdmac_driver = { 2160 .probe = at_xdmac_probe, 2161 .remove = at_xdmac_remove, 2162 .driver = { 2163 .name = "at_xdmac", 2164 .of_match_table = of_match_ptr(atmel_xdmac_dt_ids), 2165 .pm = &atmel_xdmac_dev_pm_ops, 2166 } 2167 }; 2168 2169 static int __init at_xdmac_init(void) 2170 { 2171 return platform_driver_probe(&at_xdmac_driver, at_xdmac_probe); 2172 } 2173 subsys_initcall(at_xdmac_init); 2174 2175 MODULE_DESCRIPTION("Atmel Extended DMA Controller driver"); 2176 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 2177 MODULE_LICENSE("GPL"); 2178