1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2 /* Copyright(c) 2014 - 2020 Intel Corporation */ 3 #ifndef _ICP_QAT_FW_INIT_ADMIN_H_ 4 #define _ICP_QAT_FW_INIT_ADMIN_H_ 5 6 #include "icp_qat_fw.h" 7 8 #define RL_MAX_RP_IDS 16 9 10 enum icp_qat_fw_init_admin_cmd_id { 11 ICP_QAT_FW_INIT_AE = 0, 12 ICP_QAT_FW_TRNG_ENABLE = 1, 13 ICP_QAT_FW_TRNG_DISABLE = 2, 14 ICP_QAT_FW_CONSTANTS_CFG = 3, 15 ICP_QAT_FW_STATUS_GET = 4, 16 ICP_QAT_FW_COUNTERS_GET = 5, 17 ICP_QAT_FW_LOOPBACK = 6, 18 ICP_QAT_FW_HEARTBEAT_SYNC = 7, 19 ICP_QAT_FW_HEARTBEAT_GET = 8, 20 ICP_QAT_FW_COMP_CAPABILITY_GET = 9, 21 ICP_QAT_FW_CRYPTO_CAPABILITY_GET = 10, 22 ICP_QAT_FW_DC_CHAIN_INIT = 11, 23 ICP_QAT_FW_HEARTBEAT_TIMER_SET = 13, 24 ICP_QAT_FW_RL_INIT = 15, 25 ICP_QAT_FW_TIMER_GET = 19, 26 ICP_QAT_FW_CNV_STATS_GET = 20, 27 ICP_QAT_FW_PM_STATE_CONFIG = 128, 28 ICP_QAT_FW_PM_INFO = 129, 29 ICP_QAT_FW_RL_ADD = 134, 30 ICP_QAT_FW_RL_UPDATE = 135, 31 ICP_QAT_FW_RL_REMOVE = 136, 32 }; 33 34 enum icp_qat_fw_init_admin_resp_status { 35 ICP_QAT_FW_INIT_RESP_STATUS_SUCCESS = 0, 36 ICP_QAT_FW_INIT_RESP_STATUS_FAIL 37 }; 38 39 struct icp_qat_fw_init_admin_slice_cnt { 40 __u8 cpr_cnt; 41 __u8 xlt_cnt; 42 __u8 dcpr_cnt; 43 __u8 pke_cnt; 44 __u8 wat_cnt; 45 __u8 wcp_cnt; 46 __u8 ucs_cnt; 47 __u8 cph_cnt; 48 __u8 ath_cnt; 49 }; 50 51 struct icp_qat_fw_init_admin_sla_config_params { 52 __u32 pcie_in_cir; 53 __u32 pcie_in_pir; 54 __u32 pcie_out_cir; 55 __u32 pcie_out_pir; 56 __u32 slice_util_cir; 57 __u32 slice_util_pir; 58 __u32 ae_util_cir; 59 __u32 ae_util_pir; 60 __u16 rp_ids[RL_MAX_RP_IDS]; 61 }; 62 63 struct icp_qat_fw_init_admin_req { 64 __u16 init_cfg_sz; 65 __u8 resrvd1; 66 __u8 cmd_id; 67 __u32 resrvd2; 68 __u64 opaque_data; 69 __u64 init_cfg_ptr; 70 71 union { 72 struct { 73 __u16 ibuf_size_in_kb; 74 __u16 resrvd3; 75 }; 76 struct { 77 __u32 int_timer_ticks; 78 }; 79 struct { 80 __u32 heartbeat_ticks; 81 }; 82 struct { 83 __u16 node_id; 84 __u8 node_type; 85 __u8 svc_type; 86 __u8 resrvd5[3]; 87 __u8 rp_count; 88 }; 89 __u32 idle_filter; 90 }; 91 92 __u32 resrvd4; 93 } __packed; 94 95 struct icp_qat_fw_init_admin_resp { 96 __u8 flags; 97 __u8 resrvd1; 98 __u8 status; 99 __u8 cmd_id; 100 union { 101 __u32 resrvd2; 102 struct { 103 __u16 version_minor_num; 104 __u16 version_major_num; 105 }; 106 __u32 extended_features; 107 struct { 108 __u16 error_count; 109 __u16 latest_error; 110 }; 111 }; 112 __u64 opaque_data; 113 union { 114 __u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_4]; 115 struct { 116 __u32 version_patch_num; 117 __u8 context_id; 118 __u8 ae_id; 119 __u16 resrvd4; 120 __u64 resrvd5; 121 }; 122 struct { 123 __u64 req_rec_count; 124 __u64 resp_sent_count; 125 }; 126 struct { 127 __u16 compression_algos; 128 __u16 checksum_algos; 129 __u32 deflate_capabilities; 130 __u32 resrvd6; 131 __u32 lzs_capabilities; 132 }; 133 struct { 134 __u32 cipher_algos; 135 __u32 hash_algos; 136 __u16 keygen_algos; 137 __u16 other; 138 __u16 public_key_algos; 139 __u16 prime_algos; 140 }; 141 struct { 142 __u64 timestamp; 143 __u64 resrvd7; 144 }; 145 struct { 146 __u32 successful_count; 147 __u32 unsuccessful_count; 148 __u64 resrvd8; 149 }; 150 struct icp_qat_fw_init_admin_slice_cnt slices; 151 __u16 fw_capabilities; 152 }; 153 } __packed; 154 155 #define ICP_QAT_FW_SYNC ICP_QAT_FW_HEARTBEAT_SYNC 156 #define ICP_QAT_FW_CAPABILITIES_GET ICP_QAT_FW_CRYPTO_CAPABILITY_GET 157 158 #define ICP_QAT_NUMBER_OF_PM_EVENTS 8 159 160 struct icp_qat_fw_init_admin_pm_info { 161 __u16 max_pwrreq; 162 __u16 min_pwrreq; 163 __u16 resvrd1; 164 __u8 pwr_state; 165 __u8 resvrd2; 166 __u32 fusectl0; 167 struct_group(event_counters, 168 __u32 sys_pm; 169 __u32 host_msg; 170 __u32 unknown; 171 __u32 local_ssm; 172 __u32 timer; 173 ); 174 __u32 event_log[ICP_QAT_NUMBER_OF_PM_EVENTS]; 175 struct_group(pm, 176 __u32 fw_init; 177 __u32 pwrreq; 178 __u32 status; 179 __u32 main; 180 __u32 thread; 181 ); 182 struct_group(ssm, 183 __u32 pm_enable; 184 __u32 pm_active_status; 185 __u32 pm_managed_status; 186 __u32 pm_domain_status; 187 __u32 active_constraint; 188 ); 189 __u32 resvrd3[6]; 190 }; 191 192 #endif 193