1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) 2 /* Copyright(c) 2014 - 2020 Intel Corporation */ 3 #include <linux/types.h> 4 #include <linux/mutex.h> 5 #include <linux/slab.h> 6 #include <linux/iopoll.h> 7 #include <linux/pci.h> 8 #include <linux/dma-mapping.h> 9 #include "adf_accel_devices.h" 10 #include "adf_common_drv.h" 11 #include "adf_heartbeat.h" 12 #include "icp_qat_fw_init_admin.h" 13 14 #define ADF_ADMIN_MAILBOX_STRIDE 0x1000 15 #define ADF_ADMINMSG_LEN 32 16 #define ADF_CONST_TABLE_SIZE 1024 17 #define ADF_ADMIN_POLL_DELAY_US 20 18 #define ADF_ADMIN_POLL_TIMEOUT_US (5 * USEC_PER_SEC) 19 #define ADF_ONE_AE 1 20 21 static const u8 const_tab[1024] __aligned(1024) = { 22 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 23 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 24 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 25 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 26 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 27 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 28 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 29 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 30 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 31 0x00, 0x00, 0x00, 0x03, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x01, 32 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 33 0x00, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x02, 0x00, 0x00, 34 0x00, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 35 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 36 0x00, 0x00, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 37 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 38 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 39 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 40 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 41 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 42 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 43 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 44 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 45 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 46 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0xfe, 0xdc, 0xba, 0x98, 0x76, 47 0x54, 0x32, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 48 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x67, 0x45, 0x23, 0x01, 0xef, 0xcd, 0xab, 49 0x89, 0x98, 0xba, 0xdc, 0xfe, 0x10, 0x32, 0x54, 0x76, 0xc3, 0xd2, 0xe1, 0xf0, 50 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 51 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 52 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc1, 0x05, 0x9e, 53 0xd8, 0x36, 0x7c, 0xd5, 0x07, 0x30, 0x70, 0xdd, 0x17, 0xf7, 0x0e, 0x59, 0x39, 54 0xff, 0xc0, 0x0b, 0x31, 0x68, 0x58, 0x15, 0x11, 0x64, 0xf9, 0x8f, 0xa7, 0xbe, 55 0xfa, 0x4f, 0xa4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 56 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6a, 0x09, 0xe6, 0x67, 0xbb, 0x67, 0xae, 57 0x85, 0x3c, 0x6e, 0xf3, 0x72, 0xa5, 0x4f, 0xf5, 0x3a, 0x51, 0x0e, 0x52, 0x7f, 58 0x9b, 0x05, 0x68, 0x8c, 0x1f, 0x83, 0xd9, 0xab, 0x5b, 0xe0, 0xcd, 0x19, 0x05, 59 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 60 0x00, 0x00, 0xcb, 0xbb, 0x9d, 0x5d, 0xc1, 0x05, 0x9e, 0xd8, 0x62, 0x9a, 0x29, 61 0x2a, 0x36, 0x7c, 0xd5, 0x07, 0x91, 0x59, 0x01, 0x5a, 0x30, 0x70, 0xdd, 0x17, 62 0x15, 0x2f, 0xec, 0xd8, 0xf7, 0x0e, 0x59, 0x39, 0x67, 0x33, 0x26, 0x67, 0xff, 63 0xc0, 0x0b, 0x31, 0x8e, 0xb4, 0x4a, 0x87, 0x68, 0x58, 0x15, 0x11, 0xdb, 0x0c, 64 0x2e, 0x0d, 0x64, 0xf9, 0x8f, 0xa7, 0x47, 0xb5, 0x48, 0x1d, 0xbe, 0xfa, 0x4f, 65 0xa4, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 66 0x00, 0x00, 0x00, 0x00, 0x6a, 0x09, 0xe6, 0x67, 0xf3, 0xbc, 0xc9, 0x08, 0xbb, 67 0x67, 0xae, 0x85, 0x84, 0xca, 0xa7, 0x3b, 0x3c, 0x6e, 0xf3, 0x72, 0xfe, 0x94, 68 0xf8, 0x2b, 0xa5, 0x4f, 0xf5, 0x3a, 0x5f, 0x1d, 0x36, 0xf1, 0x51, 0x0e, 0x52, 69 0x7f, 0xad, 0xe6, 0x82, 0xd1, 0x9b, 0x05, 0x68, 0x8c, 0x2b, 0x3e, 0x6c, 0x1f, 70 0x1f, 0x83, 0xd9, 0xab, 0xfb, 0x41, 0xbd, 0x6b, 0x5b, 0xe0, 0xcd, 0x19, 0x13, 71 0x7e, 0x21, 0x79, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 72 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 73 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 74 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x18, 75 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 76 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x01, 0x00, 77 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 78 0x15, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x02, 0x00, 0x00, 0x00, 79 0x00, 0x00, 0x00, 0x14, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x02, 80 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 81 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 82 0x00, 0x00, 0x00, 0x00, 0x24, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 83 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 84 0x00, 0x00, 0x12, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x00, 0x00, 85 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 86 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x01, 0x00, 0x00, 0x00, 87 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x01, 88 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 89 0x00, 0x2B, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 90 0x00, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 91 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 92 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 93 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 94 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 95 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 96 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 97 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 98 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 99 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 100 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; 101 102 struct adf_admin_comms { 103 dma_addr_t phy_addr; 104 dma_addr_t const_tbl_addr; 105 void *virt_addr; 106 void *virt_tbl_addr; 107 void __iomem *mailbox_addr; 108 struct mutex lock; /* protects adf_admin_comms struct */ 109 }; 110 111 static int adf_put_admin_msg_sync(struct adf_accel_dev *accel_dev, u32 ae, 112 void *in, void *out) 113 { 114 int ret; 115 u32 status; 116 struct adf_admin_comms *admin = accel_dev->admin; 117 int offset = ae * ADF_ADMINMSG_LEN * 2; 118 void __iomem *mailbox = admin->mailbox_addr; 119 int mb_offset = ae * ADF_ADMIN_MAILBOX_STRIDE; 120 struct icp_qat_fw_init_admin_req *request = in; 121 122 mutex_lock(&admin->lock); 123 124 if (ADF_CSR_RD(mailbox, mb_offset) == 1) { 125 mutex_unlock(&admin->lock); 126 return -EAGAIN; 127 } 128 129 memcpy(admin->virt_addr + offset, in, ADF_ADMINMSG_LEN); 130 ADF_CSR_WR(mailbox, mb_offset, 1); 131 132 ret = read_poll_timeout(ADF_CSR_RD, status, status == 0, 133 ADF_ADMIN_POLL_DELAY_US, 134 ADF_ADMIN_POLL_TIMEOUT_US, true, 135 mailbox, mb_offset); 136 if (ret < 0) { 137 /* Response timeout */ 138 dev_err(&GET_DEV(accel_dev), 139 "Failed to send admin msg %d to accelerator %d\n", 140 request->cmd_id, ae); 141 } else { 142 /* Response received from admin message, we can now 143 * make response data available in "out" parameter. 144 */ 145 memcpy(out, admin->virt_addr + offset + 146 ADF_ADMINMSG_LEN, ADF_ADMINMSG_LEN); 147 } 148 149 mutex_unlock(&admin->lock); 150 return ret; 151 } 152 153 static int adf_send_admin(struct adf_accel_dev *accel_dev, 154 struct icp_qat_fw_init_admin_req *req, 155 struct icp_qat_fw_init_admin_resp *resp, 156 const unsigned long ae_mask) 157 { 158 u32 ae; 159 160 for_each_set_bit(ae, &ae_mask, ICP_QAT_HW_AE_DELIMITER) 161 if (adf_put_admin_msg_sync(accel_dev, ae, req, resp) || 162 resp->status) 163 return -EFAULT; 164 165 return 0; 166 } 167 168 static int adf_init_ae(struct adf_accel_dev *accel_dev) 169 { 170 struct icp_qat_fw_init_admin_req req; 171 struct icp_qat_fw_init_admin_resp resp; 172 struct adf_hw_device_data *hw_device = accel_dev->hw_device; 173 u32 ae_mask = hw_device->ae_mask; 174 175 memset(&req, 0, sizeof(req)); 176 memset(&resp, 0, sizeof(resp)); 177 req.cmd_id = ICP_QAT_FW_INIT_AE; 178 179 return adf_send_admin(accel_dev, &req, &resp, ae_mask); 180 } 181 182 static int adf_set_fw_constants(struct adf_accel_dev *accel_dev) 183 { 184 struct icp_qat_fw_init_admin_req req; 185 struct icp_qat_fw_init_admin_resp resp; 186 struct adf_hw_device_data *hw_device = accel_dev->hw_device; 187 u32 ae_mask = hw_device->admin_ae_mask ?: hw_device->ae_mask; 188 189 memset(&req, 0, sizeof(req)); 190 memset(&resp, 0, sizeof(resp)); 191 req.cmd_id = ICP_QAT_FW_CONSTANTS_CFG; 192 193 req.init_cfg_sz = ADF_CONST_TABLE_SIZE; 194 req.init_cfg_ptr = accel_dev->admin->const_tbl_addr; 195 196 return adf_send_admin(accel_dev, &req, &resp, ae_mask); 197 } 198 199 int adf_get_fw_timestamp(struct adf_accel_dev *accel_dev, u64 *timestamp) 200 { 201 struct icp_qat_fw_init_admin_req req = { }; 202 struct icp_qat_fw_init_admin_resp resp; 203 unsigned int ae_mask = ADF_ONE_AE; 204 int ret; 205 206 req.cmd_id = ICP_QAT_FW_TIMER_GET; 207 ret = adf_send_admin(accel_dev, &req, &resp, ae_mask); 208 if (ret) 209 return ret; 210 211 *timestamp = resp.timestamp; 212 return 0; 213 } 214 215 static int adf_get_dc_capabilities(struct adf_accel_dev *accel_dev, 216 u32 *capabilities) 217 { 218 struct adf_hw_device_data *hw_device = accel_dev->hw_device; 219 struct icp_qat_fw_init_admin_resp resp; 220 struct icp_qat_fw_init_admin_req req; 221 unsigned long ae_mask; 222 unsigned long ae; 223 int ret; 224 225 /* Target only service accelerator engines */ 226 ae_mask = hw_device->ae_mask & ~hw_device->admin_ae_mask; 227 228 memset(&req, 0, sizeof(req)); 229 memset(&resp, 0, sizeof(resp)); 230 req.cmd_id = ICP_QAT_FW_COMP_CAPABILITY_GET; 231 232 *capabilities = 0; 233 for_each_set_bit(ae, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) { 234 ret = adf_send_admin(accel_dev, &req, &resp, 1ULL << ae); 235 if (ret) 236 return ret; 237 238 *capabilities |= resp.extended_features; 239 } 240 241 return 0; 242 } 243 244 int adf_get_ae_fw_counters(struct adf_accel_dev *accel_dev, u16 ae, u64 *reqs, u64 *resps) 245 { 246 struct icp_qat_fw_init_admin_resp resp = { }; 247 struct icp_qat_fw_init_admin_req req = { }; 248 int ret; 249 250 req.cmd_id = ICP_QAT_FW_COUNTERS_GET; 251 252 ret = adf_put_admin_msg_sync(accel_dev, ae, &req, &resp); 253 if (ret || resp.status) 254 return -EFAULT; 255 256 *reqs = resp.req_rec_count; 257 *resps = resp.resp_sent_count; 258 259 return 0; 260 } 261 262 int adf_send_admin_tim_sync(struct adf_accel_dev *accel_dev, u32 cnt) 263 { 264 u32 ae_mask = accel_dev->hw_device->ae_mask; 265 struct icp_qat_fw_init_admin_req req = { }; 266 struct icp_qat_fw_init_admin_resp resp = { }; 267 268 req.cmd_id = ICP_QAT_FW_SYNC; 269 req.int_timer_ticks = cnt; 270 271 return adf_send_admin(accel_dev, &req, &resp, ae_mask); 272 } 273 274 int adf_send_admin_hb_timer(struct adf_accel_dev *accel_dev, uint32_t ticks) 275 { 276 u32 ae_mask = accel_dev->hw_device->ae_mask; 277 struct icp_qat_fw_init_admin_req req = { }; 278 struct icp_qat_fw_init_admin_resp resp; 279 280 req.cmd_id = ICP_QAT_FW_HEARTBEAT_TIMER_SET; 281 req.init_cfg_ptr = accel_dev->heartbeat->dma.phy_addr; 282 req.heartbeat_ticks = ticks; 283 284 return adf_send_admin(accel_dev, &req, &resp, ae_mask); 285 } 286 287 /** 288 * adf_send_admin_init() - Function sends init message to FW 289 * @accel_dev: Pointer to acceleration device. 290 * 291 * Function sends admin init message to the FW 292 * 293 * Return: 0 on success, error code otherwise. 294 */ 295 int adf_send_admin_init(struct adf_accel_dev *accel_dev) 296 { 297 u32 dc_capabilities = 0; 298 int ret; 299 300 ret = adf_get_dc_capabilities(accel_dev, &dc_capabilities); 301 if (ret) { 302 dev_err(&GET_DEV(accel_dev), "Cannot get dc capabilities\n"); 303 return ret; 304 } 305 accel_dev->hw_device->extended_dc_capabilities = dc_capabilities; 306 307 ret = adf_set_fw_constants(accel_dev); 308 if (ret) 309 return ret; 310 311 return adf_init_ae(accel_dev); 312 } 313 EXPORT_SYMBOL_GPL(adf_send_admin_init); 314 315 /** 316 * adf_init_admin_pm() - Function sends PM init message to FW 317 * @accel_dev: Pointer to acceleration device. 318 * @idle_delay: QAT HW idle time before power gating is initiated. 319 * 000 - 64us 320 * 001 - 128us 321 * 010 - 256us 322 * 011 - 512us 323 * 100 - 1ms 324 * 101 - 2ms 325 * 110 - 4ms 326 * 111 - 8ms 327 * 328 * Function sends to the FW the admin init message for the PM state 329 * configuration. 330 * 331 * Return: 0 on success, error code otherwise. 332 */ 333 int adf_init_admin_pm(struct adf_accel_dev *accel_dev, u32 idle_delay) 334 { 335 struct adf_hw_device_data *hw_data = accel_dev->hw_device; 336 struct icp_qat_fw_init_admin_resp resp = {0}; 337 struct icp_qat_fw_init_admin_req req = {0}; 338 u32 ae_mask = hw_data->admin_ae_mask; 339 340 if (!accel_dev->admin) { 341 dev_err(&GET_DEV(accel_dev), "adf_admin is not available\n"); 342 return -EFAULT; 343 } 344 345 req.cmd_id = ICP_QAT_FW_PM_STATE_CONFIG; 346 req.idle_filter = idle_delay; 347 348 return adf_send_admin(accel_dev, &req, &resp, ae_mask); 349 } 350 351 int adf_init_admin_comms(struct adf_accel_dev *accel_dev) 352 { 353 struct adf_admin_comms *admin; 354 struct adf_hw_device_data *hw_data = accel_dev->hw_device; 355 void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev); 356 struct admin_info admin_csrs_info; 357 u32 mailbox_offset, adminmsg_u, adminmsg_l; 358 void __iomem *mailbox; 359 u64 reg_val; 360 361 admin = kzalloc_node(sizeof(*accel_dev->admin), GFP_KERNEL, 362 dev_to_node(&GET_DEV(accel_dev))); 363 if (!admin) 364 return -ENOMEM; 365 admin->virt_addr = dma_alloc_coherent(&GET_DEV(accel_dev), PAGE_SIZE, 366 &admin->phy_addr, GFP_KERNEL); 367 if (!admin->virt_addr) { 368 dev_err(&GET_DEV(accel_dev), "Failed to allocate dma buff\n"); 369 kfree(admin); 370 return -ENOMEM; 371 } 372 373 admin->virt_tbl_addr = dma_alloc_coherent(&GET_DEV(accel_dev), 374 PAGE_SIZE, 375 &admin->const_tbl_addr, 376 GFP_KERNEL); 377 if (!admin->virt_tbl_addr) { 378 dev_err(&GET_DEV(accel_dev), "Failed to allocate const_tbl\n"); 379 dma_free_coherent(&GET_DEV(accel_dev), PAGE_SIZE, 380 admin->virt_addr, admin->phy_addr); 381 kfree(admin); 382 return -ENOMEM; 383 } 384 385 memcpy(admin->virt_tbl_addr, const_tab, sizeof(const_tab)); 386 hw_data->get_admin_info(&admin_csrs_info); 387 388 mailbox_offset = admin_csrs_info.mailbox_offset; 389 mailbox = pmisc_addr + mailbox_offset; 390 adminmsg_u = admin_csrs_info.admin_msg_ur; 391 adminmsg_l = admin_csrs_info.admin_msg_lr; 392 393 reg_val = (u64)admin->phy_addr; 394 ADF_CSR_WR(pmisc_addr, adminmsg_u, upper_32_bits(reg_val)); 395 ADF_CSR_WR(pmisc_addr, adminmsg_l, lower_32_bits(reg_val)); 396 397 mutex_init(&admin->lock); 398 admin->mailbox_addr = mailbox; 399 accel_dev->admin = admin; 400 return 0; 401 } 402 EXPORT_SYMBOL_GPL(adf_init_admin_comms); 403 404 void adf_exit_admin_comms(struct adf_accel_dev *accel_dev) 405 { 406 struct adf_admin_comms *admin = accel_dev->admin; 407 408 if (!admin) 409 return; 410 411 if (admin->virt_addr) 412 dma_free_coherent(&GET_DEV(accel_dev), PAGE_SIZE, 413 admin->virt_addr, admin->phy_addr); 414 if (admin->virt_tbl_addr) 415 dma_free_coherent(&GET_DEV(accel_dev), PAGE_SIZE, 416 admin->virt_tbl_addr, admin->const_tbl_addr); 417 418 mutex_destroy(&admin->lock); 419 kfree(admin); 420 accel_dev->admin = NULL; 421 } 422 EXPORT_SYMBOL_GPL(adf_exit_admin_comms); 423