1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2016 AmLogic, Inc. 4 * Author: Michael Turquette <mturquette@baylibre.com> 5 */ 6 7 /* 8 * MultiPhase Locked Loops are outputs from a PLL with additional frequency 9 * scaling capabilities. MPLL rates are calculated as: 10 * 11 * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384) 12 */ 13 14 #include <linux/clk-provider.h> 15 #include "clkc.h" 16 17 #define SDM_DEN 16384 18 #define N2_MIN 4 19 #define N2_MAX 511 20 21 static inline struct meson_clk_mpll_data * 22 meson_clk_mpll_data(struct clk_regmap *clk) 23 { 24 return (struct meson_clk_mpll_data *)clk->data; 25 } 26 27 static long rate_from_params(unsigned long parent_rate, 28 unsigned int sdm, 29 unsigned int n2) 30 { 31 unsigned long divisor = (SDM_DEN * n2) + sdm; 32 33 if (n2 < N2_MIN) 34 return -EINVAL; 35 36 return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor); 37 } 38 39 static void params_from_rate(unsigned long requested_rate, 40 unsigned long parent_rate, 41 unsigned int *sdm, 42 unsigned int *n2, 43 u8 flags) 44 { 45 uint64_t div = parent_rate; 46 uint64_t frac = do_div(div, requested_rate); 47 48 frac *= SDM_DEN; 49 50 if (flags & CLK_MESON_MPLL_ROUND_CLOSEST) 51 *sdm = DIV_ROUND_CLOSEST_ULL(frac, requested_rate); 52 else 53 *sdm = DIV_ROUND_UP_ULL(frac, requested_rate); 54 55 if (*sdm == SDM_DEN) { 56 *sdm = 0; 57 div += 1; 58 } 59 60 if (div < N2_MIN) { 61 *n2 = N2_MIN; 62 *sdm = 0; 63 } else if (div > N2_MAX) { 64 *n2 = N2_MAX; 65 *sdm = SDM_DEN - 1; 66 } else { 67 *n2 = div; 68 } 69 } 70 71 static unsigned long mpll_recalc_rate(struct clk_hw *hw, 72 unsigned long parent_rate) 73 { 74 struct clk_regmap *clk = to_clk_regmap(hw); 75 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); 76 unsigned int sdm, n2; 77 long rate; 78 79 sdm = meson_parm_read(clk->map, &mpll->sdm); 80 n2 = meson_parm_read(clk->map, &mpll->n2); 81 82 rate = rate_from_params(parent_rate, sdm, n2); 83 return rate < 0 ? 0 : rate; 84 } 85 86 static long mpll_round_rate(struct clk_hw *hw, 87 unsigned long rate, 88 unsigned long *parent_rate) 89 { 90 struct clk_regmap *clk = to_clk_regmap(hw); 91 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); 92 unsigned int sdm, n2; 93 94 params_from_rate(rate, *parent_rate, &sdm, &n2, mpll->flags); 95 return rate_from_params(*parent_rate, sdm, n2); 96 } 97 98 static int mpll_set_rate(struct clk_hw *hw, 99 unsigned long rate, 100 unsigned long parent_rate) 101 { 102 struct clk_regmap *clk = to_clk_regmap(hw); 103 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); 104 unsigned int sdm, n2; 105 unsigned long flags = 0; 106 107 params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags); 108 109 if (mpll->lock) 110 spin_lock_irqsave(mpll->lock, flags); 111 else 112 __acquire(mpll->lock); 113 114 /* Enable and set the fractional part */ 115 meson_parm_write(clk->map, &mpll->sdm, sdm); 116 meson_parm_write(clk->map, &mpll->sdm_en, 1); 117 118 /* Set additional fractional part enable if required */ 119 if (MESON_PARM_APPLICABLE(&mpll->ssen)) 120 meson_parm_write(clk->map, &mpll->ssen, 1); 121 122 /* Set the integer divider part */ 123 meson_parm_write(clk->map, &mpll->n2, n2); 124 125 /* Set the magic misc bit if required */ 126 if (MESON_PARM_APPLICABLE(&mpll->misc)) 127 meson_parm_write(clk->map, &mpll->misc, 1); 128 129 if (mpll->lock) 130 spin_unlock_irqrestore(mpll->lock, flags); 131 else 132 __release(mpll->lock); 133 134 return 0; 135 } 136 137 const struct clk_ops meson_clk_mpll_ro_ops = { 138 .recalc_rate = mpll_recalc_rate, 139 .round_rate = mpll_round_rate, 140 }; 141 142 const struct clk_ops meson_clk_mpll_ops = { 143 .recalc_rate = mpll_recalc_rate, 144 .round_rate = mpll_round_rate, 145 .set_rate = mpll_set_rate, 146 }; 147