xref: /linux/drivers/clk/mediatek/clk-mt8167-mfgcfg.c (revision 58f6259b7a08f8d47d4629609703d358b042f0fd)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2020 MediaTek Inc.
4  * Copyright (c) 2020 BayLibre, SAS
5  * Author: James Liao <jamesjj.liao@mediatek.com>
6  *         Fabien Parent <fparent@baylibre.com>
7  */
8 
9 #include <linux/clk-provider.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 
15 #include "clk-mtk.h"
16 #include "clk-gate.h"
17 
18 #include <dt-bindings/clock/mt8167-clk.h>
19 
20 static const struct mtk_gate_regs mfg_cg_regs = {
21 	.set_ofs = 0x4,
22 	.clr_ofs = 0x8,
23 	.sta_ofs = 0x0,
24 };
25 
26 #define GATE_MFG(_id, _name, _parent, _shift)			\
27 	GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
28 
29 static const struct mtk_gate mfg_clks[] = {
30 	GATE_MFG(CLK_MFG_BAXI, "mfg_baxi", "ahb_infra_sel", 0),
31 	GATE_MFG(CLK_MFG_BMEM, "mfg_bmem", "gfmux_emi1x_sel", 1),
32 	GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_mm", 2),
33 	GATE_MFG(CLK_MFG_B26M, "mfg_b26m", "clk26m_ck", 3),
34 };
35 
36 static const struct mtk_clk_desc mfg_desc = {
37 	.clks = mfg_clks,
38 	.num_clks = ARRAY_SIZE(mfg_clks),
39 };
40 
41 static const struct of_device_id of_match_clk_mt8167_mfgcfg[] = {
42 	{ .compatible = "mediatek,mt8167-mfgcfg", .data = &mfg_desc },
43 	{ /* sentinel */ }
44 };
45 MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_mfgcfg);
46 
47 static struct platform_driver clk_mt8167_mfgcfg_drv = {
48 	.probe = mtk_clk_simple_probe,
49 	.remove_new = mtk_clk_simple_remove,
50 	.driver = {
51 		.name = "clk-mt8167-mfgcfg",
52 		.of_match_table = of_match_clk_mt8167_mfgcfg,
53 	},
54 };
55 module_platform_driver(clk_mt8167_mfgcfg_drv);
56 MODULE_LICENSE("GPL");
57