xref: /linux/drivers/clk/actions/owl-pll.h (revision 307797159ac25fe5a2048bf5c6a5718298edca57)
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // OWL pll clock driver
4 //
5 // Copyright (c) 2014 Actions Semi Inc.
6 // Author: David Liu <liuwei@actions-semi.com>
7 //
8 // Copyright (c) 2018 Linaro Ltd.
9 // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10 
11 #ifndef _OWL_PLL_H_
12 #define _OWL_PLL_H_
13 
14 #include "owl-common.h"
15 
16 /* last entry should have rate = 0 */
17 struct clk_pll_table {
18 	unsigned int		val;
19 	unsigned long		rate;
20 };
21 
22 struct owl_pll_hw {
23 	u32			reg;
24 	u32			bfreq;
25 	u8			bit_idx;
26 	u8			shift;
27 	u8			width;
28 	u8			min_mul;
29 	u8			max_mul;
30 	const struct clk_pll_table *table;
31 };
32 
33 struct owl_pll {
34 	struct owl_pll_hw	pll_hw;
35 	struct owl_clk_common	common;
36 };
37 
38 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,			\
39 		   _width, _min_mul, _max_mul, _table)			\
40 	{								\
41 		.reg		= _reg,					\
42 		.bfreq		= _bfreq,				\
43 		.bit_idx	= _bit_idx,				\
44 		.shift		= _shift,				\
45 		.width		= _width,				\
46 		.min_mul	= _min_mul,				\
47 		.max_mul	= _max_mul,				\
48 		.table		= _table,				\
49 	}
50 
51 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx,	\
52 		_shift, _width, _min_mul, _max_mul, _table, _flags)	\
53 	struct owl_pll _struct = {					\
54 		.pll_hw	= OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,	\
55 				     _width, _min_mul,			\
56 				     _max_mul, _table),			\
57 		.common = {						\
58 			.regmap = NULL,					\
59 			.hw.init = CLK_HW_INIT(_name,			\
60 					       _parent,			\
61 					       &owl_pll_ops,		\
62 					       _flags),			\
63 		},							\
64 	}
65 
66 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx,	\
67 		_shift, _width, _min_mul, _max_mul, _table, _flags)	\
68 	struct owl_pll _struct = {					\
69 		.pll_hw	= OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,	\
70 				     _width, _min_mul,			\
71 				     _max_mul, _table),			\
72 		.common = {						\
73 			.regmap = NULL,					\
74 			.hw.init = CLK_HW_INIT_NO_PARENT(_name,		\
75 					       &owl_pll_ops,		\
76 					       _flags),			\
77 		},							\
78 	}
79 
80 #define mul_mask(m)		((1 << ((m)->width)) - 1)
81 #define PLL_STABILITY_WAIT_US	(50)
82 
83 static inline struct owl_pll *hw_to_owl_pll(const struct clk_hw *hw)
84 {
85 	struct owl_clk_common *common = hw_to_owl_clk_common(hw);
86 
87 	return container_of(common, struct owl_pll, common);
88 }
89 
90 extern const struct clk_ops owl_pll_ops;
91 
92 #endif /* _OWL_PLL_H_ */
93