1 /* 2 * VIA AGPGART routines. 3 */ 4 5 #include <linux/types.h> 6 #include <linux/module.h> 7 #include <linux/pci.h> 8 #include <linux/init.h> 9 #include <linux/agp_backend.h> 10 #include "agp.h" 11 12 static const struct pci_device_id agp_via_pci_table[]; 13 14 #define VIA_GARTCTRL 0x80 15 #define VIA_APSIZE 0x84 16 #define VIA_ATTBASE 0x88 17 18 #define VIA_AGP3_GARTCTRL 0x90 19 #define VIA_AGP3_APSIZE 0x94 20 #define VIA_AGP3_ATTBASE 0x98 21 #define VIA_AGPSEL 0xfd 22 23 static int via_fetch_size(void) 24 { 25 int i; 26 u8 temp; 27 struct aper_size_info_8 *values; 28 29 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 30 pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp); 31 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 32 if (temp == values[i].size_value) { 33 agp_bridge->previous_size = 34 agp_bridge->current_size = (void *) (values + i); 35 agp_bridge->aperture_size_idx = i; 36 return values[i].size; 37 } 38 } 39 printk(KERN_ERR PFX "Unknown aperture size from AGP bridge (0x%x)\n", temp); 40 return 0; 41 } 42 43 44 static int via_configure(void) 45 { 46 u32 temp; 47 struct aper_size_info_8 *current_size; 48 49 current_size = A_SIZE_8(agp_bridge->current_size); 50 /* aperture size */ 51 pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, 52 current_size->size_value); 53 /* address to map too */ 54 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 55 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 56 57 /* GART control register */ 58 pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f); 59 60 /* attbase - aperture GATT base */ 61 pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE, 62 (agp_bridge->gatt_bus_addr & 0xfffff000) | 3); 63 return 0; 64 } 65 66 67 static void via_cleanup(void) 68 { 69 struct aper_size_info_8 *previous_size; 70 71 previous_size = A_SIZE_8(agp_bridge->previous_size); 72 pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, 73 previous_size->size_value); 74 /* Do not disable by writing 0 to VIA_ATTBASE, it screws things up 75 * during reinitialization. 76 */ 77 } 78 79 80 static void via_tlbflush(struct agp_memory *mem) 81 { 82 u32 temp; 83 84 pci_read_config_dword(agp_bridge->dev, VIA_GARTCTRL, &temp); 85 temp |= (1<<7); 86 pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp); 87 temp &= ~(1<<7); 88 pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, temp); 89 } 90 91 92 static const struct aper_size_info_8 via_generic_sizes[9] = 93 { 94 {256, 65536, 6, 0}, 95 {128, 32768, 5, 128}, 96 {64, 16384, 4, 192}, 97 {32, 8192, 3, 224}, 98 {16, 4096, 2, 240}, 99 {8, 2048, 1, 248}, 100 {4, 1024, 0, 252}, 101 {2, 512, 0, 254}, 102 {1, 256, 0, 255} 103 }; 104 105 106 static int via_fetch_size_agp3(void) 107 { 108 int i; 109 u16 temp; 110 struct aper_size_info_16 *values; 111 112 values = A_SIZE_16(agp_bridge->driver->aperture_sizes); 113 pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp); 114 temp &= 0xfff; 115 116 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 117 if (temp == values[i].size_value) { 118 agp_bridge->previous_size = 119 agp_bridge->current_size = (void *) (values + i); 120 agp_bridge->aperture_size_idx = i; 121 return values[i].size; 122 } 123 } 124 return 0; 125 } 126 127 128 static int via_configure_agp3(void) 129 { 130 u32 temp; 131 struct aper_size_info_16 *current_size; 132 133 current_size = A_SIZE_16(agp_bridge->current_size); 134 135 /* address to map too */ 136 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 137 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 138 139 /* attbase - aperture GATT base */ 140 pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE, 141 agp_bridge->gatt_bus_addr & 0xfffff000); 142 143 /* 1. Enable GTLB in RX90<7>, all AGP aperture access needs to fetch 144 * translation table first. 145 * 2. Enable AGP aperture in RX91<0>. This bit controls the enabling of the 146 * graphics AGP aperture for the AGP3.0 port. 147 */ 148 pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp); 149 pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp | (3<<7)); 150 return 0; 151 } 152 153 154 static void via_cleanup_agp3(void) 155 { 156 struct aper_size_info_16 *previous_size; 157 158 previous_size = A_SIZE_16(agp_bridge->previous_size); 159 pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value); 160 } 161 162 163 static void via_tlbflush_agp3(struct agp_memory *mem) 164 { 165 u32 temp; 166 167 pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp); 168 pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7)); 169 pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp); 170 } 171 172 173 static const struct agp_bridge_driver via_agp3_driver = { 174 .owner = THIS_MODULE, 175 .aperture_sizes = agp3_generic_sizes, 176 .size_type = U8_APER_SIZE, 177 .num_aperture_sizes = 10, 178 .needs_scratch_page = true, 179 .configure = via_configure_agp3, 180 .fetch_size = via_fetch_size_agp3, 181 .cleanup = via_cleanup_agp3, 182 .tlb_flush = via_tlbflush_agp3, 183 .mask_memory = agp_generic_mask_memory, 184 .masks = NULL, 185 .agp_enable = agp_generic_enable, 186 .cache_flush = global_cache_flush, 187 .create_gatt_table = agp_generic_create_gatt_table, 188 .free_gatt_table = agp_generic_free_gatt_table, 189 .insert_memory = agp_generic_insert_memory, 190 .remove_memory = agp_generic_remove_memory, 191 .alloc_by_type = agp_generic_alloc_by_type, 192 .free_by_type = agp_generic_free_by_type, 193 .agp_alloc_page = agp_generic_alloc_page, 194 .agp_alloc_pages = agp_generic_alloc_pages, 195 .agp_destroy_page = agp_generic_destroy_page, 196 .agp_destroy_pages = agp_generic_destroy_pages, 197 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 198 }; 199 200 static const struct agp_bridge_driver via_driver = { 201 .owner = THIS_MODULE, 202 .aperture_sizes = via_generic_sizes, 203 .size_type = U8_APER_SIZE, 204 .num_aperture_sizes = 9, 205 .needs_scratch_page = true, 206 .configure = via_configure, 207 .fetch_size = via_fetch_size, 208 .cleanup = via_cleanup, 209 .tlb_flush = via_tlbflush, 210 .mask_memory = agp_generic_mask_memory, 211 .masks = NULL, 212 .agp_enable = agp_generic_enable, 213 .cache_flush = global_cache_flush, 214 .create_gatt_table = agp_generic_create_gatt_table, 215 .free_gatt_table = agp_generic_free_gatt_table, 216 .insert_memory = agp_generic_insert_memory, 217 .remove_memory = agp_generic_remove_memory, 218 .alloc_by_type = agp_generic_alloc_by_type, 219 .free_by_type = agp_generic_free_by_type, 220 .agp_alloc_page = agp_generic_alloc_page, 221 .agp_alloc_pages = agp_generic_alloc_pages, 222 .agp_destroy_page = agp_generic_destroy_page, 223 .agp_destroy_pages = agp_generic_destroy_pages, 224 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 225 }; 226 227 static struct agp_device_ids via_agp_device_ids[] = 228 { 229 { 230 .device_id = PCI_DEVICE_ID_VIA_82C597_0, 231 .chipset_name = "Apollo VP3", 232 }, 233 234 { 235 .device_id = PCI_DEVICE_ID_VIA_82C598_0, 236 .chipset_name = "Apollo MVP3", 237 }, 238 239 { 240 .device_id = PCI_DEVICE_ID_VIA_8501_0, 241 .chipset_name = "Apollo MVP4", 242 }, 243 244 /* VT8601 */ 245 { 246 .device_id = PCI_DEVICE_ID_VIA_8601_0, 247 .chipset_name = "Apollo ProMedia/PLE133Ta", 248 }, 249 250 /* VT82C693A / VT28C694T */ 251 { 252 .device_id = PCI_DEVICE_ID_VIA_82C691_0, 253 .chipset_name = "Apollo Pro 133", 254 }, 255 256 { 257 .device_id = PCI_DEVICE_ID_VIA_8371_0, 258 .chipset_name = "KX133", 259 }, 260 261 /* VT8633 */ 262 { 263 .device_id = PCI_DEVICE_ID_VIA_8633_0, 264 .chipset_name = "Pro 266", 265 }, 266 267 { 268 .device_id = PCI_DEVICE_ID_VIA_XN266, 269 .chipset_name = "Apollo Pro266", 270 }, 271 272 /* VT8361 */ 273 { 274 .device_id = PCI_DEVICE_ID_VIA_8361, 275 .chipset_name = "KLE133", 276 }, 277 278 /* VT8365 / VT8362 */ 279 { 280 .device_id = PCI_DEVICE_ID_VIA_8363_0, 281 .chipset_name = "Twister-K/KT133x/KM133", 282 }, 283 284 /* VT8753A */ 285 { 286 .device_id = PCI_DEVICE_ID_VIA_8753_0, 287 .chipset_name = "P4X266", 288 }, 289 290 /* VT8366 */ 291 { 292 .device_id = PCI_DEVICE_ID_VIA_8367_0, 293 .chipset_name = "KT266/KY266x/KT333", 294 }, 295 296 /* VT8633 (for CuMine/ Celeron) */ 297 { 298 .device_id = PCI_DEVICE_ID_VIA_8653_0, 299 .chipset_name = "Pro266T", 300 }, 301 302 /* KM266 / PM266 */ 303 { 304 .device_id = PCI_DEVICE_ID_VIA_XM266, 305 .chipset_name = "PM266/KM266", 306 }, 307 308 /* CLE266 */ 309 { 310 .device_id = PCI_DEVICE_ID_VIA_862X_0, 311 .chipset_name = "CLE266", 312 }, 313 314 { 315 .device_id = PCI_DEVICE_ID_VIA_8377_0, 316 .chipset_name = "KT400/KT400A/KT600", 317 }, 318 319 /* VT8604 / VT8605 / VT8603 320 * (Apollo Pro133A chipset with S3 Savage4) */ 321 { 322 .device_id = PCI_DEVICE_ID_VIA_8605_0, 323 .chipset_name = "ProSavage PM133/PL133/PN133" 324 }, 325 326 /* P4M266x/P4N266 */ 327 { 328 .device_id = PCI_DEVICE_ID_VIA_8703_51_0, 329 .chipset_name = "P4M266x/P4N266", 330 }, 331 332 /* VT8754 */ 333 { 334 .device_id = PCI_DEVICE_ID_VIA_8754C_0, 335 .chipset_name = "PT800", 336 }, 337 338 /* P4X600 */ 339 { 340 .device_id = PCI_DEVICE_ID_VIA_8763_0, 341 .chipset_name = "P4X600" 342 }, 343 344 /* KM400 */ 345 { 346 .device_id = PCI_DEVICE_ID_VIA_8378_0, 347 .chipset_name = "KM400/KM400A", 348 }, 349 350 /* PT880 */ 351 { 352 .device_id = PCI_DEVICE_ID_VIA_PT880, 353 .chipset_name = "PT880", 354 }, 355 356 /* PT880 Ultra */ 357 { 358 .device_id = PCI_DEVICE_ID_VIA_PT880ULTRA, 359 .chipset_name = "PT880 Ultra", 360 }, 361 362 /* PT890 */ 363 { 364 .device_id = PCI_DEVICE_ID_VIA_8783_0, 365 .chipset_name = "PT890", 366 }, 367 368 /* PM800/PN800/PM880/PN880 */ 369 { 370 .device_id = PCI_DEVICE_ID_VIA_PX8X0_0, 371 .chipset_name = "PM800/PN800/PM880/PN880", 372 }, 373 /* KT880 */ 374 { 375 .device_id = PCI_DEVICE_ID_VIA_3269_0, 376 .chipset_name = "KT880", 377 }, 378 /* KTxxx/Px8xx */ 379 { 380 .device_id = PCI_DEVICE_ID_VIA_83_87XX_1, 381 .chipset_name = "VT83xx/VT87xx/KTxxx/Px8xx", 382 }, 383 /* P4M800 */ 384 { 385 .device_id = PCI_DEVICE_ID_VIA_3296_0, 386 .chipset_name = "P4M800", 387 }, 388 /* P4M800CE */ 389 { 390 .device_id = PCI_DEVICE_ID_VIA_P4M800CE, 391 .chipset_name = "VT3314", 392 }, 393 /* VT3324 / CX700 */ 394 { 395 .device_id = PCI_DEVICE_ID_VIA_VT3324, 396 .chipset_name = "CX700", 397 }, 398 /* VT3336 - this is a chipset for AMD Athlon/K8 CPU. Due to K8's unique 399 * architecture, the AGP resource and behavior are different from 400 * the traditional AGP which resides only in chipset. AGP is used 401 * by 3D driver which wasn't available for the VT3336 and VT3364 402 * generation until now. Unfortunately, by testing, VT3364 works 403 * but VT3336 doesn't. - explanation from via, just leave this as 404 * as a placeholder to avoid future patches adding it back in. 405 */ 406 #if 0 407 { 408 .device_id = PCI_DEVICE_ID_VIA_VT3336, 409 .chipset_name = "VT3336", 410 }, 411 #endif 412 /* P4M890 */ 413 { 414 .device_id = PCI_DEVICE_ID_VIA_P4M890, 415 .chipset_name = "P4M890", 416 }, 417 /* P4M900 */ 418 { 419 .device_id = PCI_DEVICE_ID_VIA_VT3364, 420 .chipset_name = "P4M900", 421 }, 422 { }, /* dummy final entry, always present */ 423 }; 424 425 426 /* 427 * VIA's AGP3 chipsets do magick to put the AGP bridge compliant 428 * with the same standards version as the graphics card. 429 */ 430 static void check_via_agp3 (struct agp_bridge_data *bridge) 431 { 432 u8 reg; 433 434 pci_read_config_byte(bridge->dev, VIA_AGPSEL, ®); 435 /* Check AGP 2.0 compatibility mode. */ 436 if ((reg & (1<<1))==0) 437 bridge->driver = &via_agp3_driver; 438 } 439 440 441 static int agp_via_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 442 { 443 struct agp_device_ids *devs = via_agp_device_ids; 444 struct agp_bridge_data *bridge; 445 int j = 0; 446 u8 cap_ptr; 447 448 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 449 if (!cap_ptr) 450 return -ENODEV; 451 452 j = ent - agp_via_pci_table; 453 printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name); 454 455 bridge = agp_alloc_bridge(); 456 if (!bridge) 457 return -ENOMEM; 458 459 bridge->dev = pdev; 460 bridge->capndx = cap_ptr; 461 bridge->driver = &via_driver; 462 463 /* 464 * Garg, there are KT400s with KT266 IDs. 465 */ 466 if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) { 467 /* Is there a KT400 subsystem ? */ 468 if (pdev->subsystem_device == PCI_DEVICE_ID_VIA_8377_0) { 469 printk(KERN_INFO PFX "Found KT400 in disguise as a KT266.\n"); 470 check_via_agp3(bridge); 471 } 472 } 473 474 /* If this is an AGP3 bridge, check which mode its in and adjust. */ 475 get_agp_version(bridge); 476 if (bridge->major_version >= 3) 477 check_via_agp3(bridge); 478 479 /* Fill in the mode register */ 480 pci_read_config_dword(pdev, 481 bridge->capndx+PCI_AGP_STATUS, &bridge->mode); 482 483 pci_set_drvdata(pdev, bridge); 484 return agp_add_bridge(bridge); 485 } 486 487 static void agp_via_remove(struct pci_dev *pdev) 488 { 489 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 490 491 agp_remove_bridge(bridge); 492 agp_put_bridge(bridge); 493 } 494 495 #ifdef CONFIG_PM 496 497 static int agp_via_suspend(struct pci_dev *pdev, pm_message_t state) 498 { 499 pci_save_state (pdev); 500 pci_set_power_state (pdev, PCI_D3hot); 501 502 return 0; 503 } 504 505 static int agp_via_resume(struct pci_dev *pdev) 506 { 507 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 508 509 pci_set_power_state (pdev, PCI_D0); 510 pci_restore_state(pdev); 511 512 if (bridge->driver == &via_agp3_driver) 513 return via_configure_agp3(); 514 else if (bridge->driver == &via_driver) 515 return via_configure(); 516 517 return 0; 518 } 519 520 #endif /* CONFIG_PM */ 521 522 /* must be the same order as name table above */ 523 static const struct pci_device_id agp_via_pci_table[] = { 524 #define ID(x) \ 525 { \ 526 .class = (PCI_CLASS_BRIDGE_HOST << 8), \ 527 .class_mask = ~0, \ 528 .vendor = PCI_VENDOR_ID_VIA, \ 529 .device = x, \ 530 .subvendor = PCI_ANY_ID, \ 531 .subdevice = PCI_ANY_ID, \ 532 } 533 ID(PCI_DEVICE_ID_VIA_82C597_0), 534 ID(PCI_DEVICE_ID_VIA_82C598_0), 535 ID(PCI_DEVICE_ID_VIA_8501_0), 536 ID(PCI_DEVICE_ID_VIA_8601_0), 537 ID(PCI_DEVICE_ID_VIA_82C691_0), 538 ID(PCI_DEVICE_ID_VIA_8371_0), 539 ID(PCI_DEVICE_ID_VIA_8633_0), 540 ID(PCI_DEVICE_ID_VIA_XN266), 541 ID(PCI_DEVICE_ID_VIA_8361), 542 ID(PCI_DEVICE_ID_VIA_8363_0), 543 ID(PCI_DEVICE_ID_VIA_8753_0), 544 ID(PCI_DEVICE_ID_VIA_8367_0), 545 ID(PCI_DEVICE_ID_VIA_8653_0), 546 ID(PCI_DEVICE_ID_VIA_XM266), 547 ID(PCI_DEVICE_ID_VIA_862X_0), 548 ID(PCI_DEVICE_ID_VIA_8377_0), 549 ID(PCI_DEVICE_ID_VIA_8605_0), 550 ID(PCI_DEVICE_ID_VIA_8703_51_0), 551 ID(PCI_DEVICE_ID_VIA_8754C_0), 552 ID(PCI_DEVICE_ID_VIA_8763_0), 553 ID(PCI_DEVICE_ID_VIA_8378_0), 554 ID(PCI_DEVICE_ID_VIA_PT880), 555 ID(PCI_DEVICE_ID_VIA_PT880ULTRA), 556 ID(PCI_DEVICE_ID_VIA_8783_0), 557 ID(PCI_DEVICE_ID_VIA_PX8X0_0), 558 ID(PCI_DEVICE_ID_VIA_3269_0), 559 ID(PCI_DEVICE_ID_VIA_83_87XX_1), 560 ID(PCI_DEVICE_ID_VIA_3296_0), 561 ID(PCI_DEVICE_ID_VIA_P4M800CE), 562 ID(PCI_DEVICE_ID_VIA_VT3324), 563 ID(PCI_DEVICE_ID_VIA_P4M890), 564 ID(PCI_DEVICE_ID_VIA_VT3364), 565 { } 566 }; 567 568 MODULE_DEVICE_TABLE(pci, agp_via_pci_table); 569 570 571 static struct pci_driver agp_via_pci_driver = { 572 .name = "agpgart-via", 573 .id_table = agp_via_pci_table, 574 .probe = agp_via_probe, 575 .remove = agp_via_remove, 576 #ifdef CONFIG_PM 577 .suspend = agp_via_suspend, 578 .resume = agp_via_resume, 579 #endif 580 }; 581 582 583 static int __init agp_via_init(void) 584 { 585 if (agp_off) 586 return -EINVAL; 587 return pci_register_driver(&agp_via_pci_driver); 588 } 589 590 static void __exit agp_via_cleanup(void) 591 { 592 pci_unregister_driver(&agp_via_pci_driver); 593 } 594 595 module_init(agp_via_init); 596 module_exit(agp_via_cleanup); 597 598 MODULE_LICENSE("GPL"); 599 MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 600