1 /* 2 * sata_mv.c - Marvell SATA support 3 * 4 * Copyright 2008-2009: Marvell Corporation, all rights reserved. 5 * Copyright 2005: EMC Corporation, all rights reserved. 6 * Copyright 2005 Red Hat, Inc. All rights reserved. 7 * 8 * Originally written by Brett Russ. 9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>. 10 * 11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; version 2 of the License. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 */ 27 28 /* 29 * sata_mv TODO list: 30 * 31 * --> Develop a low-power-consumption strategy, and implement it. 32 * 33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds. 34 * 35 * --> [Experiment, Marvell value added] Is it possible to use target 36 * mode to cross-connect two Linux boxes with Marvell cards? If so, 37 * creating LibATA target mode support would be very interesting. 38 * 39 * Target mode, for those without docs, is the ability to directly 40 * connect two SATA ports. 41 */ 42 43 /* 44 * 80x1-B2 errata PCI#11: 45 * 46 * Users of the 6041/6081 Rev.B2 chips (current is C0) 47 * should be careful to insert those cards only onto PCI-X bus #0, 48 * and only in device slots 0..7, not higher. The chips may not 49 * work correctly otherwise (note: this is a pretty rare condition). 50 */ 51 52 #include <linux/kernel.h> 53 #include <linux/module.h> 54 #include <linux/pci.h> 55 #include <linux/init.h> 56 #include <linux/blkdev.h> 57 #include <linux/delay.h> 58 #include <linux/interrupt.h> 59 #include <linux/dmapool.h> 60 #include <linux/dma-mapping.h> 61 #include <linux/device.h> 62 #include <linux/clk.h> 63 #include <linux/platform_device.h> 64 #include <linux/ata_platform.h> 65 #include <linux/mbus.h> 66 #include <linux/bitops.h> 67 #include <linux/gfp.h> 68 #include <scsi/scsi_host.h> 69 #include <scsi/scsi_cmnd.h> 70 #include <scsi/scsi_device.h> 71 #include <linux/libata.h> 72 73 #define DRV_NAME "sata_mv" 74 #define DRV_VERSION "1.28" 75 76 /* 77 * module options 78 */ 79 80 static int msi; 81 #ifdef CONFIG_PCI 82 module_param(msi, int, S_IRUGO); 83 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 84 #endif 85 86 static int irq_coalescing_io_count; 87 module_param(irq_coalescing_io_count, int, S_IRUGO); 88 MODULE_PARM_DESC(irq_coalescing_io_count, 89 "IRQ coalescing I/O count threshold (0..255)"); 90 91 static int irq_coalescing_usecs; 92 module_param(irq_coalescing_usecs, int, S_IRUGO); 93 MODULE_PARM_DESC(irq_coalescing_usecs, 94 "IRQ coalescing time threshold in usecs"); 95 96 enum { 97 /* BAR's are enumerated in terms of pci_resource_start() terms */ 98 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 99 MV_IO_BAR = 2, /* offset 0x18: IO space */ 100 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 101 102 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 103 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 104 105 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */ 106 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */ 107 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */ 108 MAX_COAL_IO_COUNT = 255, /* completed I/O count */ 109 110 MV_PCI_REG_BASE = 0, 111 112 /* 113 * Per-chip ("all ports") interrupt coalescing feature. 114 * This is only for GEN_II / GEN_IIE hardware. 115 * 116 * Coalescing defers the interrupt until either the IO_THRESHOLD 117 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 118 */ 119 COAL_REG_BASE = 0x18000, 120 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08), 121 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */ 122 123 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc), 124 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0), 125 126 /* 127 * Registers for the (unused here) transaction coalescing feature: 128 */ 129 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88), 130 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c), 131 132 SATAHC0_REG_BASE = 0x20000, 133 FLASH_CTL = 0x1046c, 134 GPIO_PORT_CTL = 0x104f0, 135 RESET_CFG = 0x180d8, 136 137 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 138 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 139 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 140 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 141 142 MV_MAX_Q_DEPTH = 32, 143 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 144 145 /* CRQB needs alignment on a 1KB boundary. Size == 1KB 146 * CRPB needs alignment on a 256B boundary. Size == 256B 147 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 148 */ 149 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 150 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 151 MV_MAX_SG_CT = 256, 152 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 153 154 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 155 MV_PORT_HC_SHIFT = 2, 156 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 157 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 158 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 159 160 /* Host Flags */ 161 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 162 163 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 164 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING, 165 166 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI, 167 168 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ | 169 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA, 170 171 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN, 172 173 CRQB_FLAG_READ = (1 << 0), 174 CRQB_TAG_SHIFT = 1, 175 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 176 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 177 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 178 CRQB_CMD_ADDR_SHIFT = 8, 179 CRQB_CMD_CS = (0x2 << 11), 180 CRQB_CMD_LAST = (1 << 15), 181 182 CRPB_FLAG_STATUS_SHIFT = 8, 183 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 184 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 185 186 EPRD_FLAG_END_OF_TBL = (1 << 31), 187 188 /* PCI interface registers */ 189 190 MV_PCI_COMMAND = 0xc00, 191 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */ 192 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 193 194 PCI_MAIN_CMD_STS = 0xd30, 195 STOP_PCI_MASTER = (1 << 2), 196 PCI_MASTER_EMPTY = (1 << 3), 197 GLOB_SFT_RST = (1 << 4), 198 199 MV_PCI_MODE = 0xd00, 200 MV_PCI_MODE_MASK = 0x30, 201 202 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 203 MV_PCI_DISC_TIMER = 0xd04, 204 MV_PCI_MSI_TRIGGER = 0xc38, 205 MV_PCI_SERR_MASK = 0xc28, 206 MV_PCI_XBAR_TMOUT = 0x1d04, 207 MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 208 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 209 MV_PCI_ERR_ATTRIBUTE = 0x1d48, 210 MV_PCI_ERR_COMMAND = 0x1d50, 211 212 PCI_IRQ_CAUSE = 0x1d58, 213 PCI_IRQ_MASK = 0x1d5c, 214 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 215 216 PCIE_IRQ_CAUSE = 0x1900, 217 PCIE_IRQ_MASK = 0x1910, 218 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 219 220 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 221 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60, 222 PCI_HC_MAIN_IRQ_MASK = 0x1d64, 223 SOC_HC_MAIN_IRQ_CAUSE = 0x20020, 224 SOC_HC_MAIN_IRQ_MASK = 0x20024, 225 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */ 226 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */ 227 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 228 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 229 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */ 230 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */ 231 PCI_ERR = (1 << 18), 232 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */ 233 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */ 234 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */ 235 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */ 236 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */ 237 GPIO_INT = (1 << 22), 238 SELF_INT = (1 << 23), 239 TWSI_INT = (1 << 24), 240 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 241 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 242 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 243 244 /* SATAHC registers */ 245 HC_CFG = 0x00, 246 247 HC_IRQ_CAUSE = 0x14, 248 DMA_IRQ = (1 << 0), /* shift by port # */ 249 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 250 DEV_IRQ = (1 << 8), /* shift by port # */ 251 252 /* 253 * Per-HC (Host-Controller) interrupt coalescing feature. 254 * This is present on all chip generations. 255 * 256 * Coalescing defers the interrupt until either the IO_THRESHOLD 257 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 258 */ 259 HC_IRQ_COAL_IO_THRESHOLD = 0x000c, 260 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010, 261 262 SOC_LED_CTRL = 0x2c, 263 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */ 264 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */ 265 /* with dev activity LED */ 266 267 /* Shadow block registers */ 268 SHD_BLK = 0x100, 269 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */ 270 271 /* SATA registers */ 272 SATA_STATUS = 0x300, /* ctrl, err regs follow status */ 273 SATA_ACTIVE = 0x350, 274 FIS_IRQ_CAUSE = 0x364, 275 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */ 276 277 LTMODE = 0x30c, /* requires read-after-write */ 278 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 279 280 PHY_MODE2 = 0x330, 281 PHY_MODE3 = 0x310, 282 283 PHY_MODE4 = 0x314, /* requires read-after-write */ 284 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ 285 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ 286 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ 287 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ 288 289 SATA_IFCTL = 0x344, 290 SATA_TESTCTL = 0x348, 291 SATA_IFSTAT = 0x34c, 292 VENDOR_UNIQUE_FIS = 0x35c, 293 294 FISCFG = 0x360, 295 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 296 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 297 298 PHY_MODE9_GEN2 = 0x398, 299 PHY_MODE9_GEN1 = 0x39c, 300 PHYCFG_OFS = 0x3a0, /* only in 65n devices */ 301 302 MV5_PHY_MODE = 0x74, 303 MV5_LTMODE = 0x30, 304 MV5_PHY_CTL = 0x0C, 305 SATA_IFCFG = 0x050, 306 307 MV_M2_PREAMP_MASK = 0x7e0, 308 309 /* Port registers */ 310 EDMA_CFG = 0, 311 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 312 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 313 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 314 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 315 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 316 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 317 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 318 319 EDMA_ERR_IRQ_CAUSE = 0x8, 320 EDMA_ERR_IRQ_MASK = 0xc, 321 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 322 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 323 EDMA_ERR_DEV = (1 << 2), /* device error */ 324 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 325 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 326 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 327 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 328 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 329 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 330 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 331 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 332 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 333 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 334 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 335 336 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 337 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 338 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 339 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 340 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 341 342 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 343 344 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 345 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 346 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 347 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 348 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 349 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 350 351 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 352 353 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 354 EDMA_ERR_OVERRUN_5 = (1 << 5), 355 EDMA_ERR_UNDERRUN_5 = (1 << 6), 356 357 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 358 EDMA_ERR_LNK_CTRL_RX_1 | 359 EDMA_ERR_LNK_CTRL_RX_3 | 360 EDMA_ERR_LNK_CTRL_TX, 361 362 EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 363 EDMA_ERR_PRD_PAR | 364 EDMA_ERR_DEV_DCON | 365 EDMA_ERR_DEV_CON | 366 EDMA_ERR_SERR | 367 EDMA_ERR_SELF_DIS | 368 EDMA_ERR_CRQB_PAR | 369 EDMA_ERR_CRPB_PAR | 370 EDMA_ERR_INTRL_PAR | 371 EDMA_ERR_IORDY | 372 EDMA_ERR_LNK_CTRL_RX_2 | 373 EDMA_ERR_LNK_DATA_RX | 374 EDMA_ERR_LNK_DATA_TX | 375 EDMA_ERR_TRANS_PROTO, 376 377 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 378 EDMA_ERR_PRD_PAR | 379 EDMA_ERR_DEV_DCON | 380 EDMA_ERR_DEV_CON | 381 EDMA_ERR_OVERRUN_5 | 382 EDMA_ERR_UNDERRUN_5 | 383 EDMA_ERR_SELF_DIS_5 | 384 EDMA_ERR_CRQB_PAR | 385 EDMA_ERR_CRPB_PAR | 386 EDMA_ERR_INTRL_PAR | 387 EDMA_ERR_IORDY, 388 389 EDMA_REQ_Q_BASE_HI = 0x10, 390 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */ 391 392 EDMA_REQ_Q_OUT_PTR = 0x18, 393 EDMA_REQ_Q_PTR_SHIFT = 5, 394 395 EDMA_RSP_Q_BASE_HI = 0x1c, 396 EDMA_RSP_Q_IN_PTR = 0x20, 397 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */ 398 EDMA_RSP_Q_PTR_SHIFT = 3, 399 400 EDMA_CMD = 0x28, /* EDMA command register */ 401 EDMA_EN = (1 << 0), /* enable EDMA */ 402 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 403 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 404 405 EDMA_STATUS = 0x30, /* EDMA engine status */ 406 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 407 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 408 409 EDMA_IORDY_TMOUT = 0x34, 410 EDMA_ARB_CFG = 0x38, 411 412 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */ 413 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */ 414 415 BMDMA_CMD = 0x224, /* bmdma command register */ 416 BMDMA_STATUS = 0x228, /* bmdma status register */ 417 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */ 418 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */ 419 420 /* Host private flags (hp_flags) */ 421 MV_HP_FLAG_MSI = (1 << 0), 422 MV_HP_ERRATA_50XXB0 = (1 << 1), 423 MV_HP_ERRATA_50XXB2 = (1 << 2), 424 MV_HP_ERRATA_60X1B2 = (1 << 3), 425 MV_HP_ERRATA_60X1C0 = (1 << 4), 426 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 427 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 428 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 429 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 430 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 431 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ 432 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */ 433 434 /* Port private flags (pp_flags) */ 435 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 436 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 437 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 438 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ 439 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */ 440 }; 441 442 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 443 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 444 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 445 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 446 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) 447 448 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 449 #define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 450 451 enum { 452 /* DMA boundary 0xffff is required by the s/g splitting 453 * we need on /length/ in mv_fill-sg(). 454 */ 455 MV_DMA_BOUNDARY = 0xffffU, 456 457 /* mask of register bits containing lower 32 bits 458 * of EDMA request queue DMA address 459 */ 460 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 461 462 /* ditto, for response queue */ 463 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 464 }; 465 466 enum chip_type { 467 chip_504x, 468 chip_508x, 469 chip_5080, 470 chip_604x, 471 chip_608x, 472 chip_6042, 473 chip_7042, 474 chip_soc, 475 }; 476 477 /* Command ReQuest Block: 32B */ 478 struct mv_crqb { 479 __le32 sg_addr; 480 __le32 sg_addr_hi; 481 __le16 ctrl_flags; 482 __le16 ata_cmd[11]; 483 }; 484 485 struct mv_crqb_iie { 486 __le32 addr; 487 __le32 addr_hi; 488 __le32 flags; 489 __le32 len; 490 __le32 ata_cmd[4]; 491 }; 492 493 /* Command ResPonse Block: 8B */ 494 struct mv_crpb { 495 __le16 id; 496 __le16 flags; 497 __le32 tmstmp; 498 }; 499 500 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 501 struct mv_sg { 502 __le32 addr; 503 __le32 flags_size; 504 __le32 addr_hi; 505 __le32 reserved; 506 }; 507 508 /* 509 * We keep a local cache of a few frequently accessed port 510 * registers here, to avoid having to read them (very slow) 511 * when switching between EDMA and non-EDMA modes. 512 */ 513 struct mv_cached_regs { 514 u32 fiscfg; 515 u32 ltmode; 516 u32 haltcond; 517 u32 unknown_rsvd; 518 }; 519 520 struct mv_port_priv { 521 struct mv_crqb *crqb; 522 dma_addr_t crqb_dma; 523 struct mv_crpb *crpb; 524 dma_addr_t crpb_dma; 525 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 526 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 527 528 unsigned int req_idx; 529 unsigned int resp_idx; 530 531 u32 pp_flags; 532 struct mv_cached_regs cached; 533 unsigned int delayed_eh_pmp_map; 534 }; 535 536 struct mv_port_signal { 537 u32 amps; 538 u32 pre; 539 }; 540 541 struct mv_host_priv { 542 u32 hp_flags; 543 unsigned int board_idx; 544 u32 main_irq_mask; 545 struct mv_port_signal signal[8]; 546 const struct mv_hw_ops *ops; 547 int n_ports; 548 void __iomem *base; 549 void __iomem *main_irq_cause_addr; 550 void __iomem *main_irq_mask_addr; 551 u32 irq_cause_offset; 552 u32 irq_mask_offset; 553 u32 unmask_all_irqs; 554 555 #if defined(CONFIG_HAVE_CLK) 556 struct clk *clk; 557 #endif 558 /* 559 * These consistent DMA memory pools give us guaranteed 560 * alignment for hardware-accessed data structures, 561 * and less memory waste in accomplishing the alignment. 562 */ 563 struct dma_pool *crqb_pool; 564 struct dma_pool *crpb_pool; 565 struct dma_pool *sg_tbl_pool; 566 }; 567 568 struct mv_hw_ops { 569 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 570 unsigned int port); 571 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 572 void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 573 void __iomem *mmio); 574 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 575 unsigned int n_hc); 576 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 577 void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 578 }; 579 580 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 581 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 582 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 583 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 584 static int mv_port_start(struct ata_port *ap); 585 static void mv_port_stop(struct ata_port *ap); 586 static int mv_qc_defer(struct ata_queued_cmd *qc); 587 static void mv_qc_prep(struct ata_queued_cmd *qc); 588 static void mv_qc_prep_iie(struct ata_queued_cmd *qc); 589 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 590 static int mv_hardreset(struct ata_link *link, unsigned int *class, 591 unsigned long deadline); 592 static void mv_eh_freeze(struct ata_port *ap); 593 static void mv_eh_thaw(struct ata_port *ap); 594 static void mv6_dev_config(struct ata_device *dev); 595 596 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 597 unsigned int port); 598 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 599 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 600 void __iomem *mmio); 601 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 602 unsigned int n_hc); 603 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 604 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 605 606 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 607 unsigned int port); 608 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 609 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 610 void __iomem *mmio); 611 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 612 unsigned int n_hc); 613 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 614 static void mv_soc_enable_leds(struct mv_host_priv *hpriv, 615 void __iomem *mmio); 616 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 617 void __iomem *mmio); 618 static int mv_soc_reset_hc(struct mv_host_priv *hpriv, 619 void __iomem *mmio, unsigned int n_hc); 620 static void mv_soc_reset_flash(struct mv_host_priv *hpriv, 621 void __iomem *mmio); 622 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 623 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, 624 void __iomem *mmio, unsigned int port); 625 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 626 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 627 unsigned int port_no); 628 static int mv_stop_edma(struct ata_port *ap); 629 static int mv_stop_edma_engine(void __iomem *port_mmio); 630 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma); 631 632 static void mv_pmp_select(struct ata_port *ap, int pmp); 633 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 634 unsigned long deadline); 635 static int mv_softreset(struct ata_link *link, unsigned int *class, 636 unsigned long deadline); 637 static void mv_pmp_error_handler(struct ata_port *ap); 638 static void mv_process_crpb_entries(struct ata_port *ap, 639 struct mv_port_priv *pp); 640 641 static void mv_sff_irq_clear(struct ata_port *ap); 642 static int mv_check_atapi_dma(struct ata_queued_cmd *qc); 643 static void mv_bmdma_setup(struct ata_queued_cmd *qc); 644 static void mv_bmdma_start(struct ata_queued_cmd *qc); 645 static void mv_bmdma_stop(struct ata_queued_cmd *qc); 646 static u8 mv_bmdma_status(struct ata_port *ap); 647 static u8 mv_sff_check_status(struct ata_port *ap); 648 649 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 650 * because we have to allow room for worst case splitting of 651 * PRDs for 64K boundaries in mv_fill_sg(). 652 */ 653 static struct scsi_host_template mv5_sht = { 654 ATA_BASE_SHT(DRV_NAME), 655 .sg_tablesize = MV_MAX_SG_CT / 2, 656 .dma_boundary = MV_DMA_BOUNDARY, 657 }; 658 659 static struct scsi_host_template mv6_sht = { 660 ATA_NCQ_SHT(DRV_NAME), 661 .can_queue = MV_MAX_Q_DEPTH - 1, 662 .sg_tablesize = MV_MAX_SG_CT / 2, 663 .dma_boundary = MV_DMA_BOUNDARY, 664 }; 665 666 static struct ata_port_operations mv5_ops = { 667 .inherits = &ata_sff_port_ops, 668 669 .lost_interrupt = ATA_OP_NULL, 670 671 .qc_defer = mv_qc_defer, 672 .qc_prep = mv_qc_prep, 673 .qc_issue = mv_qc_issue, 674 675 .freeze = mv_eh_freeze, 676 .thaw = mv_eh_thaw, 677 .hardreset = mv_hardreset, 678 679 .scr_read = mv5_scr_read, 680 .scr_write = mv5_scr_write, 681 682 .port_start = mv_port_start, 683 .port_stop = mv_port_stop, 684 }; 685 686 static struct ata_port_operations mv6_ops = { 687 .inherits = &ata_bmdma_port_ops, 688 689 .lost_interrupt = ATA_OP_NULL, 690 691 .qc_defer = mv_qc_defer, 692 .qc_prep = mv_qc_prep, 693 .qc_issue = mv_qc_issue, 694 695 .dev_config = mv6_dev_config, 696 697 .freeze = mv_eh_freeze, 698 .thaw = mv_eh_thaw, 699 .hardreset = mv_hardreset, 700 .softreset = mv_softreset, 701 .pmp_hardreset = mv_pmp_hardreset, 702 .pmp_softreset = mv_softreset, 703 .error_handler = mv_pmp_error_handler, 704 705 .scr_read = mv_scr_read, 706 .scr_write = mv_scr_write, 707 708 .sff_check_status = mv_sff_check_status, 709 .sff_irq_clear = mv_sff_irq_clear, 710 .check_atapi_dma = mv_check_atapi_dma, 711 .bmdma_setup = mv_bmdma_setup, 712 .bmdma_start = mv_bmdma_start, 713 .bmdma_stop = mv_bmdma_stop, 714 .bmdma_status = mv_bmdma_status, 715 716 .port_start = mv_port_start, 717 .port_stop = mv_port_stop, 718 }; 719 720 static struct ata_port_operations mv_iie_ops = { 721 .inherits = &mv6_ops, 722 .dev_config = ATA_OP_NULL, 723 .qc_prep = mv_qc_prep_iie, 724 }; 725 726 static const struct ata_port_info mv_port_info[] = { 727 { /* chip_504x */ 728 .flags = MV_GEN_I_FLAGS, 729 .pio_mask = ATA_PIO4, 730 .udma_mask = ATA_UDMA6, 731 .port_ops = &mv5_ops, 732 }, 733 { /* chip_508x */ 734 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 735 .pio_mask = ATA_PIO4, 736 .udma_mask = ATA_UDMA6, 737 .port_ops = &mv5_ops, 738 }, 739 { /* chip_5080 */ 740 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 741 .pio_mask = ATA_PIO4, 742 .udma_mask = ATA_UDMA6, 743 .port_ops = &mv5_ops, 744 }, 745 { /* chip_604x */ 746 .flags = MV_GEN_II_FLAGS, 747 .pio_mask = ATA_PIO4, 748 .udma_mask = ATA_UDMA6, 749 .port_ops = &mv6_ops, 750 }, 751 { /* chip_608x */ 752 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC, 753 .pio_mask = ATA_PIO4, 754 .udma_mask = ATA_UDMA6, 755 .port_ops = &mv6_ops, 756 }, 757 { /* chip_6042 */ 758 .flags = MV_GEN_IIE_FLAGS, 759 .pio_mask = ATA_PIO4, 760 .udma_mask = ATA_UDMA6, 761 .port_ops = &mv_iie_ops, 762 }, 763 { /* chip_7042 */ 764 .flags = MV_GEN_IIE_FLAGS, 765 .pio_mask = ATA_PIO4, 766 .udma_mask = ATA_UDMA6, 767 .port_ops = &mv_iie_ops, 768 }, 769 { /* chip_soc */ 770 .flags = MV_GEN_IIE_FLAGS, 771 .pio_mask = ATA_PIO4, 772 .udma_mask = ATA_UDMA6, 773 .port_ops = &mv_iie_ops, 774 }, 775 }; 776 777 static const struct pci_device_id mv_pci_tbl[] = { 778 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 779 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 780 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 781 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 782 /* RocketRAID 1720/174x have different identifiers */ 783 { PCI_VDEVICE(TTI, 0x1720), chip_6042 }, 784 { PCI_VDEVICE(TTI, 0x1740), chip_6042 }, 785 { PCI_VDEVICE(TTI, 0x1742), chip_6042 }, 786 787 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 788 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 789 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 790 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 791 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 792 793 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 794 795 /* Adaptec 1430SA */ 796 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 797 798 /* Marvell 7042 support */ 799 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 800 801 /* Highpoint RocketRAID PCIe series */ 802 { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 803 { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 804 805 { } /* terminate list */ 806 }; 807 808 static const struct mv_hw_ops mv5xxx_ops = { 809 .phy_errata = mv5_phy_errata, 810 .enable_leds = mv5_enable_leds, 811 .read_preamp = mv5_read_preamp, 812 .reset_hc = mv5_reset_hc, 813 .reset_flash = mv5_reset_flash, 814 .reset_bus = mv5_reset_bus, 815 }; 816 817 static const struct mv_hw_ops mv6xxx_ops = { 818 .phy_errata = mv6_phy_errata, 819 .enable_leds = mv6_enable_leds, 820 .read_preamp = mv6_read_preamp, 821 .reset_hc = mv6_reset_hc, 822 .reset_flash = mv6_reset_flash, 823 .reset_bus = mv_reset_pci_bus, 824 }; 825 826 static const struct mv_hw_ops mv_soc_ops = { 827 .phy_errata = mv6_phy_errata, 828 .enable_leds = mv_soc_enable_leds, 829 .read_preamp = mv_soc_read_preamp, 830 .reset_hc = mv_soc_reset_hc, 831 .reset_flash = mv_soc_reset_flash, 832 .reset_bus = mv_soc_reset_bus, 833 }; 834 835 static const struct mv_hw_ops mv_soc_65n_ops = { 836 .phy_errata = mv_soc_65n_phy_errata, 837 .enable_leds = mv_soc_enable_leds, 838 .reset_hc = mv_soc_reset_hc, 839 .reset_flash = mv_soc_reset_flash, 840 .reset_bus = mv_soc_reset_bus, 841 }; 842 843 /* 844 * Functions 845 */ 846 847 static inline void writelfl(unsigned long data, void __iomem *addr) 848 { 849 writel(data, addr); 850 (void) readl(addr); /* flush to avoid PCI posted write */ 851 } 852 853 static inline unsigned int mv_hc_from_port(unsigned int port) 854 { 855 return port >> MV_PORT_HC_SHIFT; 856 } 857 858 static inline unsigned int mv_hardport_from_port(unsigned int port) 859 { 860 return port & MV_PORT_MASK; 861 } 862 863 /* 864 * Consolidate some rather tricky bit shift calculations. 865 * This is hot-path stuff, so not a function. 866 * Simple code, with two return values, so macro rather than inline. 867 * 868 * port is the sole input, in range 0..7. 869 * shift is one output, for use with main_irq_cause / main_irq_mask registers. 870 * hardport is the other output, in range 0..3. 871 * 872 * Note that port and hardport may be the same variable in some cases. 873 */ 874 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 875 { \ 876 shift = mv_hc_from_port(port) * HC_SHIFT; \ 877 hardport = mv_hardport_from_port(port); \ 878 shift += hardport * 2; \ 879 } 880 881 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 882 { 883 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 884 } 885 886 static inline void __iomem *mv_hc_base_from_port(void __iomem *base, 887 unsigned int port) 888 { 889 return mv_hc_base(base, mv_hc_from_port(port)); 890 } 891 892 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 893 { 894 return mv_hc_base_from_port(base, port) + 895 MV_SATAHC_ARBTR_REG_SZ + 896 (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 897 } 898 899 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 900 { 901 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 902 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 903 904 return hc_mmio + ofs; 905 } 906 907 static inline void __iomem *mv_host_base(struct ata_host *host) 908 { 909 struct mv_host_priv *hpriv = host->private_data; 910 return hpriv->base; 911 } 912 913 static inline void __iomem *mv_ap_base(struct ata_port *ap) 914 { 915 return mv_port_base(mv_host_base(ap->host), ap->port_no); 916 } 917 918 static inline int mv_get_hc_count(unsigned long port_flags) 919 { 920 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 921 } 922 923 /** 924 * mv_save_cached_regs - (re-)initialize cached port registers 925 * @ap: the port whose registers we are caching 926 * 927 * Initialize the local cache of port registers, 928 * so that reading them over and over again can 929 * be avoided on the hotter paths of this driver. 930 * This saves a few microseconds each time we switch 931 * to/from EDMA mode to perform (eg.) a drive cache flush. 932 */ 933 static void mv_save_cached_regs(struct ata_port *ap) 934 { 935 void __iomem *port_mmio = mv_ap_base(ap); 936 struct mv_port_priv *pp = ap->private_data; 937 938 pp->cached.fiscfg = readl(port_mmio + FISCFG); 939 pp->cached.ltmode = readl(port_mmio + LTMODE); 940 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); 941 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); 942 } 943 944 /** 945 * mv_write_cached_reg - write to a cached port register 946 * @addr: hardware address of the register 947 * @old: pointer to cached value of the register 948 * @new: new value for the register 949 * 950 * Write a new value to a cached register, 951 * but only if the value is different from before. 952 */ 953 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new) 954 { 955 if (new != *old) { 956 unsigned long laddr; 957 *old = new; 958 /* 959 * Workaround for 88SX60x1-B2 FEr SATA#13: 960 * Read-after-write is needed to prevent generating 64-bit 961 * write cycles on the PCI bus for SATA interface registers 962 * at offsets ending in 0x4 or 0xc. 963 * 964 * Looks like a lot of fuss, but it avoids an unnecessary 965 * +1 usec read-after-write delay for unaffected registers. 966 */ 967 laddr = (long)addr & 0xffff; 968 if (laddr >= 0x300 && laddr <= 0x33c) { 969 laddr &= 0x000f; 970 if (laddr == 0x4 || laddr == 0xc) { 971 writelfl(new, addr); /* read after write */ 972 return; 973 } 974 } 975 writel(new, addr); /* unaffected by the errata */ 976 } 977 } 978 979 static void mv_set_edma_ptrs(void __iomem *port_mmio, 980 struct mv_host_priv *hpriv, 981 struct mv_port_priv *pp) 982 { 983 u32 index; 984 985 /* 986 * initialize request queue 987 */ 988 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 989 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 990 991 WARN_ON(pp->crqb_dma & 0x3ff); 992 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); 993 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 994 port_mmio + EDMA_REQ_Q_IN_PTR); 995 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR); 996 997 /* 998 * initialize response queue 999 */ 1000 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 1001 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 1002 1003 WARN_ON(pp->crpb_dma & 0xff); 1004 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); 1005 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR); 1006 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 1007 port_mmio + EDMA_RSP_Q_OUT_PTR); 1008 } 1009 1010 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) 1011 { 1012 /* 1013 * When writing to the main_irq_mask in hardware, 1014 * we must ensure exclusivity between the interrupt coalescing bits 1015 * and the corresponding individual port DONE_IRQ bits. 1016 * 1017 * Note that this register is really an "IRQ enable" register, 1018 * not an "IRQ mask" register as Marvell's naming might suggest. 1019 */ 1020 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE)) 1021 mask &= ~DONE_IRQ_0_3; 1022 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE)) 1023 mask &= ~DONE_IRQ_4_7; 1024 writelfl(mask, hpriv->main_irq_mask_addr); 1025 } 1026 1027 static void mv_set_main_irq_mask(struct ata_host *host, 1028 u32 disable_bits, u32 enable_bits) 1029 { 1030 struct mv_host_priv *hpriv = host->private_data; 1031 u32 old_mask, new_mask; 1032 1033 old_mask = hpriv->main_irq_mask; 1034 new_mask = (old_mask & ~disable_bits) | enable_bits; 1035 if (new_mask != old_mask) { 1036 hpriv->main_irq_mask = new_mask; 1037 mv_write_main_irq_mask(new_mask, hpriv); 1038 } 1039 } 1040 1041 static void mv_enable_port_irqs(struct ata_port *ap, 1042 unsigned int port_bits) 1043 { 1044 unsigned int shift, hardport, port = ap->port_no; 1045 u32 disable_bits, enable_bits; 1046 1047 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 1048 1049 disable_bits = (DONE_IRQ | ERR_IRQ) << shift; 1050 enable_bits = port_bits << shift; 1051 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); 1052 } 1053 1054 static void mv_clear_and_enable_port_irqs(struct ata_port *ap, 1055 void __iomem *port_mmio, 1056 unsigned int port_irqs) 1057 { 1058 struct mv_host_priv *hpriv = ap->host->private_data; 1059 int hardport = mv_hardport_from_port(ap->port_no); 1060 void __iomem *hc_mmio = mv_hc_base_from_port( 1061 mv_host_base(ap->host), ap->port_no); 1062 u32 hc_irq_cause; 1063 1064 /* clear EDMA event indicators, if any */ 1065 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 1066 1067 /* clear pending irq events */ 1068 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 1069 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 1070 1071 /* clear FIS IRQ Cause */ 1072 if (IS_GEN_IIE(hpriv)) 1073 writelfl(0, port_mmio + FIS_IRQ_CAUSE); 1074 1075 mv_enable_port_irqs(ap, port_irqs); 1076 } 1077 1078 static void mv_set_irq_coalescing(struct ata_host *host, 1079 unsigned int count, unsigned int usecs) 1080 { 1081 struct mv_host_priv *hpriv = host->private_data; 1082 void __iomem *mmio = hpriv->base, *hc_mmio; 1083 u32 coal_enable = 0; 1084 unsigned long flags; 1085 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; 1086 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 1087 ALL_PORTS_COAL_DONE; 1088 1089 /* Disable IRQ coalescing if either threshold is zero */ 1090 if (!usecs || !count) { 1091 clks = count = 0; 1092 } else { 1093 /* Respect maximum limits of the hardware */ 1094 clks = usecs * COAL_CLOCKS_PER_USEC; 1095 if (clks > MAX_COAL_TIME_THRESHOLD) 1096 clks = MAX_COAL_TIME_THRESHOLD; 1097 if (count > MAX_COAL_IO_COUNT) 1098 count = MAX_COAL_IO_COUNT; 1099 } 1100 1101 spin_lock_irqsave(&host->lock, flags); 1102 mv_set_main_irq_mask(host, coal_disable, 0); 1103 1104 if (is_dual_hc && !IS_GEN_I(hpriv)) { 1105 /* 1106 * GEN_II/GEN_IIE with dual host controllers: 1107 * one set of global thresholds for the entire chip. 1108 */ 1109 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD); 1110 writel(count, mmio + IRQ_COAL_IO_THRESHOLD); 1111 /* clear leftover coal IRQ bit */ 1112 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 1113 if (count) 1114 coal_enable = ALL_PORTS_COAL_DONE; 1115 clks = count = 0; /* force clearing of regular regs below */ 1116 } 1117 1118 /* 1119 * All chips: independent thresholds for each HC on the chip. 1120 */ 1121 hc_mmio = mv_hc_base_from_port(mmio, 0); 1122 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1123 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1124 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 1125 if (count) 1126 coal_enable |= PORTS_0_3_COAL_DONE; 1127 if (is_dual_hc) { 1128 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC); 1129 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1130 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1131 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 1132 if (count) 1133 coal_enable |= PORTS_4_7_COAL_DONE; 1134 } 1135 1136 mv_set_main_irq_mask(host, 0, coal_enable); 1137 spin_unlock_irqrestore(&host->lock, flags); 1138 } 1139 1140 /** 1141 * mv_start_edma - Enable eDMA engine 1142 * @base: port base address 1143 * @pp: port private data 1144 * 1145 * Verify the local cache of the eDMA state is accurate with a 1146 * WARN_ON. 1147 * 1148 * LOCKING: 1149 * Inherited from caller. 1150 */ 1151 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio, 1152 struct mv_port_priv *pp, u8 protocol) 1153 { 1154 int want_ncq = (protocol == ATA_PROT_NCQ); 1155 1156 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1157 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 1158 if (want_ncq != using_ncq) 1159 mv_stop_edma(ap); 1160 } 1161 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 1162 struct mv_host_priv *hpriv = ap->host->private_data; 1163 1164 mv_edma_cfg(ap, want_ncq, 1); 1165 1166 mv_set_edma_ptrs(port_mmio, hpriv, pp); 1167 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ); 1168 1169 writelfl(EDMA_EN, port_mmio + EDMA_CMD); 1170 pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 1171 } 1172 } 1173 1174 static void mv_wait_for_edma_empty_idle(struct ata_port *ap) 1175 { 1176 void __iomem *port_mmio = mv_ap_base(ap); 1177 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 1178 const int per_loop = 5, timeout = (15 * 1000 / per_loop); 1179 int i; 1180 1181 /* 1182 * Wait for the EDMA engine to finish transactions in progress. 1183 * No idea what a good "timeout" value might be, but measurements 1184 * indicate that it often requires hundreds of microseconds 1185 * with two drives in-use. So we use the 15msec value above 1186 * as a rough guess at what even more drives might require. 1187 */ 1188 for (i = 0; i < timeout; ++i) { 1189 u32 edma_stat = readl(port_mmio + EDMA_STATUS); 1190 if ((edma_stat & empty_idle) == empty_idle) 1191 break; 1192 udelay(per_loop); 1193 } 1194 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ 1195 } 1196 1197 /** 1198 * mv_stop_edma_engine - Disable eDMA engine 1199 * @port_mmio: io base address 1200 * 1201 * LOCKING: 1202 * Inherited from caller. 1203 */ 1204 static int mv_stop_edma_engine(void __iomem *port_mmio) 1205 { 1206 int i; 1207 1208 /* Disable eDMA. The disable bit auto clears. */ 1209 writelfl(EDMA_DS, port_mmio + EDMA_CMD); 1210 1211 /* Wait for the chip to confirm eDMA is off. */ 1212 for (i = 10000; i > 0; i--) { 1213 u32 reg = readl(port_mmio + EDMA_CMD); 1214 if (!(reg & EDMA_EN)) 1215 return 0; 1216 udelay(10); 1217 } 1218 return -EIO; 1219 } 1220 1221 static int mv_stop_edma(struct ata_port *ap) 1222 { 1223 void __iomem *port_mmio = mv_ap_base(ap); 1224 struct mv_port_priv *pp = ap->private_data; 1225 int err = 0; 1226 1227 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 1228 return 0; 1229 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1230 mv_wait_for_edma_empty_idle(ap); 1231 if (mv_stop_edma_engine(port_mmio)) { 1232 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 1233 err = -EIO; 1234 } 1235 mv_edma_cfg(ap, 0, 0); 1236 return err; 1237 } 1238 1239 #ifdef ATA_DEBUG 1240 static void mv_dump_mem(void __iomem *start, unsigned bytes) 1241 { 1242 int b, w; 1243 for (b = 0; b < bytes; ) { 1244 DPRINTK("%p: ", start + b); 1245 for (w = 0; b < bytes && w < 4; w++) { 1246 printk("%08x ", readl(start + b)); 1247 b += sizeof(u32); 1248 } 1249 printk("\n"); 1250 } 1251 } 1252 #endif 1253 1254 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 1255 { 1256 #ifdef ATA_DEBUG 1257 int b, w; 1258 u32 dw; 1259 for (b = 0; b < bytes; ) { 1260 DPRINTK("%02x: ", b); 1261 for (w = 0; b < bytes && w < 4; w++) { 1262 (void) pci_read_config_dword(pdev, b, &dw); 1263 printk("%08x ", dw); 1264 b += sizeof(u32); 1265 } 1266 printk("\n"); 1267 } 1268 #endif 1269 } 1270 static void mv_dump_all_regs(void __iomem *mmio_base, int port, 1271 struct pci_dev *pdev) 1272 { 1273 #ifdef ATA_DEBUG 1274 void __iomem *hc_base = mv_hc_base(mmio_base, 1275 port >> MV_PORT_HC_SHIFT); 1276 void __iomem *port_base; 1277 int start_port, num_ports, p, start_hc, num_hcs, hc; 1278 1279 if (0 > port) { 1280 start_hc = start_port = 0; 1281 num_ports = 8; /* shld be benign for 4 port devs */ 1282 num_hcs = 2; 1283 } else { 1284 start_hc = port >> MV_PORT_HC_SHIFT; 1285 start_port = port; 1286 num_ports = num_hcs = 1; 1287 } 1288 DPRINTK("All registers for port(s) %u-%u:\n", start_port, 1289 num_ports > 1 ? num_ports - 1 : start_port); 1290 1291 if (NULL != pdev) { 1292 DPRINTK("PCI config space regs:\n"); 1293 mv_dump_pci_cfg(pdev, 0x68); 1294 } 1295 DPRINTK("PCI regs:\n"); 1296 mv_dump_mem(mmio_base+0xc00, 0x3c); 1297 mv_dump_mem(mmio_base+0xd00, 0x34); 1298 mv_dump_mem(mmio_base+0xf00, 0x4); 1299 mv_dump_mem(mmio_base+0x1d00, 0x6c); 1300 for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1301 hc_base = mv_hc_base(mmio_base, hc); 1302 DPRINTK("HC regs (HC %i):\n", hc); 1303 mv_dump_mem(hc_base, 0x1c); 1304 } 1305 for (p = start_port; p < start_port + num_ports; p++) { 1306 port_base = mv_port_base(mmio_base, p); 1307 DPRINTK("EDMA regs (port %i):\n", p); 1308 mv_dump_mem(port_base, 0x54); 1309 DPRINTK("SATA regs (port %i):\n", p); 1310 mv_dump_mem(port_base+0x300, 0x60); 1311 } 1312 #endif 1313 } 1314 1315 static unsigned int mv_scr_offset(unsigned int sc_reg_in) 1316 { 1317 unsigned int ofs; 1318 1319 switch (sc_reg_in) { 1320 case SCR_STATUS: 1321 case SCR_CONTROL: 1322 case SCR_ERROR: 1323 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32)); 1324 break; 1325 case SCR_ACTIVE: 1326 ofs = SATA_ACTIVE; /* active is not with the others */ 1327 break; 1328 default: 1329 ofs = 0xffffffffU; 1330 break; 1331 } 1332 return ofs; 1333 } 1334 1335 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 1336 { 1337 unsigned int ofs = mv_scr_offset(sc_reg_in); 1338 1339 if (ofs != 0xffffffffU) { 1340 *val = readl(mv_ap_base(link->ap) + ofs); 1341 return 0; 1342 } else 1343 return -EINVAL; 1344 } 1345 1346 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 1347 { 1348 unsigned int ofs = mv_scr_offset(sc_reg_in); 1349 1350 if (ofs != 0xffffffffU) { 1351 void __iomem *addr = mv_ap_base(link->ap) + ofs; 1352 if (sc_reg_in == SCR_CONTROL) { 1353 /* 1354 * Workaround for 88SX60x1 FEr SATA#26: 1355 * 1356 * COMRESETs have to take care not to accidently 1357 * put the drive to sleep when writing SCR_CONTROL. 1358 * Setting bits 12..15 prevents this problem. 1359 * 1360 * So if we see an outbound COMMRESET, set those bits. 1361 * Ditto for the followup write that clears the reset. 1362 * 1363 * The proprietary driver does this for 1364 * all chip versions, and so do we. 1365 */ 1366 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) 1367 val |= 0xf000; 1368 } 1369 writelfl(val, addr); 1370 return 0; 1371 } else 1372 return -EINVAL; 1373 } 1374 1375 static void mv6_dev_config(struct ata_device *adev) 1376 { 1377 /* 1378 * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1379 * 1380 * Gen-II does not support NCQ over a port multiplier 1381 * (no FIS-based switching). 1382 */ 1383 if (adev->flags & ATA_DFLAG_NCQ) { 1384 if (sata_pmp_attached(adev->link->ap)) { 1385 adev->flags &= ~ATA_DFLAG_NCQ; 1386 ata_dev_printk(adev, KERN_INFO, 1387 "NCQ disabled for command-based switching\n"); 1388 } 1389 } 1390 } 1391 1392 static int mv_qc_defer(struct ata_queued_cmd *qc) 1393 { 1394 struct ata_link *link = qc->dev->link; 1395 struct ata_port *ap = link->ap; 1396 struct mv_port_priv *pp = ap->private_data; 1397 1398 /* 1399 * Don't allow new commands if we're in a delayed EH state 1400 * for NCQ and/or FIS-based switching. 1401 */ 1402 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 1403 return ATA_DEFER_PORT; 1404 1405 /* PIO commands need exclusive link: no other commands [DMA or PIO] 1406 * can run concurrently. 1407 * set excl_link when we want to send a PIO command in DMA mode 1408 * or a non-NCQ command in NCQ mode. 1409 * When we receive a command from that link, and there are no 1410 * outstanding commands, mark a flag to clear excl_link and let 1411 * the command go through. 1412 */ 1413 if (unlikely(ap->excl_link)) { 1414 if (link == ap->excl_link) { 1415 if (ap->nr_active_links) 1416 return ATA_DEFER_PORT; 1417 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; 1418 return 0; 1419 } else 1420 return ATA_DEFER_PORT; 1421 } 1422 1423 /* 1424 * If the port is completely idle, then allow the new qc. 1425 */ 1426 if (ap->nr_active_links == 0) 1427 return 0; 1428 1429 /* 1430 * The port is operating in host queuing mode (EDMA) with NCQ 1431 * enabled, allow multiple NCQ commands. EDMA also allows 1432 * queueing multiple DMA commands but libata core currently 1433 * doesn't allow it. 1434 */ 1435 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && 1436 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { 1437 if (ata_is_ncq(qc->tf.protocol)) 1438 return 0; 1439 else { 1440 ap->excl_link = link; 1441 return ATA_DEFER_PORT; 1442 } 1443 } 1444 1445 return ATA_DEFER_PORT; 1446 } 1447 1448 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs) 1449 { 1450 struct mv_port_priv *pp = ap->private_data; 1451 void __iomem *port_mmio; 1452 1453 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; 1454 u32 ltmode, *old_ltmode = &pp->cached.ltmode; 1455 u32 haltcond, *old_haltcond = &pp->cached.haltcond; 1456 1457 ltmode = *old_ltmode & ~LTMODE_BIT8; 1458 haltcond = *old_haltcond | EDMA_ERR_DEV; 1459 1460 if (want_fbs) { 1461 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC; 1462 ltmode = *old_ltmode | LTMODE_BIT8; 1463 if (want_ncq) 1464 haltcond &= ~EDMA_ERR_DEV; 1465 else 1466 fiscfg |= FISCFG_WAIT_DEV_ERR; 1467 } else { 1468 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 1469 } 1470 1471 port_mmio = mv_ap_base(ap); 1472 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg); 1473 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode); 1474 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond); 1475 } 1476 1477 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1478 { 1479 struct mv_host_priv *hpriv = ap->host->private_data; 1480 u32 old, new; 1481 1482 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1483 old = readl(hpriv->base + GPIO_PORT_CTL); 1484 if (want_ncq) 1485 new = old | (1 << 22); 1486 else 1487 new = old & ~(1 << 22); 1488 if (new != old) 1489 writel(new, hpriv->base + GPIO_PORT_CTL); 1490 } 1491 1492 /** 1493 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma 1494 * @ap: Port being initialized 1495 * 1496 * There are two DMA modes on these chips: basic DMA, and EDMA. 1497 * 1498 * Bit-0 of the "EDMA RESERVED" register enables/disables use 1499 * of basic DMA on the GEN_IIE versions of the chips. 1500 * 1501 * This bit survives EDMA resets, and must be set for basic DMA 1502 * to function, and should be cleared when EDMA is active. 1503 */ 1504 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma) 1505 { 1506 struct mv_port_priv *pp = ap->private_data; 1507 u32 new, *old = &pp->cached.unknown_rsvd; 1508 1509 if (enable_bmdma) 1510 new = *old | 1; 1511 else 1512 new = *old & ~1; 1513 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new); 1514 } 1515 1516 /* 1517 * SOC chips have an issue whereby the HDD LEDs don't always blink 1518 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode 1519 * of the SOC takes care of it, generating a steady blink rate when 1520 * any drive on the chip is active. 1521 * 1522 * Unfortunately, the blink mode is a global hardware setting for the SOC, 1523 * so we must use it whenever at least one port on the SOC has NCQ enabled. 1524 * 1525 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal 1526 * LED operation works then, and provides better (more accurate) feedback. 1527 * 1528 * Note that this code assumes that an SOC never has more than one HC onboard. 1529 */ 1530 static void mv_soc_led_blink_enable(struct ata_port *ap) 1531 { 1532 struct ata_host *host = ap->host; 1533 struct mv_host_priv *hpriv = host->private_data; 1534 void __iomem *hc_mmio; 1535 u32 led_ctrl; 1536 1537 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) 1538 return; 1539 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; 1540 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1541 led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1542 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1543 } 1544 1545 static void mv_soc_led_blink_disable(struct ata_port *ap) 1546 { 1547 struct ata_host *host = ap->host; 1548 struct mv_host_priv *hpriv = host->private_data; 1549 void __iomem *hc_mmio; 1550 u32 led_ctrl; 1551 unsigned int port; 1552 1553 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) 1554 return; 1555 1556 /* disable led-blink only if no ports are using NCQ */ 1557 for (port = 0; port < hpriv->n_ports; port++) { 1558 struct ata_port *this_ap = host->ports[port]; 1559 struct mv_port_priv *pp = this_ap->private_data; 1560 1561 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 1562 return; 1563 } 1564 1565 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; 1566 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1567 led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1568 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1569 } 1570 1571 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma) 1572 { 1573 u32 cfg; 1574 struct mv_port_priv *pp = ap->private_data; 1575 struct mv_host_priv *hpriv = ap->host->private_data; 1576 void __iomem *port_mmio = mv_ap_base(ap); 1577 1578 /* set up non-NCQ EDMA configuration */ 1579 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1580 pp->pp_flags &= 1581 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 1582 1583 if (IS_GEN_I(hpriv)) 1584 cfg |= (1 << 8); /* enab config burst size mask */ 1585 1586 else if (IS_GEN_II(hpriv)) { 1587 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1588 mv_60x1_errata_sata25(ap, want_ncq); 1589 1590 } else if (IS_GEN_IIE(hpriv)) { 1591 int want_fbs = sata_pmp_attached(ap); 1592 /* 1593 * Possible future enhancement: 1594 * 1595 * The chip can use FBS with non-NCQ, if we allow it, 1596 * But first we need to have the error handling in place 1597 * for this mode (datasheet section 7.3.15.4.2.3). 1598 * So disallow non-NCQ FBS for now. 1599 */ 1600 want_fbs &= want_ncq; 1601 1602 mv_config_fbs(ap, want_ncq, want_fbs); 1603 1604 if (want_fbs) { 1605 pp->pp_flags |= MV_PP_FLAG_FBS_EN; 1606 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 1607 } 1608 1609 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1610 if (want_edma) { 1611 cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1612 if (!IS_SOC(hpriv)) 1613 cfg |= (1 << 18); /* enab early completion */ 1614 } 1615 if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1616 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1617 mv_bmdma_enable_iie(ap, !want_edma); 1618 1619 if (IS_SOC(hpriv)) { 1620 if (want_ncq) 1621 mv_soc_led_blink_enable(ap); 1622 else 1623 mv_soc_led_blink_disable(ap); 1624 } 1625 } 1626 1627 if (want_ncq) { 1628 cfg |= EDMA_CFG_NCQ; 1629 pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1630 } 1631 1632 writelfl(cfg, port_mmio + EDMA_CFG); 1633 } 1634 1635 static void mv_port_free_dma_mem(struct ata_port *ap) 1636 { 1637 struct mv_host_priv *hpriv = ap->host->private_data; 1638 struct mv_port_priv *pp = ap->private_data; 1639 int tag; 1640 1641 if (pp->crqb) { 1642 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1643 pp->crqb = NULL; 1644 } 1645 if (pp->crpb) { 1646 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1647 pp->crpb = NULL; 1648 } 1649 /* 1650 * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1651 * For later hardware, we have one unique sg_tbl per NCQ tag. 1652 */ 1653 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1654 if (pp->sg_tbl[tag]) { 1655 if (tag == 0 || !IS_GEN_I(hpriv)) 1656 dma_pool_free(hpriv->sg_tbl_pool, 1657 pp->sg_tbl[tag], 1658 pp->sg_tbl_dma[tag]); 1659 pp->sg_tbl[tag] = NULL; 1660 } 1661 } 1662 } 1663 1664 /** 1665 * mv_port_start - Port specific init/start routine. 1666 * @ap: ATA channel to manipulate 1667 * 1668 * Allocate and point to DMA memory, init port private memory, 1669 * zero indices. 1670 * 1671 * LOCKING: 1672 * Inherited from caller. 1673 */ 1674 static int mv_port_start(struct ata_port *ap) 1675 { 1676 struct device *dev = ap->host->dev; 1677 struct mv_host_priv *hpriv = ap->host->private_data; 1678 struct mv_port_priv *pp; 1679 unsigned long flags; 1680 int tag; 1681 1682 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 1683 if (!pp) 1684 return -ENOMEM; 1685 ap->private_data = pp; 1686 1687 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1688 if (!pp->crqb) 1689 return -ENOMEM; 1690 memset(pp->crqb, 0, MV_CRQB_Q_SZ); 1691 1692 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1693 if (!pp->crpb) 1694 goto out_port_free_dma_mem; 1695 memset(pp->crpb, 0, MV_CRPB_Q_SZ); 1696 1697 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ 1698 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) 1699 ap->flags |= ATA_FLAG_AN; 1700 /* 1701 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1702 * For later hardware, we need one unique sg_tbl per NCQ tag. 1703 */ 1704 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1705 if (tag == 0 || !IS_GEN_I(hpriv)) { 1706 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1707 GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1708 if (!pp->sg_tbl[tag]) 1709 goto out_port_free_dma_mem; 1710 } else { 1711 pp->sg_tbl[tag] = pp->sg_tbl[0]; 1712 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1713 } 1714 } 1715 1716 spin_lock_irqsave(ap->lock, flags); 1717 mv_save_cached_regs(ap); 1718 mv_edma_cfg(ap, 0, 0); 1719 spin_unlock_irqrestore(ap->lock, flags); 1720 1721 return 0; 1722 1723 out_port_free_dma_mem: 1724 mv_port_free_dma_mem(ap); 1725 return -ENOMEM; 1726 } 1727 1728 /** 1729 * mv_port_stop - Port specific cleanup/stop routine. 1730 * @ap: ATA channel to manipulate 1731 * 1732 * Stop DMA, cleanup port memory. 1733 * 1734 * LOCKING: 1735 * This routine uses the host lock to protect the DMA stop. 1736 */ 1737 static void mv_port_stop(struct ata_port *ap) 1738 { 1739 unsigned long flags; 1740 1741 spin_lock_irqsave(ap->lock, flags); 1742 mv_stop_edma(ap); 1743 mv_enable_port_irqs(ap, 0); 1744 spin_unlock_irqrestore(ap->lock, flags); 1745 mv_port_free_dma_mem(ap); 1746 } 1747 1748 /** 1749 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 1750 * @qc: queued command whose SG list to source from 1751 * 1752 * Populate the SG list and mark the last entry. 1753 * 1754 * LOCKING: 1755 * Inherited from caller. 1756 */ 1757 static void mv_fill_sg(struct ata_queued_cmd *qc) 1758 { 1759 struct mv_port_priv *pp = qc->ap->private_data; 1760 struct scatterlist *sg; 1761 struct mv_sg *mv_sg, *last_sg = NULL; 1762 unsigned int si; 1763 1764 mv_sg = pp->sg_tbl[qc->tag]; 1765 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1766 dma_addr_t addr = sg_dma_address(sg); 1767 u32 sg_len = sg_dma_len(sg); 1768 1769 while (sg_len) { 1770 u32 offset = addr & 0xffff; 1771 u32 len = sg_len; 1772 1773 if (offset + len > 0x10000) 1774 len = 0x10000 - offset; 1775 1776 mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 1777 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 1778 mv_sg->flags_size = cpu_to_le32(len & 0xffff); 1779 mv_sg->reserved = 0; 1780 1781 sg_len -= len; 1782 addr += len; 1783 1784 last_sg = mv_sg; 1785 mv_sg++; 1786 } 1787 } 1788 1789 if (likely(last_sg)) 1790 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 1791 mb(); /* ensure data structure is visible to the chipset */ 1792 } 1793 1794 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 1795 { 1796 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 1797 (last ? CRQB_CMD_LAST : 0); 1798 *cmdw = cpu_to_le16(tmp); 1799 } 1800 1801 /** 1802 * mv_sff_irq_clear - Clear hardware interrupt after DMA. 1803 * @ap: Port associated with this ATA transaction. 1804 * 1805 * We need this only for ATAPI bmdma transactions, 1806 * as otherwise we experience spurious interrupts 1807 * after libata-sff handles the bmdma interrupts. 1808 */ 1809 static void mv_sff_irq_clear(struct ata_port *ap) 1810 { 1811 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ); 1812 } 1813 1814 /** 1815 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA. 1816 * @qc: queued command to check for chipset/DMA compatibility. 1817 * 1818 * The bmdma engines cannot handle speculative data sizes 1819 * (bytecount under/over flow). So only allow DMA for 1820 * data transfer commands with known data sizes. 1821 * 1822 * LOCKING: 1823 * Inherited from caller. 1824 */ 1825 static int mv_check_atapi_dma(struct ata_queued_cmd *qc) 1826 { 1827 struct scsi_cmnd *scmd = qc->scsicmd; 1828 1829 if (scmd) { 1830 switch (scmd->cmnd[0]) { 1831 case READ_6: 1832 case READ_10: 1833 case READ_12: 1834 case WRITE_6: 1835 case WRITE_10: 1836 case WRITE_12: 1837 case GPCMD_READ_CD: 1838 case GPCMD_SEND_DVD_STRUCTURE: 1839 case GPCMD_SEND_CUE_SHEET: 1840 return 0; /* DMA is safe */ 1841 } 1842 } 1843 return -EOPNOTSUPP; /* use PIO instead */ 1844 } 1845 1846 /** 1847 * mv_bmdma_setup - Set up BMDMA transaction 1848 * @qc: queued command to prepare DMA for. 1849 * 1850 * LOCKING: 1851 * Inherited from caller. 1852 */ 1853 static void mv_bmdma_setup(struct ata_queued_cmd *qc) 1854 { 1855 struct ata_port *ap = qc->ap; 1856 void __iomem *port_mmio = mv_ap_base(ap); 1857 struct mv_port_priv *pp = ap->private_data; 1858 1859 mv_fill_sg(qc); 1860 1861 /* clear all DMA cmd bits */ 1862 writel(0, port_mmio + BMDMA_CMD); 1863 1864 /* load PRD table addr. */ 1865 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16, 1866 port_mmio + BMDMA_PRD_HIGH); 1867 writelfl(pp->sg_tbl_dma[qc->tag], 1868 port_mmio + BMDMA_PRD_LOW); 1869 1870 /* issue r/w command */ 1871 ap->ops->sff_exec_command(ap, &qc->tf); 1872 } 1873 1874 /** 1875 * mv_bmdma_start - Start a BMDMA transaction 1876 * @qc: queued command to start DMA on. 1877 * 1878 * LOCKING: 1879 * Inherited from caller. 1880 */ 1881 static void mv_bmdma_start(struct ata_queued_cmd *qc) 1882 { 1883 struct ata_port *ap = qc->ap; 1884 void __iomem *port_mmio = mv_ap_base(ap); 1885 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 1886 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START; 1887 1888 /* start host DMA transaction */ 1889 writelfl(cmd, port_mmio + BMDMA_CMD); 1890 } 1891 1892 /** 1893 * mv_bmdma_stop - Stop BMDMA transfer 1894 * @qc: queued command to stop DMA on. 1895 * 1896 * Clears the ATA_DMA_START flag in the bmdma control register 1897 * 1898 * LOCKING: 1899 * Inherited from caller. 1900 */ 1901 static void mv_bmdma_stop_ap(struct ata_port *ap) 1902 { 1903 void __iomem *port_mmio = mv_ap_base(ap); 1904 u32 cmd; 1905 1906 /* clear start/stop bit */ 1907 cmd = readl(port_mmio + BMDMA_CMD); 1908 if (cmd & ATA_DMA_START) { 1909 cmd &= ~ATA_DMA_START; 1910 writelfl(cmd, port_mmio + BMDMA_CMD); 1911 1912 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 1913 ata_sff_dma_pause(ap); 1914 } 1915 } 1916 1917 static void mv_bmdma_stop(struct ata_queued_cmd *qc) 1918 { 1919 mv_bmdma_stop_ap(qc->ap); 1920 } 1921 1922 /** 1923 * mv_bmdma_status - Read BMDMA status 1924 * @ap: port for which to retrieve DMA status. 1925 * 1926 * Read and return equivalent of the sff BMDMA status register. 1927 * 1928 * LOCKING: 1929 * Inherited from caller. 1930 */ 1931 static u8 mv_bmdma_status(struct ata_port *ap) 1932 { 1933 void __iomem *port_mmio = mv_ap_base(ap); 1934 u32 reg, status; 1935 1936 /* 1937 * Other bits are valid only if ATA_DMA_ACTIVE==0, 1938 * and the ATA_DMA_INTR bit doesn't exist. 1939 */ 1940 reg = readl(port_mmio + BMDMA_STATUS); 1941 if (reg & ATA_DMA_ACTIVE) 1942 status = ATA_DMA_ACTIVE; 1943 else if (reg & ATA_DMA_ERR) 1944 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR; 1945 else { 1946 /* 1947 * Just because DMA_ACTIVE is 0 (DMA completed), 1948 * this does _not_ mean the device is "done". 1949 * So we should not yet be signalling ATA_DMA_INTR 1950 * in some cases. Eg. DSM/TRIM, and perhaps others. 1951 */ 1952 mv_bmdma_stop_ap(ap); 1953 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY) 1954 status = 0; 1955 else 1956 status = ATA_DMA_INTR; 1957 } 1958 return status; 1959 } 1960 1961 static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc) 1962 { 1963 struct ata_taskfile *tf = &qc->tf; 1964 /* 1965 * Workaround for 88SX60x1 FEr SATA#24. 1966 * 1967 * Chip may corrupt WRITEs if multi_count >= 4kB. 1968 * Note that READs are unaffected. 1969 * 1970 * It's not clear if this errata really means "4K bytes", 1971 * or if it always happens for multi_count > 7 1972 * regardless of device sector_size. 1973 * 1974 * So, for safety, any write with multi_count > 7 1975 * gets converted here into a regular PIO write instead: 1976 */ 1977 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { 1978 if (qc->dev->multi_count > 7) { 1979 switch (tf->command) { 1980 case ATA_CMD_WRITE_MULTI: 1981 tf->command = ATA_CMD_PIO_WRITE; 1982 break; 1983 case ATA_CMD_WRITE_MULTI_FUA_EXT: 1984 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ 1985 /* fall through */ 1986 case ATA_CMD_WRITE_MULTI_EXT: 1987 tf->command = ATA_CMD_PIO_WRITE_EXT; 1988 break; 1989 } 1990 } 1991 } 1992 } 1993 1994 /** 1995 * mv_qc_prep - Host specific command preparation. 1996 * @qc: queued command to prepare 1997 * 1998 * This routine simply redirects to the general purpose routine 1999 * if command is not DMA. Else, it handles prep of the CRQB 2000 * (command request block), does some sanity checking, and calls 2001 * the SG load routine. 2002 * 2003 * LOCKING: 2004 * Inherited from caller. 2005 */ 2006 static void mv_qc_prep(struct ata_queued_cmd *qc) 2007 { 2008 struct ata_port *ap = qc->ap; 2009 struct mv_port_priv *pp = ap->private_data; 2010 __le16 *cw; 2011 struct ata_taskfile *tf = &qc->tf; 2012 u16 flags = 0; 2013 unsigned in_index; 2014 2015 switch (tf->protocol) { 2016 case ATA_PROT_DMA: 2017 if (tf->command == ATA_CMD_DSM) 2018 return; 2019 /* fall-thru */ 2020 case ATA_PROT_NCQ: 2021 break; /* continue below */ 2022 case ATA_PROT_PIO: 2023 mv_rw_multi_errata_sata24(qc); 2024 return; 2025 default: 2026 return; 2027 } 2028 2029 /* Fill in command request block 2030 */ 2031 if (!(tf->flags & ATA_TFLAG_WRITE)) 2032 flags |= CRQB_FLAG_READ; 2033 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 2034 flags |= qc->tag << CRQB_TAG_SHIFT; 2035 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 2036 2037 /* get current queue index from software */ 2038 in_index = pp->req_idx; 2039 2040 pp->crqb[in_index].sg_addr = 2041 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 2042 pp->crqb[in_index].sg_addr_hi = 2043 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 2044 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 2045 2046 cw = &pp->crqb[in_index].ata_cmd[0]; 2047 2048 /* Sadly, the CRQB cannot accomodate all registers--there are 2049 * only 11 bytes...so we must pick and choose required 2050 * registers based on the command. So, we drop feature and 2051 * hob_feature for [RW] DMA commands, but they are needed for 2052 * NCQ. NCQ will drop hob_nsect, which is not needed there 2053 * (nsect is used only for the tag; feat/hob_feat hold true nsect). 2054 */ 2055 switch (tf->command) { 2056 case ATA_CMD_READ: 2057 case ATA_CMD_READ_EXT: 2058 case ATA_CMD_WRITE: 2059 case ATA_CMD_WRITE_EXT: 2060 case ATA_CMD_WRITE_FUA_EXT: 2061 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 2062 break; 2063 case ATA_CMD_FPDMA_READ: 2064 case ATA_CMD_FPDMA_WRITE: 2065 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 2066 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 2067 break; 2068 default: 2069 /* The only other commands EDMA supports in non-queued and 2070 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 2071 * of which are defined/used by Linux. If we get here, this 2072 * driver needs work. 2073 * 2074 * FIXME: modify libata to give qc_prep a return value and 2075 * return error here. 2076 */ 2077 BUG_ON(tf->command); 2078 break; 2079 } 2080 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 2081 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 2082 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 2083 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 2084 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 2085 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 2086 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 2087 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 2088 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 2089 2090 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2091 return; 2092 mv_fill_sg(qc); 2093 } 2094 2095 /** 2096 * mv_qc_prep_iie - Host specific command preparation. 2097 * @qc: queued command to prepare 2098 * 2099 * This routine simply redirects to the general purpose routine 2100 * if command is not DMA. Else, it handles prep of the CRQB 2101 * (command request block), does some sanity checking, and calls 2102 * the SG load routine. 2103 * 2104 * LOCKING: 2105 * Inherited from caller. 2106 */ 2107 static void mv_qc_prep_iie(struct ata_queued_cmd *qc) 2108 { 2109 struct ata_port *ap = qc->ap; 2110 struct mv_port_priv *pp = ap->private_data; 2111 struct mv_crqb_iie *crqb; 2112 struct ata_taskfile *tf = &qc->tf; 2113 unsigned in_index; 2114 u32 flags = 0; 2115 2116 if ((tf->protocol != ATA_PROT_DMA) && 2117 (tf->protocol != ATA_PROT_NCQ)) 2118 return; 2119 if (tf->command == ATA_CMD_DSM) 2120 return; /* use bmdma for this */ 2121 2122 /* Fill in Gen IIE command request block */ 2123 if (!(tf->flags & ATA_TFLAG_WRITE)) 2124 flags |= CRQB_FLAG_READ; 2125 2126 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 2127 flags |= qc->tag << CRQB_TAG_SHIFT; 2128 flags |= qc->tag << CRQB_HOSTQ_SHIFT; 2129 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 2130 2131 /* get current queue index from software */ 2132 in_index = pp->req_idx; 2133 2134 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 2135 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 2136 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 2137 crqb->flags = cpu_to_le32(flags); 2138 2139 crqb->ata_cmd[0] = cpu_to_le32( 2140 (tf->command << 16) | 2141 (tf->feature << 24) 2142 ); 2143 crqb->ata_cmd[1] = cpu_to_le32( 2144 (tf->lbal << 0) | 2145 (tf->lbam << 8) | 2146 (tf->lbah << 16) | 2147 (tf->device << 24) 2148 ); 2149 crqb->ata_cmd[2] = cpu_to_le32( 2150 (tf->hob_lbal << 0) | 2151 (tf->hob_lbam << 8) | 2152 (tf->hob_lbah << 16) | 2153 (tf->hob_feature << 24) 2154 ); 2155 crqb->ata_cmd[3] = cpu_to_le32( 2156 (tf->nsect << 0) | 2157 (tf->hob_nsect << 8) 2158 ); 2159 2160 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2161 return; 2162 mv_fill_sg(qc); 2163 } 2164 2165 /** 2166 * mv_sff_check_status - fetch device status, if valid 2167 * @ap: ATA port to fetch status from 2168 * 2169 * When using command issue via mv_qc_issue_fis(), 2170 * the initial ATA_BUSY state does not show up in the 2171 * ATA status (shadow) register. This can confuse libata! 2172 * 2173 * So we have a hook here to fake ATA_BUSY for that situation, 2174 * until the first time a BUSY, DRQ, or ERR bit is seen. 2175 * 2176 * The rest of the time, it simply returns the ATA status register. 2177 */ 2178 static u8 mv_sff_check_status(struct ata_port *ap) 2179 { 2180 u8 stat = ioread8(ap->ioaddr.status_addr); 2181 struct mv_port_priv *pp = ap->private_data; 2182 2183 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { 2184 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) 2185 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; 2186 else 2187 stat = ATA_BUSY; 2188 } 2189 return stat; 2190 } 2191 2192 /** 2193 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register 2194 * @fis: fis to be sent 2195 * @nwords: number of 32-bit words in the fis 2196 */ 2197 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords) 2198 { 2199 void __iomem *port_mmio = mv_ap_base(ap); 2200 u32 ifctl, old_ifctl, ifstat; 2201 int i, timeout = 200, final_word = nwords - 1; 2202 2203 /* Initiate FIS transmission mode */ 2204 old_ifctl = readl(port_mmio + SATA_IFCTL); 2205 ifctl = 0x100 | (old_ifctl & 0xf); 2206 writelfl(ifctl, port_mmio + SATA_IFCTL); 2207 2208 /* Send all words of the FIS except for the final word */ 2209 for (i = 0; i < final_word; ++i) 2210 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS); 2211 2212 /* Flag end-of-transmission, and then send the final word */ 2213 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL); 2214 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS); 2215 2216 /* 2217 * Wait for FIS transmission to complete. 2218 * This typically takes just a single iteration. 2219 */ 2220 do { 2221 ifstat = readl(port_mmio + SATA_IFSTAT); 2222 } while (!(ifstat & 0x1000) && --timeout); 2223 2224 /* Restore original port configuration */ 2225 writelfl(old_ifctl, port_mmio + SATA_IFCTL); 2226 2227 /* See if it worked */ 2228 if ((ifstat & 0x3000) != 0x1000) { 2229 ata_port_printk(ap, KERN_WARNING, 2230 "%s transmission error, ifstat=%08x\n", 2231 __func__, ifstat); 2232 return AC_ERR_OTHER; 2233 } 2234 return 0; 2235 } 2236 2237 /** 2238 * mv_qc_issue_fis - Issue a command directly as a FIS 2239 * @qc: queued command to start 2240 * 2241 * Note that the ATA shadow registers are not updated 2242 * after command issue, so the device will appear "READY" 2243 * if polled, even while it is BUSY processing the command. 2244 * 2245 * So we use a status hook to fake ATA_BUSY until the drive changes state. 2246 * 2247 * Note: we don't get updated shadow regs on *completion* 2248 * of non-data commands. So avoid sending them via this function, 2249 * as they will appear to have completed immediately. 2250 * 2251 * GEN_IIE has special registers that we could get the result tf from, 2252 * but earlier chipsets do not. For now, we ignore those registers. 2253 */ 2254 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc) 2255 { 2256 struct ata_port *ap = qc->ap; 2257 struct mv_port_priv *pp = ap->private_data; 2258 struct ata_link *link = qc->dev->link; 2259 u32 fis[5]; 2260 int err = 0; 2261 2262 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); 2263 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis)); 2264 if (err) 2265 return err; 2266 2267 switch (qc->tf.protocol) { 2268 case ATAPI_PROT_PIO: 2269 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 2270 /* fall through */ 2271 case ATAPI_PROT_NODATA: 2272 ap->hsm_task_state = HSM_ST_FIRST; 2273 break; 2274 case ATA_PROT_PIO: 2275 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 2276 if (qc->tf.flags & ATA_TFLAG_WRITE) 2277 ap->hsm_task_state = HSM_ST_FIRST; 2278 else 2279 ap->hsm_task_state = HSM_ST; 2280 break; 2281 default: 2282 ap->hsm_task_state = HSM_ST_LAST; 2283 break; 2284 } 2285 2286 if (qc->tf.flags & ATA_TFLAG_POLLING) 2287 ata_sff_queue_pio_task(link, 0); 2288 return 0; 2289 } 2290 2291 /** 2292 * mv_qc_issue - Initiate a command to the host 2293 * @qc: queued command to start 2294 * 2295 * This routine simply redirects to the general purpose routine 2296 * if command is not DMA. Else, it sanity checks our local 2297 * caches of the request producer/consumer indices then enables 2298 * DMA and bumps the request producer index. 2299 * 2300 * LOCKING: 2301 * Inherited from caller. 2302 */ 2303 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 2304 { 2305 static int limit_warnings = 10; 2306 struct ata_port *ap = qc->ap; 2307 void __iomem *port_mmio = mv_ap_base(ap); 2308 struct mv_port_priv *pp = ap->private_data; 2309 u32 in_index; 2310 unsigned int port_irqs; 2311 2312 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ 2313 2314 switch (qc->tf.protocol) { 2315 case ATA_PROT_DMA: 2316 if (qc->tf.command == ATA_CMD_DSM) { 2317 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */ 2318 return AC_ERR_OTHER; 2319 break; /* use bmdma for this */ 2320 } 2321 /* fall thru */ 2322 case ATA_PROT_NCQ: 2323 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); 2324 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2325 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 2326 2327 /* Write the request in pointer to kick the EDMA to life */ 2328 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 2329 port_mmio + EDMA_REQ_Q_IN_PTR); 2330 return 0; 2331 2332 case ATA_PROT_PIO: 2333 /* 2334 * Errata SATA#16, SATA#24: warn if multiple DRQs expected. 2335 * 2336 * Someday, we might implement special polling workarounds 2337 * for these, but it all seems rather unnecessary since we 2338 * normally use only DMA for commands which transfer more 2339 * than a single block of data. 2340 * 2341 * Much of the time, this could just work regardless. 2342 * So for now, just log the incident, and allow the attempt. 2343 */ 2344 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { 2345 --limit_warnings; 2346 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME 2347 ": attempting PIO w/multiple DRQ: " 2348 "this may fail due to h/w errata\n"); 2349 } 2350 /* drop through */ 2351 case ATA_PROT_NODATA: 2352 case ATAPI_PROT_PIO: 2353 case ATAPI_PROT_NODATA: 2354 if (ap->flags & ATA_FLAG_PIO_POLLING) 2355 qc->tf.flags |= ATA_TFLAG_POLLING; 2356 break; 2357 } 2358 2359 if (qc->tf.flags & ATA_TFLAG_POLLING) 2360 port_irqs = ERR_IRQ; /* mask device interrupt when polling */ 2361 else 2362 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */ 2363 2364 /* 2365 * We're about to send a non-EDMA capable command to the 2366 * port. Turn off EDMA so there won't be problems accessing 2367 * shadow block, etc registers. 2368 */ 2369 mv_stop_edma(ap); 2370 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs); 2371 mv_pmp_select(ap, qc->dev->link->pmp); 2372 2373 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { 2374 struct mv_host_priv *hpriv = ap->host->private_data; 2375 /* 2376 * Workaround for 88SX60x1 FEr SATA#25 (part 2). 2377 * 2378 * After any NCQ error, the READ_LOG_EXT command 2379 * from libata-eh *must* use mv_qc_issue_fis(). 2380 * Otherwise it might fail, due to chip errata. 2381 * 2382 * Rather than special-case it, we'll just *always* 2383 * use this method here for READ_LOG_EXT, making for 2384 * easier testing. 2385 */ 2386 if (IS_GEN_II(hpriv)) 2387 return mv_qc_issue_fis(qc); 2388 } 2389 return ata_bmdma_qc_issue(qc); 2390 } 2391 2392 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 2393 { 2394 struct mv_port_priv *pp = ap->private_data; 2395 struct ata_queued_cmd *qc; 2396 2397 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 2398 return NULL; 2399 qc = ata_qc_from_tag(ap, ap->link.active_tag); 2400 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) 2401 return qc; 2402 return NULL; 2403 } 2404 2405 static void mv_pmp_error_handler(struct ata_port *ap) 2406 { 2407 unsigned int pmp, pmp_map; 2408 struct mv_port_priv *pp = ap->private_data; 2409 2410 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { 2411 /* 2412 * Perform NCQ error analysis on failed PMPs 2413 * before we freeze the port entirely. 2414 * 2415 * The failed PMPs are marked earlier by mv_pmp_eh_prep(). 2416 */ 2417 pmp_map = pp->delayed_eh_pmp_map; 2418 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; 2419 for (pmp = 0; pmp_map != 0; pmp++) { 2420 unsigned int this_pmp = (1 << pmp); 2421 if (pmp_map & this_pmp) { 2422 struct ata_link *link = &ap->pmp_link[pmp]; 2423 pmp_map &= ~this_pmp; 2424 ata_eh_analyze_ncq_error(link); 2425 } 2426 } 2427 ata_port_freeze(ap); 2428 } 2429 sata_pmp_error_handler(ap); 2430 } 2431 2432 static unsigned int mv_get_err_pmp_map(struct ata_port *ap) 2433 { 2434 void __iomem *port_mmio = mv_ap_base(ap); 2435 2436 return readl(port_mmio + SATA_TESTCTL) >> 16; 2437 } 2438 2439 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) 2440 { 2441 struct ata_eh_info *ehi; 2442 unsigned int pmp; 2443 2444 /* 2445 * Initialize EH info for PMPs which saw device errors 2446 */ 2447 ehi = &ap->link.eh_info; 2448 for (pmp = 0; pmp_map != 0; pmp++) { 2449 unsigned int this_pmp = (1 << pmp); 2450 if (pmp_map & this_pmp) { 2451 struct ata_link *link = &ap->pmp_link[pmp]; 2452 2453 pmp_map &= ~this_pmp; 2454 ehi = &link->eh_info; 2455 ata_ehi_clear_desc(ehi); 2456 ata_ehi_push_desc(ehi, "dev err"); 2457 ehi->err_mask |= AC_ERR_DEV; 2458 ehi->action |= ATA_EH_RESET; 2459 ata_link_abort(link); 2460 } 2461 } 2462 } 2463 2464 static int mv_req_q_empty(struct ata_port *ap) 2465 { 2466 void __iomem *port_mmio = mv_ap_base(ap); 2467 u32 in_ptr, out_ptr; 2468 2469 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR) 2470 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2471 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR) 2472 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2473 return (in_ptr == out_ptr); /* 1 == queue_is_empty */ 2474 } 2475 2476 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 2477 { 2478 struct mv_port_priv *pp = ap->private_data; 2479 int failed_links; 2480 unsigned int old_map, new_map; 2481 2482 /* 2483 * Device error during FBS+NCQ operation: 2484 * 2485 * Set a port flag to prevent further I/O being enqueued. 2486 * Leave the EDMA running to drain outstanding commands from this port. 2487 * Perform the post-mortem/EH only when all responses are complete. 2488 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). 2489 */ 2490 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { 2491 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; 2492 pp->delayed_eh_pmp_map = 0; 2493 } 2494 old_map = pp->delayed_eh_pmp_map; 2495 new_map = old_map | mv_get_err_pmp_map(ap); 2496 2497 if (old_map != new_map) { 2498 pp->delayed_eh_pmp_map = new_map; 2499 mv_pmp_eh_prep(ap, new_map & ~old_map); 2500 } 2501 failed_links = hweight16(new_map); 2502 2503 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x " 2504 "failed_links=%d nr_active_links=%d\n", 2505 __func__, pp->delayed_eh_pmp_map, 2506 ap->qc_active, failed_links, 2507 ap->nr_active_links); 2508 2509 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { 2510 mv_process_crpb_entries(ap, pp); 2511 mv_stop_edma(ap); 2512 mv_eh_freeze(ap); 2513 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__); 2514 return 1; /* handled */ 2515 } 2516 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__); 2517 return 1; /* handled */ 2518 } 2519 2520 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) 2521 { 2522 /* 2523 * Possible future enhancement: 2524 * 2525 * FBS+non-NCQ operation is not yet implemented. 2526 * See related notes in mv_edma_cfg(). 2527 * 2528 * Device error during FBS+non-NCQ operation: 2529 * 2530 * We need to snapshot the shadow registers for each failed command. 2531 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). 2532 */ 2533 return 0; /* not handled */ 2534 } 2535 2536 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) 2537 { 2538 struct mv_port_priv *pp = ap->private_data; 2539 2540 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 2541 return 0; /* EDMA was not active: not handled */ 2542 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) 2543 return 0; /* FBS was not active: not handled */ 2544 2545 if (!(edma_err_cause & EDMA_ERR_DEV)) 2546 return 0; /* non DEV error: not handled */ 2547 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; 2548 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) 2549 return 0; /* other problems: not handled */ 2550 2551 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 2552 /* 2553 * EDMA should NOT have self-disabled for this case. 2554 * If it did, then something is wrong elsewhere, 2555 * and we cannot handle it here. 2556 */ 2557 if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2558 ata_port_printk(ap, KERN_WARNING, 2559 "%s: err_cause=0x%x pp_flags=0x%x\n", 2560 __func__, edma_err_cause, pp->pp_flags); 2561 return 0; /* not handled */ 2562 } 2563 return mv_handle_fbs_ncq_dev_err(ap); 2564 } else { 2565 /* 2566 * EDMA should have self-disabled for this case. 2567 * If it did not, then something is wrong elsewhere, 2568 * and we cannot handle it here. 2569 */ 2570 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { 2571 ata_port_printk(ap, KERN_WARNING, 2572 "%s: err_cause=0x%x pp_flags=0x%x\n", 2573 __func__, edma_err_cause, pp->pp_flags); 2574 return 0; /* not handled */ 2575 } 2576 return mv_handle_fbs_non_ncq_dev_err(ap); 2577 } 2578 return 0; /* not handled */ 2579 } 2580 2581 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) 2582 { 2583 struct ata_eh_info *ehi = &ap->link.eh_info; 2584 char *when = "idle"; 2585 2586 ata_ehi_clear_desc(ehi); 2587 if (edma_was_enabled) { 2588 when = "EDMA enabled"; 2589 } else { 2590 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 2591 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 2592 when = "polling"; 2593 } 2594 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); 2595 ehi->err_mask |= AC_ERR_OTHER; 2596 ehi->action |= ATA_EH_RESET; 2597 ata_port_freeze(ap); 2598 } 2599 2600 /** 2601 * mv_err_intr - Handle error interrupts on the port 2602 * @ap: ATA channel to manipulate 2603 * 2604 * Most cases require a full reset of the chip's state machine, 2605 * which also performs a COMRESET. 2606 * Also, if the port disabled DMA, update our cached copy to match. 2607 * 2608 * LOCKING: 2609 * Inherited from caller. 2610 */ 2611 static void mv_err_intr(struct ata_port *ap) 2612 { 2613 void __iomem *port_mmio = mv_ap_base(ap); 2614 u32 edma_err_cause, eh_freeze_mask, serr = 0; 2615 u32 fis_cause = 0; 2616 struct mv_port_priv *pp = ap->private_data; 2617 struct mv_host_priv *hpriv = ap->host->private_data; 2618 unsigned int action = 0, err_mask = 0; 2619 struct ata_eh_info *ehi = &ap->link.eh_info; 2620 struct ata_queued_cmd *qc; 2621 int abort = 0; 2622 2623 /* 2624 * Read and clear the SError and err_cause bits. 2625 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear 2626 * the FIS_IRQ_CAUSE register before clearing edma_err_cause. 2627 */ 2628 sata_scr_read(&ap->link, SCR_ERROR, &serr); 2629 sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 2630 2631 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE); 2632 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2633 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE); 2634 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE); 2635 } 2636 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE); 2637 2638 if (edma_err_cause & EDMA_ERR_DEV) { 2639 /* 2640 * Device errors during FIS-based switching operation 2641 * require special handling. 2642 */ 2643 if (mv_handle_dev_err(ap, edma_err_cause)) 2644 return; 2645 } 2646 2647 qc = mv_get_active_qc(ap); 2648 ata_ehi_clear_desc(ehi); 2649 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 2650 edma_err_cause, pp->pp_flags); 2651 2652 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2653 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); 2654 if (fis_cause & FIS_IRQ_CAUSE_AN) { 2655 u32 ec = edma_err_cause & 2656 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); 2657 sata_async_notification(ap); 2658 if (!ec) 2659 return; /* Just an AN; no need for the nukes */ 2660 ata_ehi_push_desc(ehi, "SDB notify"); 2661 } 2662 } 2663 /* 2664 * All generations share these EDMA error cause bits: 2665 */ 2666 if (edma_err_cause & EDMA_ERR_DEV) { 2667 err_mask |= AC_ERR_DEV; 2668 action |= ATA_EH_RESET; 2669 ata_ehi_push_desc(ehi, "dev error"); 2670 } 2671 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 2672 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 2673 EDMA_ERR_INTRL_PAR)) { 2674 err_mask |= AC_ERR_ATA_BUS; 2675 action |= ATA_EH_RESET; 2676 ata_ehi_push_desc(ehi, "parity error"); 2677 } 2678 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 2679 ata_ehi_hotplugged(ehi); 2680 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 2681 "dev disconnect" : "dev connect"); 2682 action |= ATA_EH_RESET; 2683 } 2684 2685 /* 2686 * Gen-I has a different SELF_DIS bit, 2687 * different FREEZE bits, and no SERR bit: 2688 */ 2689 if (IS_GEN_I(hpriv)) { 2690 eh_freeze_mask = EDMA_EH_FREEZE_5; 2691 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 2692 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2693 ata_ehi_push_desc(ehi, "EDMA self-disable"); 2694 } 2695 } else { 2696 eh_freeze_mask = EDMA_EH_FREEZE; 2697 if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2698 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2699 ata_ehi_push_desc(ehi, "EDMA self-disable"); 2700 } 2701 if (edma_err_cause & EDMA_ERR_SERR) { 2702 ata_ehi_push_desc(ehi, "SError=%08x", serr); 2703 err_mask |= AC_ERR_ATA_BUS; 2704 action |= ATA_EH_RESET; 2705 } 2706 } 2707 2708 if (!err_mask) { 2709 err_mask = AC_ERR_OTHER; 2710 action |= ATA_EH_RESET; 2711 } 2712 2713 ehi->serror |= serr; 2714 ehi->action |= action; 2715 2716 if (qc) 2717 qc->err_mask |= err_mask; 2718 else 2719 ehi->err_mask |= err_mask; 2720 2721 if (err_mask == AC_ERR_DEV) { 2722 /* 2723 * Cannot do ata_port_freeze() here, 2724 * because it would kill PIO access, 2725 * which is needed for further diagnosis. 2726 */ 2727 mv_eh_freeze(ap); 2728 abort = 1; 2729 } else if (edma_err_cause & eh_freeze_mask) { 2730 /* 2731 * Note to self: ata_port_freeze() calls ata_port_abort() 2732 */ 2733 ata_port_freeze(ap); 2734 } else { 2735 abort = 1; 2736 } 2737 2738 if (abort) { 2739 if (qc) 2740 ata_link_abort(qc->dev->link); 2741 else 2742 ata_port_abort(ap); 2743 } 2744 } 2745 2746 static void mv_process_crpb_response(struct ata_port *ap, 2747 struct mv_crpb *response, unsigned int tag, int ncq_enabled) 2748 { 2749 u8 ata_status; 2750 u16 edma_status = le16_to_cpu(response->flags); 2751 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 2752 2753 if (unlikely(!qc)) { 2754 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 2755 __func__, tag); 2756 return; 2757 } 2758 2759 /* 2760 * edma_status from a response queue entry: 2761 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). 2762 * MSB is saved ATA status from command completion. 2763 */ 2764 if (!ncq_enabled) { 2765 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 2766 if (err_cause) { 2767 /* 2768 * Error will be seen/handled by 2769 * mv_err_intr(). So do nothing at all here. 2770 */ 2771 return; 2772 } 2773 } 2774 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 2775 if (!ac_err_mask(ata_status)) 2776 ata_qc_complete(qc); 2777 /* else: leave it for mv_err_intr() */ 2778 } 2779 2780 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 2781 { 2782 void __iomem *port_mmio = mv_ap_base(ap); 2783 struct mv_host_priv *hpriv = ap->host->private_data; 2784 u32 in_index; 2785 bool work_done = false; 2786 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 2787 2788 /* Get the hardware queue position index */ 2789 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR) 2790 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2791 2792 /* Process new responses from since the last time we looked */ 2793 while (in_index != pp->resp_idx) { 2794 unsigned int tag; 2795 struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 2796 2797 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2798 2799 if (IS_GEN_I(hpriv)) { 2800 /* 50xx: no NCQ, only one command active at a time */ 2801 tag = ap->link.active_tag; 2802 } else { 2803 /* Gen II/IIE: get command tag from CRPB entry */ 2804 tag = le16_to_cpu(response->id) & 0x1f; 2805 } 2806 mv_process_crpb_response(ap, response, tag, ncq_enabled); 2807 work_done = true; 2808 } 2809 2810 /* Update the software queue position index in hardware */ 2811 if (work_done) 2812 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 2813 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 2814 port_mmio + EDMA_RSP_Q_OUT_PTR); 2815 } 2816 2817 static void mv_port_intr(struct ata_port *ap, u32 port_cause) 2818 { 2819 struct mv_port_priv *pp; 2820 int edma_was_enabled; 2821 2822 /* 2823 * Grab a snapshot of the EDMA_EN flag setting, 2824 * so that we have a consistent view for this port, 2825 * even if something we call of our routines changes it. 2826 */ 2827 pp = ap->private_data; 2828 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2829 /* 2830 * Process completed CRPB response(s) before other events. 2831 */ 2832 if (edma_was_enabled && (port_cause & DONE_IRQ)) { 2833 mv_process_crpb_entries(ap, pp); 2834 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 2835 mv_handle_fbs_ncq_dev_err(ap); 2836 } 2837 /* 2838 * Handle chip-reported errors, or continue on to handle PIO. 2839 */ 2840 if (unlikely(port_cause & ERR_IRQ)) { 2841 mv_err_intr(ap); 2842 } else if (!edma_was_enabled) { 2843 struct ata_queued_cmd *qc = mv_get_active_qc(ap); 2844 if (qc) 2845 ata_bmdma_port_intr(ap, qc); 2846 else 2847 mv_unexpected_intr(ap, edma_was_enabled); 2848 } 2849 } 2850 2851 /** 2852 * mv_host_intr - Handle all interrupts on the given host controller 2853 * @host: host specific structure 2854 * @main_irq_cause: Main interrupt cause register for the chip. 2855 * 2856 * LOCKING: 2857 * Inherited from caller. 2858 */ 2859 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 2860 { 2861 struct mv_host_priv *hpriv = host->private_data; 2862 void __iomem *mmio = hpriv->base, *hc_mmio; 2863 unsigned int handled = 0, port; 2864 2865 /* If asserted, clear the "all ports" IRQ coalescing bit */ 2866 if (main_irq_cause & ALL_PORTS_COAL_DONE) 2867 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 2868 2869 for (port = 0; port < hpriv->n_ports; port++) { 2870 struct ata_port *ap = host->ports[port]; 2871 unsigned int p, shift, hardport, port_cause; 2872 2873 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2874 /* 2875 * Each hc within the host has its own hc_irq_cause register, 2876 * where the interrupting ports bits get ack'd. 2877 */ 2878 if (hardport == 0) { /* first port on this hc ? */ 2879 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; 2880 u32 port_mask, ack_irqs; 2881 /* 2882 * Skip this entire hc if nothing pending for any ports 2883 */ 2884 if (!hc_cause) { 2885 port += MV_PORTS_PER_HC - 1; 2886 continue; 2887 } 2888 /* 2889 * We don't need/want to read the hc_irq_cause register, 2890 * because doing so hurts performance, and 2891 * main_irq_cause already gives us everything we need. 2892 * 2893 * But we do have to *write* to the hc_irq_cause to ack 2894 * the ports that we are handling this time through. 2895 * 2896 * This requires that we create a bitmap for those 2897 * ports which interrupted us, and use that bitmap 2898 * to ack (only) those ports via hc_irq_cause. 2899 */ 2900 ack_irqs = 0; 2901 if (hc_cause & PORTS_0_3_COAL_DONE) 2902 ack_irqs = HC_COAL_IRQ; 2903 for (p = 0; p < MV_PORTS_PER_HC; ++p) { 2904 if ((port + p) >= hpriv->n_ports) 2905 break; 2906 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); 2907 if (hc_cause & port_mask) 2908 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; 2909 } 2910 hc_mmio = mv_hc_base_from_port(mmio, port); 2911 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE); 2912 handled = 1; 2913 } 2914 /* 2915 * Handle interrupts signalled for this port: 2916 */ 2917 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 2918 if (port_cause) 2919 mv_port_intr(ap, port_cause); 2920 } 2921 return handled; 2922 } 2923 2924 static int mv_pci_error(struct ata_host *host, void __iomem *mmio) 2925 { 2926 struct mv_host_priv *hpriv = host->private_data; 2927 struct ata_port *ap; 2928 struct ata_queued_cmd *qc; 2929 struct ata_eh_info *ehi; 2930 unsigned int i, err_mask, printed = 0; 2931 u32 err_cause; 2932 2933 err_cause = readl(mmio + hpriv->irq_cause_offset); 2934 2935 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 2936 err_cause); 2937 2938 DPRINTK("All regs @ PCI error\n"); 2939 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 2940 2941 writelfl(0, mmio + hpriv->irq_cause_offset); 2942 2943 for (i = 0; i < host->n_ports; i++) { 2944 ap = host->ports[i]; 2945 if (!ata_link_offline(&ap->link)) { 2946 ehi = &ap->link.eh_info; 2947 ata_ehi_clear_desc(ehi); 2948 if (!printed++) 2949 ata_ehi_push_desc(ehi, 2950 "PCI err cause 0x%08x", err_cause); 2951 err_mask = AC_ERR_HOST_BUS; 2952 ehi->action = ATA_EH_RESET; 2953 qc = ata_qc_from_tag(ap, ap->link.active_tag); 2954 if (qc) 2955 qc->err_mask |= err_mask; 2956 else 2957 ehi->err_mask |= err_mask; 2958 2959 ata_port_freeze(ap); 2960 } 2961 } 2962 return 1; /* handled */ 2963 } 2964 2965 /** 2966 * mv_interrupt - Main interrupt event handler 2967 * @irq: unused 2968 * @dev_instance: private data; in this case the host structure 2969 * 2970 * Read the read only register to determine if any host 2971 * controllers have pending interrupts. If so, call lower level 2972 * routine to handle. Also check for PCI errors which are only 2973 * reported here. 2974 * 2975 * LOCKING: 2976 * This routine holds the host lock while processing pending 2977 * interrupts. 2978 */ 2979 static irqreturn_t mv_interrupt(int irq, void *dev_instance) 2980 { 2981 struct ata_host *host = dev_instance; 2982 struct mv_host_priv *hpriv = host->private_data; 2983 unsigned int handled = 0; 2984 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; 2985 u32 main_irq_cause, pending_irqs; 2986 2987 spin_lock(&host->lock); 2988 2989 /* for MSI: block new interrupts while in here */ 2990 if (using_msi) 2991 mv_write_main_irq_mask(0, hpriv); 2992 2993 main_irq_cause = readl(hpriv->main_irq_cause_addr); 2994 pending_irqs = main_irq_cause & hpriv->main_irq_mask; 2995 /* 2996 * Deal with cases where we either have nothing pending, or have read 2997 * a bogus register value which can indicate HW removal or PCI fault. 2998 */ 2999 if (pending_irqs && main_irq_cause != 0xffffffffU) { 3000 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) 3001 handled = mv_pci_error(host, hpriv->base); 3002 else 3003 handled = mv_host_intr(host, pending_irqs); 3004 } 3005 3006 /* for MSI: unmask; interrupt cause bits will retrigger now */ 3007 if (using_msi) 3008 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); 3009 3010 spin_unlock(&host->lock); 3011 3012 return IRQ_RETVAL(handled); 3013 } 3014 3015 static unsigned int mv5_scr_offset(unsigned int sc_reg_in) 3016 { 3017 unsigned int ofs; 3018 3019 switch (sc_reg_in) { 3020 case SCR_STATUS: 3021 case SCR_ERROR: 3022 case SCR_CONTROL: 3023 ofs = sc_reg_in * sizeof(u32); 3024 break; 3025 default: 3026 ofs = 0xffffffffU; 3027 break; 3028 } 3029 return ofs; 3030 } 3031 3032 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 3033 { 3034 struct mv_host_priv *hpriv = link->ap->host->private_data; 3035 void __iomem *mmio = hpriv->base; 3036 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 3037 unsigned int ofs = mv5_scr_offset(sc_reg_in); 3038 3039 if (ofs != 0xffffffffU) { 3040 *val = readl(addr + ofs); 3041 return 0; 3042 } else 3043 return -EINVAL; 3044 } 3045 3046 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 3047 { 3048 struct mv_host_priv *hpriv = link->ap->host->private_data; 3049 void __iomem *mmio = hpriv->base; 3050 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 3051 unsigned int ofs = mv5_scr_offset(sc_reg_in); 3052 3053 if (ofs != 0xffffffffU) { 3054 writelfl(val, addr + ofs); 3055 return 0; 3056 } else 3057 return -EINVAL; 3058 } 3059 3060 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 3061 { 3062 struct pci_dev *pdev = to_pci_dev(host->dev); 3063 int early_5080; 3064 3065 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 3066 3067 if (!early_5080) { 3068 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3069 tmp |= (1 << 0); 3070 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3071 } 3072 3073 mv_reset_pci_bus(host, mmio); 3074 } 3075 3076 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3077 { 3078 writel(0x0fcfffff, mmio + FLASH_CTL); 3079 } 3080 3081 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 3082 void __iomem *mmio) 3083 { 3084 void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 3085 u32 tmp; 3086 3087 tmp = readl(phy_mmio + MV5_PHY_MODE); 3088 3089 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 3090 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 3091 } 3092 3093 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3094 { 3095 u32 tmp; 3096 3097 writel(0, mmio + GPIO_PORT_CTL); 3098 3099 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 3100 3101 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3102 tmp |= ~(1 << 0); 3103 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3104 } 3105 3106 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 3107 unsigned int port) 3108 { 3109 void __iomem *phy_mmio = mv5_phy_base(mmio, port); 3110 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 3111 u32 tmp; 3112 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 3113 3114 if (fix_apm_sq) { 3115 tmp = readl(phy_mmio + MV5_LTMODE); 3116 tmp |= (1 << 19); 3117 writel(tmp, phy_mmio + MV5_LTMODE); 3118 3119 tmp = readl(phy_mmio + MV5_PHY_CTL); 3120 tmp &= ~0x3; 3121 tmp |= 0x1; 3122 writel(tmp, phy_mmio + MV5_PHY_CTL); 3123 } 3124 3125 tmp = readl(phy_mmio + MV5_PHY_MODE); 3126 tmp &= ~mask; 3127 tmp |= hpriv->signal[port].pre; 3128 tmp |= hpriv->signal[port].amps; 3129 writel(tmp, phy_mmio + MV5_PHY_MODE); 3130 } 3131 3132 3133 #undef ZERO 3134 #define ZERO(reg) writel(0, port_mmio + (reg)) 3135 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 3136 unsigned int port) 3137 { 3138 void __iomem *port_mmio = mv_port_base(mmio, port); 3139 3140 mv_reset_channel(hpriv, mmio, port); 3141 3142 ZERO(0x028); /* command */ 3143 writel(0x11f, port_mmio + EDMA_CFG); 3144 ZERO(0x004); /* timer */ 3145 ZERO(0x008); /* irq err cause */ 3146 ZERO(0x00c); /* irq err mask */ 3147 ZERO(0x010); /* rq bah */ 3148 ZERO(0x014); /* rq inp */ 3149 ZERO(0x018); /* rq outp */ 3150 ZERO(0x01c); /* respq bah */ 3151 ZERO(0x024); /* respq outp */ 3152 ZERO(0x020); /* respq inp */ 3153 ZERO(0x02c); /* test control */ 3154 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 3155 } 3156 #undef ZERO 3157 3158 #define ZERO(reg) writel(0, hc_mmio + (reg)) 3159 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3160 unsigned int hc) 3161 { 3162 void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3163 u32 tmp; 3164 3165 ZERO(0x00c); 3166 ZERO(0x010); 3167 ZERO(0x014); 3168 ZERO(0x018); 3169 3170 tmp = readl(hc_mmio + 0x20); 3171 tmp &= 0x1c1c1c1c; 3172 tmp |= 0x03030303; 3173 writel(tmp, hc_mmio + 0x20); 3174 } 3175 #undef ZERO 3176 3177 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3178 unsigned int n_hc) 3179 { 3180 unsigned int hc, port; 3181 3182 for (hc = 0; hc < n_hc; hc++) { 3183 for (port = 0; port < MV_PORTS_PER_HC; port++) 3184 mv5_reset_hc_port(hpriv, mmio, 3185 (hc * MV_PORTS_PER_HC) + port); 3186 3187 mv5_reset_one_hc(hpriv, mmio, hc); 3188 } 3189 3190 return 0; 3191 } 3192 3193 #undef ZERO 3194 #define ZERO(reg) writel(0, mmio + (reg)) 3195 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 3196 { 3197 struct mv_host_priv *hpriv = host->private_data; 3198 u32 tmp; 3199 3200 tmp = readl(mmio + MV_PCI_MODE); 3201 tmp &= 0xff00ffff; 3202 writel(tmp, mmio + MV_PCI_MODE); 3203 3204 ZERO(MV_PCI_DISC_TIMER); 3205 ZERO(MV_PCI_MSI_TRIGGER); 3206 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 3207 ZERO(MV_PCI_SERR_MASK); 3208 ZERO(hpriv->irq_cause_offset); 3209 ZERO(hpriv->irq_mask_offset); 3210 ZERO(MV_PCI_ERR_LOW_ADDRESS); 3211 ZERO(MV_PCI_ERR_HIGH_ADDRESS); 3212 ZERO(MV_PCI_ERR_ATTRIBUTE); 3213 ZERO(MV_PCI_ERR_COMMAND); 3214 } 3215 #undef ZERO 3216 3217 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3218 { 3219 u32 tmp; 3220 3221 mv5_reset_flash(hpriv, mmio); 3222 3223 tmp = readl(mmio + GPIO_PORT_CTL); 3224 tmp &= 0x3; 3225 tmp |= (1 << 5) | (1 << 6); 3226 writel(tmp, mmio + GPIO_PORT_CTL); 3227 } 3228 3229 /** 3230 * mv6_reset_hc - Perform the 6xxx global soft reset 3231 * @mmio: base address of the HBA 3232 * 3233 * This routine only applies to 6xxx parts. 3234 * 3235 * LOCKING: 3236 * Inherited from caller. 3237 */ 3238 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3239 unsigned int n_hc) 3240 { 3241 void __iomem *reg = mmio + PCI_MAIN_CMD_STS; 3242 int i, rc = 0; 3243 u32 t; 3244 3245 /* Following procedure defined in PCI "main command and status 3246 * register" table. 3247 */ 3248 t = readl(reg); 3249 writel(t | STOP_PCI_MASTER, reg); 3250 3251 for (i = 0; i < 1000; i++) { 3252 udelay(1); 3253 t = readl(reg); 3254 if (PCI_MASTER_EMPTY & t) 3255 break; 3256 } 3257 if (!(PCI_MASTER_EMPTY & t)) { 3258 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 3259 rc = 1; 3260 goto done; 3261 } 3262 3263 /* set reset */ 3264 i = 5; 3265 do { 3266 writel(t | GLOB_SFT_RST, reg); 3267 t = readl(reg); 3268 udelay(1); 3269 } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 3270 3271 if (!(GLOB_SFT_RST & t)) { 3272 printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 3273 rc = 1; 3274 goto done; 3275 } 3276 3277 /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 3278 i = 5; 3279 do { 3280 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 3281 t = readl(reg); 3282 udelay(1); 3283 } while ((GLOB_SFT_RST & t) && (i-- > 0)); 3284 3285 if (GLOB_SFT_RST & t) { 3286 printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 3287 rc = 1; 3288 } 3289 done: 3290 return rc; 3291 } 3292 3293 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 3294 void __iomem *mmio) 3295 { 3296 void __iomem *port_mmio; 3297 u32 tmp; 3298 3299 tmp = readl(mmio + RESET_CFG); 3300 if ((tmp & (1 << 0)) == 0) { 3301 hpriv->signal[idx].amps = 0x7 << 8; 3302 hpriv->signal[idx].pre = 0x1 << 5; 3303 return; 3304 } 3305 3306 port_mmio = mv_port_base(mmio, idx); 3307 tmp = readl(port_mmio + PHY_MODE2); 3308 3309 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3310 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3311 } 3312 3313 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3314 { 3315 writel(0x00000060, mmio + GPIO_PORT_CTL); 3316 } 3317 3318 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 3319 unsigned int port) 3320 { 3321 void __iomem *port_mmio = mv_port_base(mmio, port); 3322 3323 u32 hp_flags = hpriv->hp_flags; 3324 int fix_phy_mode2 = 3325 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 3326 int fix_phy_mode4 = 3327 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 3328 u32 m2, m3; 3329 3330 if (fix_phy_mode2) { 3331 m2 = readl(port_mmio + PHY_MODE2); 3332 m2 &= ~(1 << 16); 3333 m2 |= (1 << 31); 3334 writel(m2, port_mmio + PHY_MODE2); 3335 3336 udelay(200); 3337 3338 m2 = readl(port_mmio + PHY_MODE2); 3339 m2 &= ~((1 << 16) | (1 << 31)); 3340 writel(m2, port_mmio + PHY_MODE2); 3341 3342 udelay(200); 3343 } 3344 3345 /* 3346 * Gen-II/IIe PHY_MODE3 errata RM#2: 3347 * Achieves better receiver noise performance than the h/w default: 3348 */ 3349 m3 = readl(port_mmio + PHY_MODE3); 3350 m3 = (m3 & 0x1f) | (0x5555601 << 5); 3351 3352 /* Guideline 88F5182 (GL# SATA-S11) */ 3353 if (IS_SOC(hpriv)) 3354 m3 &= ~0x1c; 3355 3356 if (fix_phy_mode4) { 3357 u32 m4 = readl(port_mmio + PHY_MODE4); 3358 /* 3359 * Enforce reserved-bit restrictions on GenIIe devices only. 3360 * For earlier chipsets, force only the internal config field 3361 * (workaround for errata FEr SATA#10 part 1). 3362 */ 3363 if (IS_GEN_IIE(hpriv)) 3364 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; 3365 else 3366 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; 3367 writel(m4, port_mmio + PHY_MODE4); 3368 } 3369 /* 3370 * Workaround for 60x1-B2 errata SATA#13: 3371 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, 3372 * so we must always rewrite PHY_MODE3 after PHY_MODE4. 3373 * Or ensure we use writelfl() when writing PHY_MODE4. 3374 */ 3375 writel(m3, port_mmio + PHY_MODE3); 3376 3377 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3378 m2 = readl(port_mmio + PHY_MODE2); 3379 3380 m2 &= ~MV_M2_PREAMP_MASK; 3381 m2 |= hpriv->signal[port].amps; 3382 m2 |= hpriv->signal[port].pre; 3383 m2 &= ~(1 << 16); 3384 3385 /* according to mvSata 3.6.1, some IIE values are fixed */ 3386 if (IS_GEN_IIE(hpriv)) { 3387 m2 &= ~0xC30FF01F; 3388 m2 |= 0x0000900F; 3389 } 3390 3391 writel(m2, port_mmio + PHY_MODE2); 3392 } 3393 3394 /* TODO: use the generic LED interface to configure the SATA Presence */ 3395 /* & Acitivy LEDs on the board */ 3396 static void mv_soc_enable_leds(struct mv_host_priv *hpriv, 3397 void __iomem *mmio) 3398 { 3399 return; 3400 } 3401 3402 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 3403 void __iomem *mmio) 3404 { 3405 void __iomem *port_mmio; 3406 u32 tmp; 3407 3408 port_mmio = mv_port_base(mmio, idx); 3409 tmp = readl(port_mmio + PHY_MODE2); 3410 3411 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3412 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3413 } 3414 3415 #undef ZERO 3416 #define ZERO(reg) writel(0, port_mmio + (reg)) 3417 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 3418 void __iomem *mmio, unsigned int port) 3419 { 3420 void __iomem *port_mmio = mv_port_base(mmio, port); 3421 3422 mv_reset_channel(hpriv, mmio, port); 3423 3424 ZERO(0x028); /* command */ 3425 writel(0x101f, port_mmio + EDMA_CFG); 3426 ZERO(0x004); /* timer */ 3427 ZERO(0x008); /* irq err cause */ 3428 ZERO(0x00c); /* irq err mask */ 3429 ZERO(0x010); /* rq bah */ 3430 ZERO(0x014); /* rq inp */ 3431 ZERO(0x018); /* rq outp */ 3432 ZERO(0x01c); /* respq bah */ 3433 ZERO(0x024); /* respq outp */ 3434 ZERO(0x020); /* respq inp */ 3435 ZERO(0x02c); /* test control */ 3436 writel(0x800, port_mmio + EDMA_IORDY_TMOUT); 3437 } 3438 3439 #undef ZERO 3440 3441 #define ZERO(reg) writel(0, hc_mmio + (reg)) 3442 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 3443 void __iomem *mmio) 3444 { 3445 void __iomem *hc_mmio = mv_hc_base(mmio, 0); 3446 3447 ZERO(0x00c); 3448 ZERO(0x010); 3449 ZERO(0x014); 3450 3451 } 3452 3453 #undef ZERO 3454 3455 static int mv_soc_reset_hc(struct mv_host_priv *hpriv, 3456 void __iomem *mmio, unsigned int n_hc) 3457 { 3458 unsigned int port; 3459 3460 for (port = 0; port < hpriv->n_ports; port++) 3461 mv_soc_reset_hc_port(hpriv, mmio, port); 3462 3463 mv_soc_reset_one_hc(hpriv, mmio); 3464 3465 return 0; 3466 } 3467 3468 static void mv_soc_reset_flash(struct mv_host_priv *hpriv, 3469 void __iomem *mmio) 3470 { 3471 return; 3472 } 3473 3474 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 3475 { 3476 return; 3477 } 3478 3479 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, 3480 void __iomem *mmio, unsigned int port) 3481 { 3482 void __iomem *port_mmio = mv_port_base(mmio, port); 3483 u32 reg; 3484 3485 reg = readl(port_mmio + PHY_MODE3); 3486 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */ 3487 reg |= (0x1 << 27); 3488 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */ 3489 reg |= (0x1 << 29); 3490 writel(reg, port_mmio + PHY_MODE3); 3491 3492 reg = readl(port_mmio + PHY_MODE4); 3493 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */ 3494 reg |= (0x1 << 16); 3495 writel(reg, port_mmio + PHY_MODE4); 3496 3497 reg = readl(port_mmio + PHY_MODE9_GEN2); 3498 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ 3499 reg |= 0x8; 3500 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ 3501 writel(reg, port_mmio + PHY_MODE9_GEN2); 3502 3503 reg = readl(port_mmio + PHY_MODE9_GEN1); 3504 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ 3505 reg |= 0x8; 3506 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ 3507 writel(reg, port_mmio + PHY_MODE9_GEN1); 3508 } 3509 3510 /** 3511 * soc_is_65 - check if the soc is 65 nano device 3512 * 3513 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS 3514 * register, this register should contain non-zero value and it exists only 3515 * in the 65 nano devices, when reading it from older devices we get 0. 3516 */ 3517 static bool soc_is_65n(struct mv_host_priv *hpriv) 3518 { 3519 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); 3520 3521 if (readl(port0_mmio + PHYCFG_OFS)) 3522 return true; 3523 return false; 3524 } 3525 3526 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 3527 { 3528 u32 ifcfg = readl(port_mmio + SATA_IFCFG); 3529 3530 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 3531 if (want_gen2i) 3532 ifcfg |= (1 << 7); /* enable gen2i speed */ 3533 writelfl(ifcfg, port_mmio + SATA_IFCFG); 3534 } 3535 3536 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 3537 unsigned int port_no) 3538 { 3539 void __iomem *port_mmio = mv_port_base(mmio, port_no); 3540 3541 /* 3542 * The datasheet warns against setting EDMA_RESET when EDMA is active 3543 * (but doesn't say what the problem might be). So we first try 3544 * to disable the EDMA engine before doing the EDMA_RESET operation. 3545 */ 3546 mv_stop_edma_engine(port_mmio); 3547 writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3548 3549 if (!IS_GEN_I(hpriv)) { 3550 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 3551 mv_setup_ifcfg(port_mmio, 1); 3552 } 3553 /* 3554 * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 3555 * link, and physical layers. It resets all SATA interface registers 3556 * (except for SATA_IFCFG), and issues a COMRESET to the dev. 3557 */ 3558 writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3559 udelay(25); /* allow reset propagation */ 3560 writelfl(0, port_mmio + EDMA_CMD); 3561 3562 hpriv->ops->phy_errata(hpriv, mmio, port_no); 3563 3564 if (IS_GEN_I(hpriv)) 3565 mdelay(1); 3566 } 3567 3568 static void mv_pmp_select(struct ata_port *ap, int pmp) 3569 { 3570 if (sata_pmp_supported(ap)) { 3571 void __iomem *port_mmio = mv_ap_base(ap); 3572 u32 reg = readl(port_mmio + SATA_IFCTL); 3573 int old = reg & 0xf; 3574 3575 if (old != pmp) { 3576 reg = (reg & ~0xf) | pmp; 3577 writelfl(reg, port_mmio + SATA_IFCTL); 3578 } 3579 } 3580 } 3581 3582 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 3583 unsigned long deadline) 3584 { 3585 mv_pmp_select(link->ap, sata_srst_pmp(link)); 3586 return sata_std_hardreset(link, class, deadline); 3587 } 3588 3589 static int mv_softreset(struct ata_link *link, unsigned int *class, 3590 unsigned long deadline) 3591 { 3592 mv_pmp_select(link->ap, sata_srst_pmp(link)); 3593 return ata_sff_softreset(link, class, deadline); 3594 } 3595 3596 static int mv_hardreset(struct ata_link *link, unsigned int *class, 3597 unsigned long deadline) 3598 { 3599 struct ata_port *ap = link->ap; 3600 struct mv_host_priv *hpriv = ap->host->private_data; 3601 struct mv_port_priv *pp = ap->private_data; 3602 void __iomem *mmio = hpriv->base; 3603 int rc, attempts = 0, extra = 0; 3604 u32 sstatus; 3605 bool online; 3606 3607 mv_reset_channel(hpriv, mmio, ap->port_no); 3608 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 3609 pp->pp_flags &= 3610 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 3611 3612 /* Workaround for errata FEr SATA#10 (part 2) */ 3613 do { 3614 const unsigned long *timing = 3615 sata_ehc_deb_timing(&link->eh_context); 3616 3617 rc = sata_link_hardreset(link, timing, deadline + extra, 3618 &online, NULL); 3619 rc = online ? -EAGAIN : rc; 3620 if (rc) 3621 return rc; 3622 sata_scr_read(link, SCR_STATUS, &sstatus); 3623 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 3624 /* Force 1.5gb/s link speed and try again */ 3625 mv_setup_ifcfg(mv_ap_base(ap), 0); 3626 if (time_after(jiffies + HZ, deadline)) 3627 extra = HZ; /* only extend it once, max */ 3628 } 3629 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 3630 mv_save_cached_regs(ap); 3631 mv_edma_cfg(ap, 0, 0); 3632 3633 return rc; 3634 } 3635 3636 static void mv_eh_freeze(struct ata_port *ap) 3637 { 3638 mv_stop_edma(ap); 3639 mv_enable_port_irqs(ap, 0); 3640 } 3641 3642 static void mv_eh_thaw(struct ata_port *ap) 3643 { 3644 struct mv_host_priv *hpriv = ap->host->private_data; 3645 unsigned int port = ap->port_no; 3646 unsigned int hardport = mv_hardport_from_port(port); 3647 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 3648 void __iomem *port_mmio = mv_ap_base(ap); 3649 u32 hc_irq_cause; 3650 3651 /* clear EDMA errors on this port */ 3652 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 3653 3654 /* clear pending irq events */ 3655 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 3656 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 3657 3658 mv_enable_port_irqs(ap, ERR_IRQ); 3659 } 3660 3661 /** 3662 * mv_port_init - Perform some early initialization on a single port. 3663 * @port: libata data structure storing shadow register addresses 3664 * @port_mmio: base address of the port 3665 * 3666 * Initialize shadow register mmio addresses, clear outstanding 3667 * interrupts on the port, and unmask interrupts for the future 3668 * start of the port. 3669 * 3670 * LOCKING: 3671 * Inherited from caller. 3672 */ 3673 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 3674 { 3675 void __iomem *serr, *shd_base = port_mmio + SHD_BLK; 3676 3677 /* PIO related setup 3678 */ 3679 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 3680 port->error_addr = 3681 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 3682 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 3683 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 3684 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 3685 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 3686 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 3687 port->status_addr = 3688 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 3689 /* special case: control/altstatus doesn't have ATA_REG_ address */ 3690 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; 3691 3692 /* Clear any currently outstanding port interrupt conditions */ 3693 serr = port_mmio + mv_scr_offset(SCR_ERROR); 3694 writelfl(readl(serr), serr); 3695 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 3696 3697 /* unmask all non-transient EDMA error interrupts */ 3698 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK); 3699 3700 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 3701 readl(port_mmio + EDMA_CFG), 3702 readl(port_mmio + EDMA_ERR_IRQ_CAUSE), 3703 readl(port_mmio + EDMA_ERR_IRQ_MASK)); 3704 } 3705 3706 static unsigned int mv_in_pcix_mode(struct ata_host *host) 3707 { 3708 struct mv_host_priv *hpriv = host->private_data; 3709 void __iomem *mmio = hpriv->base; 3710 u32 reg; 3711 3712 if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) 3713 return 0; /* not PCI-X capable */ 3714 reg = readl(mmio + MV_PCI_MODE); 3715 if ((reg & MV_PCI_MODE_MASK) == 0) 3716 return 0; /* conventional PCI mode */ 3717 return 1; /* chip is in PCI-X mode */ 3718 } 3719 3720 static int mv_pci_cut_through_okay(struct ata_host *host) 3721 { 3722 struct mv_host_priv *hpriv = host->private_data; 3723 void __iomem *mmio = hpriv->base; 3724 u32 reg; 3725 3726 if (!mv_in_pcix_mode(host)) { 3727 reg = readl(mmio + MV_PCI_COMMAND); 3728 if (reg & MV_PCI_COMMAND_MRDTRIG) 3729 return 0; /* not okay */ 3730 } 3731 return 1; /* okay */ 3732 } 3733 3734 static void mv_60x1b2_errata_pci7(struct ata_host *host) 3735 { 3736 struct mv_host_priv *hpriv = host->private_data; 3737 void __iomem *mmio = hpriv->base; 3738 3739 /* workaround for 60x1-B2 errata PCI#7 */ 3740 if (mv_in_pcix_mode(host)) { 3741 u32 reg = readl(mmio + MV_PCI_COMMAND); 3742 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND); 3743 } 3744 } 3745 3746 static int mv_chip_id(struct ata_host *host, unsigned int board_idx) 3747 { 3748 struct pci_dev *pdev = to_pci_dev(host->dev); 3749 struct mv_host_priv *hpriv = host->private_data; 3750 u32 hp_flags = hpriv->hp_flags; 3751 3752 switch (board_idx) { 3753 case chip_5080: 3754 hpriv->ops = &mv5xxx_ops; 3755 hp_flags |= MV_HP_GEN_I; 3756 3757 switch (pdev->revision) { 3758 case 0x1: 3759 hp_flags |= MV_HP_ERRATA_50XXB0; 3760 break; 3761 case 0x3: 3762 hp_flags |= MV_HP_ERRATA_50XXB2; 3763 break; 3764 default: 3765 dev_printk(KERN_WARNING, &pdev->dev, 3766 "Applying 50XXB2 workarounds to unknown rev\n"); 3767 hp_flags |= MV_HP_ERRATA_50XXB2; 3768 break; 3769 } 3770 break; 3771 3772 case chip_504x: 3773 case chip_508x: 3774 hpriv->ops = &mv5xxx_ops; 3775 hp_flags |= MV_HP_GEN_I; 3776 3777 switch (pdev->revision) { 3778 case 0x0: 3779 hp_flags |= MV_HP_ERRATA_50XXB0; 3780 break; 3781 case 0x3: 3782 hp_flags |= MV_HP_ERRATA_50XXB2; 3783 break; 3784 default: 3785 dev_printk(KERN_WARNING, &pdev->dev, 3786 "Applying B2 workarounds to unknown rev\n"); 3787 hp_flags |= MV_HP_ERRATA_50XXB2; 3788 break; 3789 } 3790 break; 3791 3792 case chip_604x: 3793 case chip_608x: 3794 hpriv->ops = &mv6xxx_ops; 3795 hp_flags |= MV_HP_GEN_II; 3796 3797 switch (pdev->revision) { 3798 case 0x7: 3799 mv_60x1b2_errata_pci7(host); 3800 hp_flags |= MV_HP_ERRATA_60X1B2; 3801 break; 3802 case 0x9: 3803 hp_flags |= MV_HP_ERRATA_60X1C0; 3804 break; 3805 default: 3806 dev_printk(KERN_WARNING, &pdev->dev, 3807 "Applying B2 workarounds to unknown rev\n"); 3808 hp_flags |= MV_HP_ERRATA_60X1B2; 3809 break; 3810 } 3811 break; 3812 3813 case chip_7042: 3814 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 3815 if (pdev->vendor == PCI_VENDOR_ID_TTI && 3816 (pdev->device == 0x2300 || pdev->device == 0x2310)) 3817 { 3818 /* 3819 * Highpoint RocketRAID PCIe 23xx series cards: 3820 * 3821 * Unconfigured drives are treated as "Legacy" 3822 * by the BIOS, and it overwrites sector 8 with 3823 * a "Lgcy" metadata block prior to Linux boot. 3824 * 3825 * Configured drives (RAID or JBOD) leave sector 8 3826 * alone, but instead overwrite a high numbered 3827 * sector for the RAID metadata. This sector can 3828 * be determined exactly, by truncating the physical 3829 * drive capacity to a nice even GB value. 3830 * 3831 * RAID metadata is at: (dev->n_sectors & ~0xfffff) 3832 * 3833 * Warn the user, lest they think we're just buggy. 3834 */ 3835 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 3836 " BIOS CORRUPTS DATA on all attached drives," 3837 " regardless of if/how they are configured." 3838 " BEWARE!\n"); 3839 printk(KERN_WARNING DRV_NAME ": For data safety, do not" 3840 " use sectors 8-9 on \"Legacy\" drives," 3841 " and avoid the final two gigabytes on" 3842 " all RocketRAID BIOS initialized drives.\n"); 3843 } 3844 /* drop through */ 3845 case chip_6042: 3846 hpriv->ops = &mv6xxx_ops; 3847 hp_flags |= MV_HP_GEN_IIE; 3848 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 3849 hp_flags |= MV_HP_CUT_THROUGH; 3850 3851 switch (pdev->revision) { 3852 case 0x2: /* Rev.B0: the first/only public release */ 3853 hp_flags |= MV_HP_ERRATA_60X1C0; 3854 break; 3855 default: 3856 dev_printk(KERN_WARNING, &pdev->dev, 3857 "Applying 60X1C0 workarounds to unknown rev\n"); 3858 hp_flags |= MV_HP_ERRATA_60X1C0; 3859 break; 3860 } 3861 break; 3862 case chip_soc: 3863 if (soc_is_65n(hpriv)) 3864 hpriv->ops = &mv_soc_65n_ops; 3865 else 3866 hpriv->ops = &mv_soc_ops; 3867 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | 3868 MV_HP_ERRATA_60X1C0; 3869 break; 3870 3871 default: 3872 dev_printk(KERN_ERR, host->dev, 3873 "BUG: invalid board index %u\n", board_idx); 3874 return 1; 3875 } 3876 3877 hpriv->hp_flags = hp_flags; 3878 if (hp_flags & MV_HP_PCIE) { 3879 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; 3880 hpriv->irq_mask_offset = PCIE_IRQ_MASK; 3881 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 3882 } else { 3883 hpriv->irq_cause_offset = PCI_IRQ_CAUSE; 3884 hpriv->irq_mask_offset = PCI_IRQ_MASK; 3885 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 3886 } 3887 3888 return 0; 3889 } 3890 3891 /** 3892 * mv_init_host - Perform some early initialization of the host. 3893 * @host: ATA host to initialize 3894 * 3895 * If possible, do an early global reset of the host. Then do 3896 * our port init and clear/unmask all/relevant host interrupts. 3897 * 3898 * LOCKING: 3899 * Inherited from caller. 3900 */ 3901 static int mv_init_host(struct ata_host *host) 3902 { 3903 int rc = 0, n_hc, port, hc; 3904 struct mv_host_priv *hpriv = host->private_data; 3905 void __iomem *mmio = hpriv->base; 3906 3907 rc = mv_chip_id(host, hpriv->board_idx); 3908 if (rc) 3909 goto done; 3910 3911 if (IS_SOC(hpriv)) { 3912 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; 3913 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; 3914 } else { 3915 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; 3916 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; 3917 } 3918 3919 /* initialize shadow irq mask with register's value */ 3920 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); 3921 3922 /* global interrupt mask: 0 == mask everything */ 3923 mv_set_main_irq_mask(host, ~0, 0); 3924 3925 n_hc = mv_get_hc_count(host->ports[0]->flags); 3926 3927 for (port = 0; port < host->n_ports; port++) 3928 if (hpriv->ops->read_preamp) 3929 hpriv->ops->read_preamp(hpriv, port, mmio); 3930 3931 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 3932 if (rc) 3933 goto done; 3934 3935 hpriv->ops->reset_flash(hpriv, mmio); 3936 hpriv->ops->reset_bus(host, mmio); 3937 hpriv->ops->enable_leds(hpriv, mmio); 3938 3939 for (port = 0; port < host->n_ports; port++) { 3940 struct ata_port *ap = host->ports[port]; 3941 void __iomem *port_mmio = mv_port_base(mmio, port); 3942 3943 mv_port_init(&ap->ioaddr, port_mmio); 3944 } 3945 3946 for (hc = 0; hc < n_hc; hc++) { 3947 void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3948 3949 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 3950 "(before clear)=0x%08x\n", hc, 3951 readl(hc_mmio + HC_CFG), 3952 readl(hc_mmio + HC_IRQ_CAUSE)); 3953 3954 /* Clear any currently outstanding hc interrupt conditions */ 3955 writelfl(0, hc_mmio + HC_IRQ_CAUSE); 3956 } 3957 3958 if (!IS_SOC(hpriv)) { 3959 /* Clear any currently outstanding host interrupt conditions */ 3960 writelfl(0, mmio + hpriv->irq_cause_offset); 3961 3962 /* and unmask interrupt generation for host regs */ 3963 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); 3964 } 3965 3966 /* 3967 * enable only global host interrupts for now. 3968 * The per-port interrupts get done later as ports are set up. 3969 */ 3970 mv_set_main_irq_mask(host, 0, PCI_ERR); 3971 mv_set_irq_coalescing(host, irq_coalescing_io_count, 3972 irq_coalescing_usecs); 3973 done: 3974 return rc; 3975 } 3976 3977 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 3978 { 3979 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 3980 MV_CRQB_Q_SZ, 0); 3981 if (!hpriv->crqb_pool) 3982 return -ENOMEM; 3983 3984 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 3985 MV_CRPB_Q_SZ, 0); 3986 if (!hpriv->crpb_pool) 3987 return -ENOMEM; 3988 3989 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 3990 MV_SG_TBL_SZ, 0); 3991 if (!hpriv->sg_tbl_pool) 3992 return -ENOMEM; 3993 3994 return 0; 3995 } 3996 3997 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 3998 struct mbus_dram_target_info *dram) 3999 { 4000 int i; 4001 4002 for (i = 0; i < 4; i++) { 4003 writel(0, hpriv->base + WINDOW_CTRL(i)); 4004 writel(0, hpriv->base + WINDOW_BASE(i)); 4005 } 4006 4007 for (i = 0; i < dram->num_cs; i++) { 4008 struct mbus_dram_window *cs = dram->cs + i; 4009 4010 writel(((cs->size - 1) & 0xffff0000) | 4011 (cs->mbus_attr << 8) | 4012 (dram->mbus_dram_target_id << 4) | 1, 4013 hpriv->base + WINDOW_CTRL(i)); 4014 writel(cs->base, hpriv->base + WINDOW_BASE(i)); 4015 } 4016 } 4017 4018 /** 4019 * mv_platform_probe - handle a positive probe of an soc Marvell 4020 * host 4021 * @pdev: platform device found 4022 * 4023 * LOCKING: 4024 * Inherited from caller. 4025 */ 4026 static int mv_platform_probe(struct platform_device *pdev) 4027 { 4028 static int printed_version; 4029 const struct mv_sata_platform_data *mv_platform_data; 4030 const struct ata_port_info *ppi[] = 4031 { &mv_port_info[chip_soc], NULL }; 4032 struct ata_host *host; 4033 struct mv_host_priv *hpriv; 4034 struct resource *res; 4035 int n_ports, rc; 4036 4037 if (!printed_version++) 4038 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 4039 4040 /* 4041 * Simple resource validation .. 4042 */ 4043 if (unlikely(pdev->num_resources != 2)) { 4044 dev_err(&pdev->dev, "invalid number of resources\n"); 4045 return -EINVAL; 4046 } 4047 4048 /* 4049 * Get the register base first 4050 */ 4051 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4052 if (res == NULL) 4053 return -EINVAL; 4054 4055 /* allocate host */ 4056 mv_platform_data = pdev->dev.platform_data; 4057 n_ports = mv_platform_data->n_ports; 4058 4059 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 4060 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 4061 4062 if (!host || !hpriv) 4063 return -ENOMEM; 4064 host->private_data = hpriv; 4065 hpriv->n_ports = n_ports; 4066 hpriv->board_idx = chip_soc; 4067 4068 host->iomap = NULL; 4069 hpriv->base = devm_ioremap(&pdev->dev, res->start, 4070 resource_size(res)); 4071 hpriv->base -= SATAHC0_REG_BASE; 4072 4073 #if defined(CONFIG_HAVE_CLK) 4074 hpriv->clk = clk_get(&pdev->dev, NULL); 4075 if (IS_ERR(hpriv->clk)) 4076 dev_notice(&pdev->dev, "cannot get clkdev\n"); 4077 else 4078 clk_enable(hpriv->clk); 4079 #endif 4080 4081 /* 4082 * (Re-)program MBUS remapping windows if we are asked to. 4083 */ 4084 if (mv_platform_data->dram != NULL) 4085 mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 4086 4087 rc = mv_create_dma_pools(hpriv, &pdev->dev); 4088 if (rc) 4089 goto err; 4090 4091 /* initialize adapter */ 4092 rc = mv_init_host(host); 4093 if (rc) 4094 goto err; 4095 4096 dev_printk(KERN_INFO, &pdev->dev, 4097 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 4098 host->n_ports); 4099 4100 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 4101 IRQF_SHARED, &mv6_sht); 4102 err: 4103 #if defined(CONFIG_HAVE_CLK) 4104 if (!IS_ERR(hpriv->clk)) { 4105 clk_disable(hpriv->clk); 4106 clk_put(hpriv->clk); 4107 } 4108 #endif 4109 4110 return rc; 4111 } 4112 4113 /* 4114 * 4115 * mv_platform_remove - unplug a platform interface 4116 * @pdev: platform device 4117 * 4118 * A platform bus SATA device has been unplugged. Perform the needed 4119 * cleanup. Also called on module unload for any active devices. 4120 */ 4121 static int __devexit mv_platform_remove(struct platform_device *pdev) 4122 { 4123 struct device *dev = &pdev->dev; 4124 struct ata_host *host = dev_get_drvdata(dev); 4125 #if defined(CONFIG_HAVE_CLK) 4126 struct mv_host_priv *hpriv = host->private_data; 4127 #endif 4128 ata_host_detach(host); 4129 4130 #if defined(CONFIG_HAVE_CLK) 4131 if (!IS_ERR(hpriv->clk)) { 4132 clk_disable(hpriv->clk); 4133 clk_put(hpriv->clk); 4134 } 4135 #endif 4136 return 0; 4137 } 4138 4139 #ifdef CONFIG_PM 4140 static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state) 4141 { 4142 struct ata_host *host = dev_get_drvdata(&pdev->dev); 4143 if (host) 4144 return ata_host_suspend(host, state); 4145 else 4146 return 0; 4147 } 4148 4149 static int mv_platform_resume(struct platform_device *pdev) 4150 { 4151 struct ata_host *host = dev_get_drvdata(&pdev->dev); 4152 int ret; 4153 4154 if (host) { 4155 struct mv_host_priv *hpriv = host->private_data; 4156 const struct mv_sata_platform_data *mv_platform_data = \ 4157 pdev->dev.platform_data; 4158 /* 4159 * (Re-)program MBUS remapping windows if we are asked to. 4160 */ 4161 if (mv_platform_data->dram != NULL) 4162 mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 4163 4164 /* initialize adapter */ 4165 ret = mv_init_host(host); 4166 if (ret) { 4167 printk(KERN_ERR DRV_NAME ": Error during HW init\n"); 4168 return ret; 4169 } 4170 ata_host_resume(host); 4171 } 4172 4173 return 0; 4174 } 4175 #else 4176 #define mv_platform_suspend NULL 4177 #define mv_platform_resume NULL 4178 #endif 4179 4180 static struct platform_driver mv_platform_driver = { 4181 .probe = mv_platform_probe, 4182 .remove = __devexit_p(mv_platform_remove), 4183 .suspend = mv_platform_suspend, 4184 .resume = mv_platform_resume, 4185 .driver = { 4186 .name = DRV_NAME, 4187 .owner = THIS_MODULE, 4188 }, 4189 }; 4190 4191 4192 #ifdef CONFIG_PCI 4193 static int mv_pci_init_one(struct pci_dev *pdev, 4194 const struct pci_device_id *ent); 4195 #ifdef CONFIG_PM 4196 static int mv_pci_device_resume(struct pci_dev *pdev); 4197 #endif 4198 4199 4200 static struct pci_driver mv_pci_driver = { 4201 .name = DRV_NAME, 4202 .id_table = mv_pci_tbl, 4203 .probe = mv_pci_init_one, 4204 .remove = ata_pci_remove_one, 4205 #ifdef CONFIG_PM 4206 .suspend = ata_pci_device_suspend, 4207 .resume = mv_pci_device_resume, 4208 #endif 4209 4210 }; 4211 4212 /* move to PCI layer or libata core? */ 4213 static int pci_go_64(struct pci_dev *pdev) 4214 { 4215 int rc; 4216 4217 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 4218 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 4219 if (rc) { 4220 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 4221 if (rc) { 4222 dev_printk(KERN_ERR, &pdev->dev, 4223 "64-bit DMA enable failed\n"); 4224 return rc; 4225 } 4226 } 4227 } else { 4228 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 4229 if (rc) { 4230 dev_printk(KERN_ERR, &pdev->dev, 4231 "32-bit DMA enable failed\n"); 4232 return rc; 4233 } 4234 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 4235 if (rc) { 4236 dev_printk(KERN_ERR, &pdev->dev, 4237 "32-bit consistent DMA enable failed\n"); 4238 return rc; 4239 } 4240 } 4241 4242 return rc; 4243 } 4244 4245 /** 4246 * mv_print_info - Dump key info to kernel log for perusal. 4247 * @host: ATA host to print info about 4248 * 4249 * FIXME: complete this. 4250 * 4251 * LOCKING: 4252 * Inherited from caller. 4253 */ 4254 static void mv_print_info(struct ata_host *host) 4255 { 4256 struct pci_dev *pdev = to_pci_dev(host->dev); 4257 struct mv_host_priv *hpriv = host->private_data; 4258 u8 scc; 4259 const char *scc_s, *gen; 4260 4261 /* Use this to determine the HW stepping of the chip so we know 4262 * what errata to workaround 4263 */ 4264 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 4265 if (scc == 0) 4266 scc_s = "SCSI"; 4267 else if (scc == 0x01) 4268 scc_s = "RAID"; 4269 else 4270 scc_s = "?"; 4271 4272 if (IS_GEN_I(hpriv)) 4273 gen = "I"; 4274 else if (IS_GEN_II(hpriv)) 4275 gen = "II"; 4276 else if (IS_GEN_IIE(hpriv)) 4277 gen = "IIE"; 4278 else 4279 gen = "?"; 4280 4281 dev_printk(KERN_INFO, &pdev->dev, 4282 "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 4283 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 4284 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 4285 } 4286 4287 /** 4288 * mv_pci_init_one - handle a positive probe of a PCI Marvell host 4289 * @pdev: PCI device found 4290 * @ent: PCI device ID entry for the matched host 4291 * 4292 * LOCKING: 4293 * Inherited from caller. 4294 */ 4295 static int mv_pci_init_one(struct pci_dev *pdev, 4296 const struct pci_device_id *ent) 4297 { 4298 static int printed_version; 4299 unsigned int board_idx = (unsigned int)ent->driver_data; 4300 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 4301 struct ata_host *host; 4302 struct mv_host_priv *hpriv; 4303 int n_ports, port, rc; 4304 4305 if (!printed_version++) 4306 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 4307 4308 /* allocate host */ 4309 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 4310 4311 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 4312 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 4313 if (!host || !hpriv) 4314 return -ENOMEM; 4315 host->private_data = hpriv; 4316 hpriv->n_ports = n_ports; 4317 hpriv->board_idx = board_idx; 4318 4319 /* acquire resources */ 4320 rc = pcim_enable_device(pdev); 4321 if (rc) 4322 return rc; 4323 4324 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 4325 if (rc == -EBUSY) 4326 pcim_pin_device(pdev); 4327 if (rc) 4328 return rc; 4329 host->iomap = pcim_iomap_table(pdev); 4330 hpriv->base = host->iomap[MV_PRIMARY_BAR]; 4331 4332 rc = pci_go_64(pdev); 4333 if (rc) 4334 return rc; 4335 4336 rc = mv_create_dma_pools(hpriv, &pdev->dev); 4337 if (rc) 4338 return rc; 4339 4340 for (port = 0; port < host->n_ports; port++) { 4341 struct ata_port *ap = host->ports[port]; 4342 void __iomem *port_mmio = mv_port_base(hpriv->base, port); 4343 unsigned int offset = port_mmio - hpriv->base; 4344 4345 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 4346 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 4347 } 4348 4349 /* initialize adapter */ 4350 rc = mv_init_host(host); 4351 if (rc) 4352 return rc; 4353 4354 /* Enable message-switched interrupts, if requested */ 4355 if (msi && pci_enable_msi(pdev) == 0) 4356 hpriv->hp_flags |= MV_HP_FLAG_MSI; 4357 4358 mv_dump_pci_cfg(pdev, 0x68); 4359 mv_print_info(host); 4360 4361 pci_set_master(pdev); 4362 pci_try_set_mwi(pdev); 4363 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 4364 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 4365 } 4366 4367 #ifdef CONFIG_PM 4368 static int mv_pci_device_resume(struct pci_dev *pdev) 4369 { 4370 struct ata_host *host = dev_get_drvdata(&pdev->dev); 4371 int rc; 4372 4373 rc = ata_pci_device_do_resume(pdev); 4374 if (rc) 4375 return rc; 4376 4377 /* initialize adapter */ 4378 rc = mv_init_host(host); 4379 if (rc) 4380 return rc; 4381 4382 ata_host_resume(host); 4383 4384 return 0; 4385 } 4386 #endif 4387 #endif 4388 4389 static int mv_platform_probe(struct platform_device *pdev); 4390 static int __devexit mv_platform_remove(struct platform_device *pdev); 4391 4392 static int __init mv_init(void) 4393 { 4394 int rc = -ENODEV; 4395 #ifdef CONFIG_PCI 4396 rc = pci_register_driver(&mv_pci_driver); 4397 if (rc < 0) 4398 return rc; 4399 #endif 4400 rc = platform_driver_register(&mv_platform_driver); 4401 4402 #ifdef CONFIG_PCI 4403 if (rc < 0) 4404 pci_unregister_driver(&mv_pci_driver); 4405 #endif 4406 return rc; 4407 } 4408 4409 static void __exit mv_exit(void) 4410 { 4411 #ifdef CONFIG_PCI 4412 pci_unregister_driver(&mv_pci_driver); 4413 #endif 4414 platform_driver_unregister(&mv_platform_driver); 4415 } 4416 4417 MODULE_AUTHOR("Brett Russ"); 4418 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 4419 MODULE_LICENSE("GPL"); 4420 MODULE_DEVICE_TABLE(pci, mv_pci_tbl); 4421 MODULE_VERSION(DRV_VERSION); 4422 MODULE_ALIAS("platform:" DRV_NAME); 4423 4424 module_init(mv_init); 4425 module_exit(mv_exit); 4426