1 /* 2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers. 3 * 4 * This driver is heavily based upon: 5 * 6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 7 * 8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 9 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 10 * Portions Copyright (C) 2003 Red Hat Inc 11 * Portions Copyright (C) 2005-2010 MontaVista Software, Inc. 12 * 13 * TODO 14 * Look into engine reset on timeout errors. Should not be required. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/init.h> 21 #include <linux/blkdev.h> 22 #include <linux/delay.h> 23 #include <scsi/scsi_host.h> 24 #include <linux/libata.h> 25 26 #define DRV_NAME "pata_hpt37x" 27 #define DRV_VERSION "0.6.22" 28 29 struct hpt_clock { 30 u8 xfer_speed; 31 u32 timing; 32 }; 33 34 struct hpt_chip { 35 const char *name; 36 unsigned int base; 37 struct hpt_clock const *clocks[4]; 38 }; 39 40 /* key for bus clock timings 41 * bit 42 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. 43 * cycles = value + 1 44 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. 45 * cycles = value + 1 46 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file 47 * register access. 48 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file 49 * register access. 50 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. 51 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. 52 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. 53 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file 54 * register access. 55 * 28 UDMA enable. 56 * 29 DMA enable. 57 * 30 PIO_MST enable. If set, the chip is in bus master mode during 58 * PIO xfer. 59 * 31 FIFO enable. Only for PIO. 60 */ 61 62 static struct hpt_clock hpt37x_timings_33[] = { 63 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */ 64 { XFER_UDMA_5, 0x12446231 }, 65 { XFER_UDMA_4, 0x12446231 }, 66 { XFER_UDMA_3, 0x126c6231 }, 67 { XFER_UDMA_2, 0x12486231 }, 68 { XFER_UDMA_1, 0x124c6233 }, 69 { XFER_UDMA_0, 0x12506297 }, 70 71 { XFER_MW_DMA_2, 0x22406c31 }, 72 { XFER_MW_DMA_1, 0x22406c33 }, 73 { XFER_MW_DMA_0, 0x22406c97 }, 74 75 { XFER_PIO_4, 0x06414e31 }, 76 { XFER_PIO_3, 0x06414e42 }, 77 { XFER_PIO_2, 0x06414e53 }, 78 { XFER_PIO_1, 0x06814e93 }, 79 { XFER_PIO_0, 0x06814ea7 } 80 }; 81 82 static struct hpt_clock hpt37x_timings_50[] = { 83 { XFER_UDMA_6, 0x12848242 }, 84 { XFER_UDMA_5, 0x12848242 }, 85 { XFER_UDMA_4, 0x12ac8242 }, 86 { XFER_UDMA_3, 0x128c8242 }, 87 { XFER_UDMA_2, 0x120c8242 }, 88 { XFER_UDMA_1, 0x12148254 }, 89 { XFER_UDMA_0, 0x121882ea }, 90 91 { XFER_MW_DMA_2, 0x22808242 }, 92 { XFER_MW_DMA_1, 0x22808254 }, 93 { XFER_MW_DMA_0, 0x228082ea }, 94 95 { XFER_PIO_4, 0x0a81f442 }, 96 { XFER_PIO_3, 0x0a81f443 }, 97 { XFER_PIO_2, 0x0a81f454 }, 98 { XFER_PIO_1, 0x0ac1f465 }, 99 { XFER_PIO_0, 0x0ac1f48a } 100 }; 101 102 static struct hpt_clock hpt37x_timings_66[] = { 103 { XFER_UDMA_6, 0x1c869c62 }, 104 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */ 105 { XFER_UDMA_4, 0x1c8a9c62 }, 106 { XFER_UDMA_3, 0x1c8e9c62 }, 107 { XFER_UDMA_2, 0x1c929c62 }, 108 { XFER_UDMA_1, 0x1c9a9c62 }, 109 { XFER_UDMA_0, 0x1c829c62 }, 110 111 { XFER_MW_DMA_2, 0x2c829c62 }, 112 { XFER_MW_DMA_1, 0x2c829c66 }, 113 { XFER_MW_DMA_0, 0x2c829d2e }, 114 115 { XFER_PIO_4, 0x0c829c62 }, 116 { XFER_PIO_3, 0x0c829c84 }, 117 { XFER_PIO_2, 0x0c829ca6 }, 118 { XFER_PIO_1, 0x0d029d26 }, 119 { XFER_PIO_0, 0x0d029d5e } 120 }; 121 122 123 static const struct hpt_chip hpt370 = { 124 "HPT370", 125 48, 126 { 127 hpt37x_timings_33, 128 NULL, 129 NULL, 130 NULL 131 } 132 }; 133 134 static const struct hpt_chip hpt370a = { 135 "HPT370A", 136 48, 137 { 138 hpt37x_timings_33, 139 NULL, 140 hpt37x_timings_50, 141 NULL 142 } 143 }; 144 145 static const struct hpt_chip hpt372 = { 146 "HPT372", 147 55, 148 { 149 hpt37x_timings_33, 150 NULL, 151 hpt37x_timings_50, 152 hpt37x_timings_66 153 } 154 }; 155 156 static const struct hpt_chip hpt302 = { 157 "HPT302", 158 66, 159 { 160 hpt37x_timings_33, 161 NULL, 162 hpt37x_timings_50, 163 hpt37x_timings_66 164 } 165 }; 166 167 static const struct hpt_chip hpt371 = { 168 "HPT371", 169 66, 170 { 171 hpt37x_timings_33, 172 NULL, 173 hpt37x_timings_50, 174 hpt37x_timings_66 175 } 176 }; 177 178 static const struct hpt_chip hpt372a = { 179 "HPT372A", 180 66, 181 { 182 hpt37x_timings_33, 183 NULL, 184 hpt37x_timings_50, 185 hpt37x_timings_66 186 } 187 }; 188 189 static const struct hpt_chip hpt374 = { 190 "HPT374", 191 48, 192 { 193 hpt37x_timings_33, 194 NULL, 195 NULL, 196 NULL 197 } 198 }; 199 200 /** 201 * hpt37x_find_mode - reset the hpt37x bus 202 * @ap: ATA port 203 * @speed: transfer mode 204 * 205 * Return the 32bit register programming information for this channel 206 * that matches the speed provided. 207 */ 208 209 static u32 hpt37x_find_mode(struct ata_port *ap, int speed) 210 { 211 struct hpt_clock *clocks = ap->host->private_data; 212 213 while (clocks->xfer_speed) { 214 if (clocks->xfer_speed == speed) 215 return clocks->timing; 216 clocks++; 217 } 218 BUG(); 219 return 0xffffffffU; /* silence compiler warning */ 220 } 221 222 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, 223 const char * const list[]) 224 { 225 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 226 int i = 0; 227 228 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 229 230 while (list[i] != NULL) { 231 if (!strcmp(list[i], model_num)) { 232 pr_warning(DRV_NAME ": %s is not supported for %s.\n", 233 modestr, list[i]); 234 return 1; 235 } 236 i++; 237 } 238 return 0; 239 } 240 241 static const char * const bad_ata33[] = { 242 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", 243 "Maxtor 90845U3", "Maxtor 90650U2", 244 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", 245 "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", 246 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", 247 "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", 248 "Maxtor 90510D4", 249 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", 250 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", 251 "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", 252 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", 253 "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", 254 NULL 255 }; 256 257 static const char * const bad_ata100_5[] = { 258 "IBM-DTLA-307075", 259 "IBM-DTLA-307060", 260 "IBM-DTLA-307045", 261 "IBM-DTLA-307030", 262 "IBM-DTLA-307020", 263 "IBM-DTLA-307015", 264 "IBM-DTLA-305040", 265 "IBM-DTLA-305030", 266 "IBM-DTLA-305020", 267 "IC35L010AVER07-0", 268 "IC35L020AVER07-0", 269 "IC35L030AVER07-0", 270 "IC35L040AVER07-0", 271 "IC35L060AVER07-0", 272 "WDC AC310200R", 273 NULL 274 }; 275 276 /** 277 * hpt370_filter - mode selection filter 278 * @adev: ATA device 279 * 280 * Block UDMA on devices that cause trouble with this controller. 281 */ 282 283 static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask) 284 { 285 if (adev->class == ATA_DEV_ATA) { 286 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) 287 mask &= ~ATA_MASK_UDMA; 288 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) 289 mask &= ~(0xE0 << ATA_SHIFT_UDMA); 290 } 291 return mask; 292 } 293 294 /** 295 * hpt370a_filter - mode selection filter 296 * @adev: ATA device 297 * 298 * Block UDMA on devices that cause trouble with this controller. 299 */ 300 301 static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask) 302 { 303 if (adev->class == ATA_DEV_ATA) { 304 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) 305 mask &= ~(0xE0 << ATA_SHIFT_UDMA); 306 } 307 return mask; 308 } 309 310 /** 311 * hpt372_filter - mode selection filter 312 * @adev: ATA device 313 * @mask: mode mask 314 * 315 * The Marvell bridge chips used on the HighPoint SATA cards do not seem 316 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... 317 */ 318 static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask) 319 { 320 if (ata_id_is_sata(adev->id)) 321 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); 322 323 return mask; 324 } 325 326 /** 327 * hpt37x_cable_detect - Detect the cable type 328 * @ap: ATA port to detect on 329 * 330 * Return the cable type attached to this port 331 */ 332 333 static int hpt37x_cable_detect(struct ata_port *ap) 334 { 335 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 336 u8 scr2, ata66; 337 338 pci_read_config_byte(pdev, 0x5B, &scr2); 339 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); 340 341 udelay(10); /* debounce */ 342 343 /* Cable register now active */ 344 pci_read_config_byte(pdev, 0x5A, &ata66); 345 /* Restore state */ 346 pci_write_config_byte(pdev, 0x5B, scr2); 347 348 if (ata66 & (2 >> ap->port_no)) 349 return ATA_CBL_PATA40; 350 else 351 return ATA_CBL_PATA80; 352 } 353 354 /** 355 * hpt374_fn1_cable_detect - Detect the cable type 356 * @ap: ATA port to detect on 357 * 358 * Return the cable type attached to this port 359 */ 360 361 static int hpt374_fn1_cable_detect(struct ata_port *ap) 362 { 363 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 364 unsigned int mcrbase = 0x50 + 4 * ap->port_no; 365 u16 mcr3; 366 u8 ata66; 367 368 /* Do the extra channel work */ 369 pci_read_config_word(pdev, mcrbase + 2, &mcr3); 370 /* Set bit 15 of 0x52 to enable TCBLID as input */ 371 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000); 372 pci_read_config_byte(pdev, 0x5A, &ata66); 373 /* Reset TCBLID/FCBLID to output */ 374 pci_write_config_word(pdev, mcrbase + 2, mcr3); 375 376 if (ata66 & (2 >> ap->port_no)) 377 return ATA_CBL_PATA40; 378 else 379 return ATA_CBL_PATA80; 380 } 381 382 /** 383 * hpt37x_pre_reset - reset the hpt37x bus 384 * @link: ATA link to reset 385 * @deadline: deadline jiffies for the operation 386 * 387 * Perform the initial reset handling for the HPT37x. 388 */ 389 390 static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline) 391 { 392 struct ata_port *ap = link->ap; 393 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 394 static const struct pci_bits hpt37x_enable_bits[] = { 395 { 0x50, 1, 0x04, 0x04 }, 396 { 0x54, 1, 0x04, 0x04 } 397 }; 398 399 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) 400 return -ENOENT; 401 402 /* Reset the state machine */ 403 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 404 udelay(100); 405 406 return ata_sff_prereset(link, deadline); 407 } 408 409 static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev, 410 u8 mode) 411 { 412 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 413 u32 addr1, addr2; 414 u32 reg, timing, mask; 415 u8 fast; 416 417 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 418 addr2 = 0x51 + 4 * ap->port_no; 419 420 /* Fast interrupt prediction disable, hold off interrupt disable */ 421 pci_read_config_byte(pdev, addr2, &fast); 422 fast &= ~0x02; 423 fast |= 0x01; 424 pci_write_config_byte(pdev, addr2, fast); 425 426 /* Determine timing mask and find matching mode entry */ 427 if (mode < XFER_MW_DMA_0) 428 mask = 0xcfc3ffff; 429 else if (mode < XFER_UDMA_0) 430 mask = 0x31c001ff; 431 else 432 mask = 0x303c0000; 433 434 timing = hpt37x_find_mode(ap, mode); 435 436 pci_read_config_dword(pdev, addr1, ®); 437 reg = (reg & ~mask) | (timing & mask); 438 pci_write_config_dword(pdev, addr1, reg); 439 } 440 /** 441 * hpt370_set_piomode - PIO setup 442 * @ap: ATA interface 443 * @adev: device on the interface 444 * 445 * Perform PIO mode setup. 446 */ 447 448 static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev) 449 { 450 hpt370_set_mode(ap, adev, adev->pio_mode); 451 } 452 453 /** 454 * hpt370_set_dmamode - DMA timing setup 455 * @ap: ATA interface 456 * @adev: Device being configured 457 * 458 * Set up the channel for MWDMA or UDMA modes. 459 */ 460 461 static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev) 462 { 463 hpt370_set_mode(ap, adev, adev->dma_mode); 464 } 465 466 /** 467 * hpt370_bmdma_end - DMA engine stop 468 * @qc: ATA command 469 * 470 * Work around the HPT370 DMA engine. 471 */ 472 473 static void hpt370_bmdma_stop(struct ata_queued_cmd *qc) 474 { 475 struct ata_port *ap = qc->ap; 476 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 477 void __iomem *bmdma = ap->ioaddr.bmdma_addr; 478 u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); 479 u8 dma_cmd; 480 481 if (dma_stat & ATA_DMA_ACTIVE) { 482 udelay(20); 483 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); 484 } 485 if (dma_stat & ATA_DMA_ACTIVE) { 486 /* Clear the engine */ 487 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 488 udelay(10); 489 /* Stop DMA */ 490 dma_cmd = ioread8(bmdma + ATA_DMA_CMD); 491 iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD); 492 /* Clear Error */ 493 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); 494 iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, 495 bmdma + ATA_DMA_STATUS); 496 /* Clear the engine */ 497 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 498 udelay(10); 499 } 500 ata_bmdma_stop(qc); 501 } 502 503 static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev, 504 u8 mode) 505 { 506 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 507 u32 addr1, addr2; 508 u32 reg, timing, mask; 509 u8 fast; 510 511 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 512 addr2 = 0x51 + 4 * ap->port_no; 513 514 /* Fast interrupt prediction disable, hold off interrupt disable */ 515 pci_read_config_byte(pdev, addr2, &fast); 516 fast &= ~0x07; 517 pci_write_config_byte(pdev, addr2, fast); 518 519 /* Determine timing mask and find matching mode entry */ 520 if (mode < XFER_MW_DMA_0) 521 mask = 0xcfc3ffff; 522 else if (mode < XFER_UDMA_0) 523 mask = 0x31c001ff; 524 else 525 mask = 0x303c0000; 526 527 timing = hpt37x_find_mode(ap, mode); 528 529 pci_read_config_dword(pdev, addr1, ®); 530 reg = (reg & ~mask) | (timing & mask); 531 pci_write_config_dword(pdev, addr1, reg); 532 } 533 534 /** 535 * hpt372_set_piomode - PIO setup 536 * @ap: ATA interface 537 * @adev: device on the interface 538 * 539 * Perform PIO mode setup. 540 */ 541 542 static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev) 543 { 544 hpt372_set_mode(ap, adev, adev->pio_mode); 545 } 546 547 /** 548 * hpt372_set_dmamode - DMA timing setup 549 * @ap: ATA interface 550 * @adev: Device being configured 551 * 552 * Set up the channel for MWDMA or UDMA modes. 553 */ 554 555 static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev) 556 { 557 hpt372_set_mode(ap, adev, adev->dma_mode); 558 } 559 560 /** 561 * hpt37x_bmdma_end - DMA engine stop 562 * @qc: ATA command 563 * 564 * Clean up after the HPT372 and later DMA engine 565 */ 566 567 static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc) 568 { 569 struct ata_port *ap = qc->ap; 570 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 571 int mscreg = 0x50 + 4 * ap->port_no; 572 u8 bwsr_stat, msc_stat; 573 574 pci_read_config_byte(pdev, 0x6A, &bwsr_stat); 575 pci_read_config_byte(pdev, mscreg, &msc_stat); 576 if (bwsr_stat & (1 << ap->port_no)) 577 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); 578 ata_bmdma_stop(qc); 579 } 580 581 582 static struct scsi_host_template hpt37x_sht = { 583 ATA_BMDMA_SHT(DRV_NAME), 584 }; 585 586 /* 587 * Configuration for HPT370 588 */ 589 590 static struct ata_port_operations hpt370_port_ops = { 591 .inherits = &ata_bmdma_port_ops, 592 593 .bmdma_stop = hpt370_bmdma_stop, 594 595 .mode_filter = hpt370_filter, 596 .cable_detect = hpt37x_cable_detect, 597 .set_piomode = hpt370_set_piomode, 598 .set_dmamode = hpt370_set_dmamode, 599 .prereset = hpt37x_pre_reset, 600 }; 601 602 /* 603 * Configuration for HPT370A. Close to 370 but less filters 604 */ 605 606 static struct ata_port_operations hpt370a_port_ops = { 607 .inherits = &hpt370_port_ops, 608 .mode_filter = hpt370a_filter, 609 }; 610 611 /* 612 * Configuration for HPT371 and HPT302. Slightly different PIO and DMA 613 * mode setting functionality. 614 */ 615 616 static struct ata_port_operations hpt302_port_ops = { 617 .inherits = &ata_bmdma_port_ops, 618 619 .bmdma_stop = hpt37x_bmdma_stop, 620 621 .cable_detect = hpt37x_cable_detect, 622 .set_piomode = hpt372_set_piomode, 623 .set_dmamode = hpt372_set_dmamode, 624 .prereset = hpt37x_pre_reset, 625 }; 626 627 /* 628 * Configuration for HPT372. Mode setting works like 371 and 302 629 * but we have a mode filter. 630 */ 631 632 static struct ata_port_operations hpt372_port_ops = { 633 .inherits = &hpt302_port_ops, 634 .mode_filter = hpt372_filter, 635 }; 636 637 /* 638 * Configuration for HPT374. Mode setting and filtering works like 372 639 * but we have a different cable detection procedure for function 1. 640 */ 641 642 static struct ata_port_operations hpt374_fn1_port_ops = { 643 .inherits = &hpt372_port_ops, 644 .cable_detect = hpt374_fn1_cable_detect, 645 }; 646 647 /** 648 * hpt37x_clock_slot - Turn timing to PC clock entry 649 * @freq: Reported frequency timing 650 * @base: Base timing 651 * 652 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50 653 * and 3 for 66Mhz) 654 */ 655 656 static int hpt37x_clock_slot(unsigned int freq, unsigned int base) 657 { 658 unsigned int f = (base * freq) / 192; /* Mhz */ 659 if (f < 40) 660 return 0; /* 33Mhz slot */ 661 if (f < 45) 662 return 1; /* 40Mhz slot */ 663 if (f < 55) 664 return 2; /* 50Mhz slot */ 665 return 3; /* 60Mhz slot */ 666 } 667 668 /** 669 * hpt37x_calibrate_dpll - Calibrate the DPLL loop 670 * @dev: PCI device 671 * 672 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this 673 * succeeds 674 */ 675 676 static int hpt37x_calibrate_dpll(struct pci_dev *dev) 677 { 678 u8 reg5b; 679 u32 reg5c; 680 int tries; 681 682 for (tries = 0; tries < 0x5000; tries++) { 683 udelay(50); 684 pci_read_config_byte(dev, 0x5b, ®5b); 685 if (reg5b & 0x80) { 686 /* See if it stays set */ 687 for (tries = 0; tries < 0x1000; tries++) { 688 pci_read_config_byte(dev, 0x5b, ®5b); 689 /* Failed ? */ 690 if ((reg5b & 0x80) == 0) 691 return 0; 692 } 693 /* Turn off tuning, we have the DPLL set */ 694 pci_read_config_dword(dev, 0x5c, ®5c); 695 pci_write_config_dword(dev, 0x5c, reg5c & ~0x100); 696 return 1; 697 } 698 } 699 /* Never went stable */ 700 return 0; 701 } 702 703 static u32 hpt374_read_freq(struct pci_dev *pdev) 704 { 705 u32 freq; 706 unsigned long io_base = pci_resource_start(pdev, 4); 707 708 if (PCI_FUNC(pdev->devfn) & 1) { 709 struct pci_dev *pdev_0; 710 711 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1); 712 /* Someone hot plugged the controller on us ? */ 713 if (pdev_0 == NULL) 714 return 0; 715 io_base = pci_resource_start(pdev_0, 4); 716 freq = inl(io_base + 0x90); 717 pci_dev_put(pdev_0); 718 } else 719 freq = inl(io_base + 0x90); 720 return freq; 721 } 722 723 /** 724 * hpt37x_init_one - Initialise an HPT37X/302 725 * @dev: PCI device 726 * @id: Entry in match table 727 * 728 * Initialise an HPT37x device. There are some interesting complications 729 * here. Firstly the chip may report 366 and be one of several variants. 730 * Secondly all the timings depend on the clock for the chip which we must 731 * detect and look up 732 * 733 * This is the known chip mappings. It may be missing a couple of later 734 * releases. 735 * 736 * Chip version PCI Rev Notes 737 * HPT366 4 (HPT366) 0 Other driver 738 * HPT366 4 (HPT366) 1 Other driver 739 * HPT368 4 (HPT366) 2 Other driver 740 * HPT370 4 (HPT366) 3 UDMA100 741 * HPT370A 4 (HPT366) 4 UDMA100 742 * HPT372 4 (HPT366) 5 UDMA133 (1) 743 * HPT372N 4 (HPT366) 6 Other driver 744 * HPT372A 5 (HPT372) 1 UDMA133 (1) 745 * HPT372N 5 (HPT372) 2 Other driver 746 * HPT302 6 (HPT302) 1 UDMA133 747 * HPT302N 6 (HPT302) 2 Other driver 748 * HPT371 7 (HPT371) * UDMA133 749 * HPT374 8 (HPT374) * UDMA133 4 channel 750 * HPT372N 9 (HPT372N) * Other driver 751 * 752 * (1) UDMA133 support depends on the bus clock 753 */ 754 755 static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id) 756 { 757 /* HPT370 - UDMA100 */ 758 static const struct ata_port_info info_hpt370 = { 759 .flags = ATA_FLAG_SLAVE_POSS, 760 .pio_mask = ATA_PIO4, 761 .mwdma_mask = ATA_MWDMA2, 762 .udma_mask = ATA_UDMA5, 763 .port_ops = &hpt370_port_ops 764 }; 765 /* HPT370A - UDMA100 */ 766 static const struct ata_port_info info_hpt370a = { 767 .flags = ATA_FLAG_SLAVE_POSS, 768 .pio_mask = ATA_PIO4, 769 .mwdma_mask = ATA_MWDMA2, 770 .udma_mask = ATA_UDMA5, 771 .port_ops = &hpt370a_port_ops 772 }; 773 /* HPT370 - UDMA66 */ 774 static const struct ata_port_info info_hpt370_33 = { 775 .flags = ATA_FLAG_SLAVE_POSS, 776 .pio_mask = ATA_PIO4, 777 .mwdma_mask = ATA_MWDMA2, 778 .udma_mask = ATA_UDMA4, 779 .port_ops = &hpt370_port_ops 780 }; 781 /* HPT370A - UDMA66 */ 782 static const struct ata_port_info info_hpt370a_33 = { 783 .flags = ATA_FLAG_SLAVE_POSS, 784 .pio_mask = ATA_PIO4, 785 .mwdma_mask = ATA_MWDMA2, 786 .udma_mask = ATA_UDMA4, 787 .port_ops = &hpt370a_port_ops 788 }; 789 /* HPT372 - UDMA133 */ 790 static const struct ata_port_info info_hpt372 = { 791 .flags = ATA_FLAG_SLAVE_POSS, 792 .pio_mask = ATA_PIO4, 793 .mwdma_mask = ATA_MWDMA2, 794 .udma_mask = ATA_UDMA6, 795 .port_ops = &hpt372_port_ops 796 }; 797 /* HPT371, 302 - UDMA133 */ 798 static const struct ata_port_info info_hpt302 = { 799 .flags = ATA_FLAG_SLAVE_POSS, 800 .pio_mask = ATA_PIO4, 801 .mwdma_mask = ATA_MWDMA2, 802 .udma_mask = ATA_UDMA6, 803 .port_ops = &hpt302_port_ops 804 }; 805 /* HPT374 - UDMA100, function 1 uses different cable_detect method */ 806 static const struct ata_port_info info_hpt374_fn0 = { 807 .flags = ATA_FLAG_SLAVE_POSS, 808 .pio_mask = ATA_PIO4, 809 .mwdma_mask = ATA_MWDMA2, 810 .udma_mask = ATA_UDMA5, 811 .port_ops = &hpt372_port_ops 812 }; 813 static const struct ata_port_info info_hpt374_fn1 = { 814 .flags = ATA_FLAG_SLAVE_POSS, 815 .pio_mask = ATA_PIO4, 816 .mwdma_mask = ATA_MWDMA2, 817 .udma_mask = ATA_UDMA5, 818 .port_ops = &hpt374_fn1_port_ops 819 }; 820 821 static const int MHz[4] = { 33, 40, 50, 66 }; 822 void *private_data = NULL; 823 const struct ata_port_info *ppi[] = { NULL, NULL }; 824 u8 rev = dev->revision; 825 u8 irqmask; 826 u8 mcr1; 827 u32 freq; 828 int prefer_dpll = 1; 829 830 unsigned long iobase = pci_resource_start(dev, 4); 831 832 const struct hpt_chip *chip_table; 833 int clock_slot; 834 int rc; 835 836 rc = pcim_enable_device(dev); 837 if (rc) 838 return rc; 839 840 switch (dev->device) { 841 case PCI_DEVICE_ID_TTI_HPT366: 842 /* May be a later chip in disguise. Check */ 843 /* Older chips are in the HPT366 driver. Ignore them */ 844 if (rev < 3) 845 return -ENODEV; 846 /* N series chips have their own driver. Ignore */ 847 if (rev == 6) 848 return -ENODEV; 849 850 switch (rev) { 851 case 3: 852 ppi[0] = &info_hpt370; 853 chip_table = &hpt370; 854 prefer_dpll = 0; 855 break; 856 case 4: 857 ppi[0] = &info_hpt370a; 858 chip_table = &hpt370a; 859 prefer_dpll = 0; 860 break; 861 case 5: 862 ppi[0] = &info_hpt372; 863 chip_table = &hpt372; 864 break; 865 default: 866 pr_err(DRV_NAME ": Unknown HPT366 subtype, " 867 "please report (%d).\n", rev); 868 return -ENODEV; 869 } 870 break; 871 case PCI_DEVICE_ID_TTI_HPT372: 872 /* 372N if rev >= 2 */ 873 if (rev >= 2) 874 return -ENODEV; 875 ppi[0] = &info_hpt372; 876 chip_table = &hpt372a; 877 break; 878 case PCI_DEVICE_ID_TTI_HPT302: 879 /* 302N if rev > 1 */ 880 if (rev > 1) 881 return -ENODEV; 882 ppi[0] = &info_hpt302; 883 /* Check this */ 884 chip_table = &hpt302; 885 break; 886 case PCI_DEVICE_ID_TTI_HPT371: 887 if (rev > 1) 888 return -ENODEV; 889 ppi[0] = &info_hpt302; 890 chip_table = &hpt371; 891 /* 892 * Single channel device, master is not present but the BIOS 893 * (or us for non x86) must mark it absent 894 */ 895 pci_read_config_byte(dev, 0x50, &mcr1); 896 mcr1 &= ~0x04; 897 pci_write_config_byte(dev, 0x50, mcr1); 898 break; 899 case PCI_DEVICE_ID_TTI_HPT374: 900 chip_table = &hpt374; 901 if (!(PCI_FUNC(dev->devfn) & 1)) 902 *ppi = &info_hpt374_fn0; 903 else 904 *ppi = &info_hpt374_fn1; 905 break; 906 default: 907 pr_err(DRV_NAME ": PCI table is bogus, please report (%d).\n", 908 dev->device); 909 return -ENODEV; 910 } 911 /* Ok so this is a chip we support */ 912 913 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 914 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 915 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 916 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 917 918 pci_read_config_byte(dev, 0x5A, &irqmask); 919 irqmask &= ~0x10; 920 pci_write_config_byte(dev, 0x5a, irqmask); 921 922 /* 923 * default to pci clock. make sure MA15/16 are set to output 924 * to prevent drives having problems with 40-pin cables. Needed 925 * for some drives such as IBM-DTLA which will not enter ready 926 * state on reset when PDIAG is a input. 927 */ 928 929 pci_write_config_byte(dev, 0x5b, 0x23); 930 931 /* 932 * HighPoint does this for HPT372A. 933 * NOTE: This register is only writeable via I/O space. 934 */ 935 if (chip_table == &hpt372a) 936 outb(0x0e, iobase + 0x9c); 937 938 /* 939 * Some devices do not let this value be accessed via PCI space 940 * according to the old driver. In addition we must use the value 941 * from FN 0 on the HPT374. 942 */ 943 944 if (chip_table == &hpt374) { 945 freq = hpt374_read_freq(dev); 946 if (freq == 0) 947 return -ENODEV; 948 } else 949 freq = inl(iobase + 0x90); 950 951 if ((freq >> 12) != 0xABCDE) { 952 int i; 953 u8 sr; 954 u32 total = 0; 955 956 pr_warning(DRV_NAME ": BIOS has not set timing clocks.\n"); 957 958 /* This is the process the HPT371 BIOS is reported to use */ 959 for (i = 0; i < 128; i++) { 960 pci_read_config_byte(dev, 0x78, &sr); 961 total += sr & 0x1FF; 962 udelay(15); 963 } 964 freq = total / 128; 965 } 966 freq &= 0x1FF; 967 968 /* 969 * Turn the frequency check into a band and then find a timing 970 * table to match it. 971 */ 972 973 clock_slot = hpt37x_clock_slot(freq, chip_table->base); 974 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { 975 /* 976 * We need to try PLL mode instead 977 * 978 * For non UDMA133 capable devices we should 979 * use a 50MHz DPLL by choice 980 */ 981 unsigned int f_low, f_high; 982 int dpll, adjust; 983 984 /* Compute DPLL */ 985 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; 986 987 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; 988 f_high = f_low + 2; 989 if (clock_slot > 1) 990 f_high += 2; 991 992 /* Select the DPLL clock. */ 993 pci_write_config_byte(dev, 0x5b, 0x21); 994 pci_write_config_dword(dev, 0x5C, 995 (f_high << 16) | f_low | 0x100); 996 997 for (adjust = 0; adjust < 8; adjust++) { 998 if (hpt37x_calibrate_dpll(dev)) 999 break; 1000 /* 1001 * See if it'll settle at a fractionally 1002 * different clock 1003 */ 1004 if (adjust & 1) 1005 f_low -= adjust >> 1; 1006 else 1007 f_high += adjust >> 1; 1008 pci_write_config_dword(dev, 0x5C, 1009 (f_high << 16) | f_low | 0x100); 1010 } 1011 if (adjust == 8) { 1012 pr_err(DRV_NAME ": DPLL did not stabilize!\n"); 1013 return -ENODEV; 1014 } 1015 if (dpll == 3) 1016 private_data = (void *)hpt37x_timings_66; 1017 else 1018 private_data = (void *)hpt37x_timings_50; 1019 1020 pr_info(DRV_NAME ": bus clock %dMHz, using %dMHz DPLL.\n", 1021 MHz[clock_slot], MHz[dpll]); 1022 } else { 1023 private_data = (void *)chip_table->clocks[clock_slot]; 1024 /* 1025 * Perform a final fixup. Note that we will have used the 1026 * DPLL on the HPT372 which means we don't have to worry 1027 * about lack of UDMA133 support on lower clocks 1028 */ 1029 1030 if (clock_slot < 2 && ppi[0] == &info_hpt370) 1031 ppi[0] = &info_hpt370_33; 1032 if (clock_slot < 2 && ppi[0] == &info_hpt370a) 1033 ppi[0] = &info_hpt370a_33; 1034 1035 pr_info(DRV_NAME ": %s using %dMHz bus clock.\n", 1036 chip_table->name, MHz[clock_slot]); 1037 } 1038 1039 /* Now kick off ATA set up */ 1040 return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0); 1041 } 1042 1043 static const struct pci_device_id hpt37x[] = { 1044 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, 1045 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, 1046 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, 1047 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), }, 1048 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, 1049 1050 { }, 1051 }; 1052 1053 static struct pci_driver hpt37x_pci_driver = { 1054 .name = DRV_NAME, 1055 .id_table = hpt37x, 1056 .probe = hpt37x_init_one, 1057 .remove = ata_pci_remove_one 1058 }; 1059 1060 static int __init hpt37x_init(void) 1061 { 1062 return pci_register_driver(&hpt37x_pci_driver); 1063 } 1064 1065 static void __exit hpt37x_exit(void) 1066 { 1067 pci_unregister_driver(&hpt37x_pci_driver); 1068 } 1069 1070 MODULE_AUTHOR("Alan Cox"); 1071 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x"); 1072 MODULE_LICENSE("GPL"); 1073 MODULE_DEVICE_TABLE(pci, hpt37x); 1074 MODULE_VERSION(DRV_VERSION); 1075 1076 module_init(hpt37x_init); 1077 module_exit(hpt37x_exit); 1078