1 /* 2 * libahci.c - Common AHCI SATA low-level routines 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/gfp.h> 37 #include <linux/module.h> 38 #include <linux/init.h> 39 #include <linux/blkdev.h> 40 #include <linux/delay.h> 41 #include <linux/interrupt.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/device.h> 44 #include <scsi/scsi_host.h> 45 #include <scsi/scsi_cmnd.h> 46 #include <linux/libata.h> 47 #include "ahci.h" 48 #include "libata.h" 49 50 static int ahci_skip_host_reset; 51 int ahci_ignore_sss; 52 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 53 54 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 55 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 56 57 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 58 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 59 60 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 61 unsigned hints); 62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 64 size_t size); 65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 66 ssize_t size); 67 68 69 70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 72 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); 73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 74 static int ahci_port_start(struct ata_port *ap); 75 static void ahci_port_stop(struct ata_port *ap); 76 static void ahci_qc_prep(struct ata_queued_cmd *qc); 77 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 78 static void ahci_freeze(struct ata_port *ap); 79 static void ahci_thaw(struct ata_port *ap); 80 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep); 81 static void ahci_enable_fbs(struct ata_port *ap); 82 static void ahci_disable_fbs(struct ata_port *ap); 83 static void ahci_pmp_attach(struct ata_port *ap); 84 static void ahci_pmp_detach(struct ata_port *ap); 85 static int ahci_softreset(struct ata_link *link, unsigned int *class, 86 unsigned long deadline); 87 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 88 unsigned long deadline); 89 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 90 unsigned long deadline); 91 static void ahci_postreset(struct ata_link *link, unsigned int *class); 92 static void ahci_error_handler(struct ata_port *ap); 93 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 94 static void ahci_dev_config(struct ata_device *dev); 95 #ifdef CONFIG_PM 96 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 97 #endif 98 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 99 static ssize_t ahci_activity_store(struct ata_device *dev, 100 enum sw_activity val); 101 static void ahci_init_sw_activity(struct ata_link *link); 102 103 static ssize_t ahci_show_host_caps(struct device *dev, 104 struct device_attribute *attr, char *buf); 105 static ssize_t ahci_show_host_cap2(struct device *dev, 106 struct device_attribute *attr, char *buf); 107 static ssize_t ahci_show_host_version(struct device *dev, 108 struct device_attribute *attr, char *buf); 109 static ssize_t ahci_show_port_cmd(struct device *dev, 110 struct device_attribute *attr, char *buf); 111 static ssize_t ahci_read_em_buffer(struct device *dev, 112 struct device_attribute *attr, char *buf); 113 static ssize_t ahci_store_em_buffer(struct device *dev, 114 struct device_attribute *attr, 115 const char *buf, size_t size); 116 static ssize_t ahci_show_em_supported(struct device *dev, 117 struct device_attribute *attr, char *buf); 118 119 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 120 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 121 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 122 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 123 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 124 ahci_read_em_buffer, ahci_store_em_buffer); 125 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 126 127 struct device_attribute *ahci_shost_attrs[] = { 128 &dev_attr_link_power_management_policy, 129 &dev_attr_em_message_type, 130 &dev_attr_em_message, 131 &dev_attr_ahci_host_caps, 132 &dev_attr_ahci_host_cap2, 133 &dev_attr_ahci_host_version, 134 &dev_attr_ahci_port_cmd, 135 &dev_attr_em_buffer, 136 &dev_attr_em_message_supported, 137 NULL 138 }; 139 EXPORT_SYMBOL_GPL(ahci_shost_attrs); 140 141 struct device_attribute *ahci_sdev_attrs[] = { 142 &dev_attr_sw_activity, 143 &dev_attr_unload_heads, 144 NULL 145 }; 146 EXPORT_SYMBOL_GPL(ahci_sdev_attrs); 147 148 struct ata_port_operations ahci_ops = { 149 .inherits = &sata_pmp_port_ops, 150 151 .qc_defer = ahci_pmp_qc_defer, 152 .qc_prep = ahci_qc_prep, 153 .qc_issue = ahci_qc_issue, 154 .qc_fill_rtf = ahci_qc_fill_rtf, 155 156 .freeze = ahci_freeze, 157 .thaw = ahci_thaw, 158 .softreset = ahci_softreset, 159 .hardreset = ahci_hardreset, 160 .postreset = ahci_postreset, 161 .pmp_softreset = ahci_softreset, 162 .error_handler = ahci_error_handler, 163 .post_internal_cmd = ahci_post_internal_cmd, 164 .dev_config = ahci_dev_config, 165 166 .scr_read = ahci_scr_read, 167 .scr_write = ahci_scr_write, 168 .pmp_attach = ahci_pmp_attach, 169 .pmp_detach = ahci_pmp_detach, 170 171 .set_lpm = ahci_set_lpm, 172 .em_show = ahci_led_show, 173 .em_store = ahci_led_store, 174 .sw_activity_show = ahci_activity_show, 175 .sw_activity_store = ahci_activity_store, 176 #ifdef CONFIG_PM 177 .port_suspend = ahci_port_suspend, 178 .port_resume = ahci_port_resume, 179 #endif 180 .port_start = ahci_port_start, 181 .port_stop = ahci_port_stop, 182 }; 183 EXPORT_SYMBOL_GPL(ahci_ops); 184 185 struct ata_port_operations ahci_pmp_retry_srst_ops = { 186 .inherits = &ahci_ops, 187 .softreset = ahci_pmp_retry_softreset, 188 }; 189 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops); 190 191 int ahci_em_messages = 1; 192 EXPORT_SYMBOL_GPL(ahci_em_messages); 193 module_param(ahci_em_messages, int, 0444); 194 /* add other LED protocol types when they become supported */ 195 MODULE_PARM_DESC(ahci_em_messages, 196 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 197 198 int devslp_idle_timeout = 1000; /* device sleep idle timeout in ms */ 199 module_param(devslp_idle_timeout, int, 0644); 200 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout"); 201 202 static void ahci_enable_ahci(void __iomem *mmio) 203 { 204 int i; 205 u32 tmp; 206 207 /* turn on AHCI_EN */ 208 tmp = readl(mmio + HOST_CTL); 209 if (tmp & HOST_AHCI_EN) 210 return; 211 212 /* Some controllers need AHCI_EN to be written multiple times. 213 * Try a few times before giving up. 214 */ 215 for (i = 0; i < 5; i++) { 216 tmp |= HOST_AHCI_EN; 217 writel(tmp, mmio + HOST_CTL); 218 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 219 if (tmp & HOST_AHCI_EN) 220 return; 221 msleep(10); 222 } 223 224 WARN_ON(1); 225 } 226 227 static ssize_t ahci_show_host_caps(struct device *dev, 228 struct device_attribute *attr, char *buf) 229 { 230 struct Scsi_Host *shost = class_to_shost(dev); 231 struct ata_port *ap = ata_shost_to_port(shost); 232 struct ahci_host_priv *hpriv = ap->host->private_data; 233 234 return sprintf(buf, "%x\n", hpriv->cap); 235 } 236 237 static ssize_t ahci_show_host_cap2(struct device *dev, 238 struct device_attribute *attr, char *buf) 239 { 240 struct Scsi_Host *shost = class_to_shost(dev); 241 struct ata_port *ap = ata_shost_to_port(shost); 242 struct ahci_host_priv *hpriv = ap->host->private_data; 243 244 return sprintf(buf, "%x\n", hpriv->cap2); 245 } 246 247 static ssize_t ahci_show_host_version(struct device *dev, 248 struct device_attribute *attr, char *buf) 249 { 250 struct Scsi_Host *shost = class_to_shost(dev); 251 struct ata_port *ap = ata_shost_to_port(shost); 252 struct ahci_host_priv *hpriv = ap->host->private_data; 253 void __iomem *mmio = hpriv->mmio; 254 255 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION)); 256 } 257 258 static ssize_t ahci_show_port_cmd(struct device *dev, 259 struct device_attribute *attr, char *buf) 260 { 261 struct Scsi_Host *shost = class_to_shost(dev); 262 struct ata_port *ap = ata_shost_to_port(shost); 263 void __iomem *port_mmio = ahci_port_base(ap); 264 265 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 266 } 267 268 static ssize_t ahci_read_em_buffer(struct device *dev, 269 struct device_attribute *attr, char *buf) 270 { 271 struct Scsi_Host *shost = class_to_shost(dev); 272 struct ata_port *ap = ata_shost_to_port(shost); 273 struct ahci_host_priv *hpriv = ap->host->private_data; 274 void __iomem *mmio = hpriv->mmio; 275 void __iomem *em_mmio = mmio + hpriv->em_loc; 276 u32 em_ctl, msg; 277 unsigned long flags; 278 size_t count; 279 int i; 280 281 spin_lock_irqsave(ap->lock, flags); 282 283 em_ctl = readl(mmio + HOST_EM_CTL); 284 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 285 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 286 spin_unlock_irqrestore(ap->lock, flags); 287 return -EINVAL; 288 } 289 290 if (!(em_ctl & EM_CTL_MR)) { 291 spin_unlock_irqrestore(ap->lock, flags); 292 return -EAGAIN; 293 } 294 295 if (!(em_ctl & EM_CTL_SMB)) 296 em_mmio += hpriv->em_buf_sz; 297 298 count = hpriv->em_buf_sz; 299 300 /* the count should not be larger than PAGE_SIZE */ 301 if (count > PAGE_SIZE) { 302 if (printk_ratelimit()) 303 ata_port_warn(ap, 304 "EM read buffer size too large: " 305 "buffer size %u, page size %lu\n", 306 hpriv->em_buf_sz, PAGE_SIZE); 307 count = PAGE_SIZE; 308 } 309 310 for (i = 0; i < count; i += 4) { 311 msg = readl(em_mmio + i); 312 buf[i] = msg & 0xff; 313 buf[i + 1] = (msg >> 8) & 0xff; 314 buf[i + 2] = (msg >> 16) & 0xff; 315 buf[i + 3] = (msg >> 24) & 0xff; 316 } 317 318 spin_unlock_irqrestore(ap->lock, flags); 319 320 return i; 321 } 322 323 static ssize_t ahci_store_em_buffer(struct device *dev, 324 struct device_attribute *attr, 325 const char *buf, size_t size) 326 { 327 struct Scsi_Host *shost = class_to_shost(dev); 328 struct ata_port *ap = ata_shost_to_port(shost); 329 struct ahci_host_priv *hpriv = ap->host->private_data; 330 void __iomem *mmio = hpriv->mmio; 331 void __iomem *em_mmio = mmio + hpriv->em_loc; 332 const unsigned char *msg_buf = buf; 333 u32 em_ctl, msg; 334 unsigned long flags; 335 int i; 336 337 /* check size validity */ 338 if (!(ap->flags & ATA_FLAG_EM) || 339 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 340 size % 4 || size > hpriv->em_buf_sz) 341 return -EINVAL; 342 343 spin_lock_irqsave(ap->lock, flags); 344 345 em_ctl = readl(mmio + HOST_EM_CTL); 346 if (em_ctl & EM_CTL_TM) { 347 spin_unlock_irqrestore(ap->lock, flags); 348 return -EBUSY; 349 } 350 351 for (i = 0; i < size; i += 4) { 352 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 353 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 354 writel(msg, em_mmio + i); 355 } 356 357 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 358 359 spin_unlock_irqrestore(ap->lock, flags); 360 361 return size; 362 } 363 364 static ssize_t ahci_show_em_supported(struct device *dev, 365 struct device_attribute *attr, char *buf) 366 { 367 struct Scsi_Host *shost = class_to_shost(dev); 368 struct ata_port *ap = ata_shost_to_port(shost); 369 struct ahci_host_priv *hpriv = ap->host->private_data; 370 void __iomem *mmio = hpriv->mmio; 371 u32 em_ctl; 372 373 em_ctl = readl(mmio + HOST_EM_CTL); 374 375 return sprintf(buf, "%s%s%s%s\n", 376 em_ctl & EM_CTL_LED ? "led " : "", 377 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 378 em_ctl & EM_CTL_SES ? "ses-2 " : "", 379 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 380 } 381 382 /** 383 * ahci_save_initial_config - Save and fixup initial config values 384 * @dev: target AHCI device 385 * @hpriv: host private area to store config values 386 * @force_port_map: force port map to a specified value 387 * @mask_port_map: mask out particular bits from port map 388 * 389 * Some registers containing configuration info might be setup by 390 * BIOS and might be cleared on reset. This function saves the 391 * initial values of those registers into @hpriv such that they 392 * can be restored after controller reset. 393 * 394 * If inconsistent, config values are fixed up by this function. 395 * 396 * LOCKING: 397 * None. 398 */ 399 void ahci_save_initial_config(struct device *dev, 400 struct ahci_host_priv *hpriv, 401 unsigned int force_port_map, 402 unsigned int mask_port_map) 403 { 404 void __iomem *mmio = hpriv->mmio; 405 u32 cap, cap2, vers, port_map; 406 int i; 407 408 /* make sure AHCI mode is enabled before accessing CAP */ 409 ahci_enable_ahci(mmio); 410 411 /* Values prefixed with saved_ are written back to host after 412 * reset. Values without are used for driver operation. 413 */ 414 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 415 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 416 417 /* CAP2 register is only defined for AHCI 1.2 and later */ 418 vers = readl(mmio + HOST_VERSION); 419 if ((vers >> 16) > 1 || 420 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 421 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 422 else 423 hpriv->saved_cap2 = cap2 = 0; 424 425 /* some chips have errata preventing 64bit use */ 426 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 427 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n"); 428 cap &= ~HOST_CAP_64; 429 } 430 431 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 432 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n"); 433 cap &= ~HOST_CAP_NCQ; 434 } 435 436 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 437 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n"); 438 cap |= HOST_CAP_NCQ; 439 } 440 441 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 442 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n"); 443 cap &= ~HOST_CAP_PMP; 444 } 445 446 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 447 dev_info(dev, 448 "controller can't do SNTF, turning off CAP_SNTF\n"); 449 cap &= ~HOST_CAP_SNTF; 450 } 451 452 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 453 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n"); 454 cap |= HOST_CAP_FBS; 455 } 456 457 if (force_port_map && port_map != force_port_map) { 458 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", 459 port_map, force_port_map); 460 port_map = force_port_map; 461 } 462 463 if (mask_port_map) { 464 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n", 465 port_map, 466 port_map & mask_port_map); 467 port_map &= mask_port_map; 468 } 469 470 /* cross check port_map and cap.n_ports */ 471 if (port_map) { 472 int map_ports = 0; 473 474 for (i = 0; i < AHCI_MAX_PORTS; i++) 475 if (port_map & (1 << i)) 476 map_ports++; 477 478 /* If PI has more ports than n_ports, whine, clear 479 * port_map and let it be generated from n_ports. 480 */ 481 if (map_ports > ahci_nr_ports(cap)) { 482 dev_warn(dev, 483 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n", 484 port_map, ahci_nr_ports(cap)); 485 port_map = 0; 486 } 487 } 488 489 /* fabricate port_map from cap.nr_ports */ 490 if (!port_map) { 491 port_map = (1 << ahci_nr_ports(cap)) - 1; 492 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map); 493 494 /* write the fixed up value to the PI register */ 495 hpriv->saved_port_map = port_map; 496 } 497 498 /* record values to use during operation */ 499 hpriv->cap = cap; 500 hpriv->cap2 = cap2; 501 hpriv->port_map = port_map; 502 } 503 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 504 505 /** 506 * ahci_restore_initial_config - Restore initial config 507 * @host: target ATA host 508 * 509 * Restore initial config stored by ahci_save_initial_config(). 510 * 511 * LOCKING: 512 * None. 513 */ 514 static void ahci_restore_initial_config(struct ata_host *host) 515 { 516 struct ahci_host_priv *hpriv = host->private_data; 517 void __iomem *mmio = hpriv->mmio; 518 519 writel(hpriv->saved_cap, mmio + HOST_CAP); 520 if (hpriv->saved_cap2) 521 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 522 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 523 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 524 } 525 526 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 527 { 528 static const int offset[] = { 529 [SCR_STATUS] = PORT_SCR_STAT, 530 [SCR_CONTROL] = PORT_SCR_CTL, 531 [SCR_ERROR] = PORT_SCR_ERR, 532 [SCR_ACTIVE] = PORT_SCR_ACT, 533 [SCR_NOTIFICATION] = PORT_SCR_NTF, 534 }; 535 struct ahci_host_priv *hpriv = ap->host->private_data; 536 537 if (sc_reg < ARRAY_SIZE(offset) && 538 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 539 return offset[sc_reg]; 540 return 0; 541 } 542 543 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 544 { 545 void __iomem *port_mmio = ahci_port_base(link->ap); 546 int offset = ahci_scr_offset(link->ap, sc_reg); 547 548 if (offset) { 549 *val = readl(port_mmio + offset); 550 return 0; 551 } 552 return -EINVAL; 553 } 554 555 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 556 { 557 void __iomem *port_mmio = ahci_port_base(link->ap); 558 int offset = ahci_scr_offset(link->ap, sc_reg); 559 560 if (offset) { 561 writel(val, port_mmio + offset); 562 return 0; 563 } 564 return -EINVAL; 565 } 566 567 void ahci_start_engine(struct ata_port *ap) 568 { 569 void __iomem *port_mmio = ahci_port_base(ap); 570 u32 tmp; 571 572 /* start DMA */ 573 tmp = readl(port_mmio + PORT_CMD); 574 tmp |= PORT_CMD_START; 575 writel(tmp, port_mmio + PORT_CMD); 576 readl(port_mmio + PORT_CMD); /* flush */ 577 } 578 EXPORT_SYMBOL_GPL(ahci_start_engine); 579 580 int ahci_stop_engine(struct ata_port *ap) 581 { 582 void __iomem *port_mmio = ahci_port_base(ap); 583 u32 tmp; 584 585 tmp = readl(port_mmio + PORT_CMD); 586 587 /* check if the HBA is idle */ 588 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 589 return 0; 590 591 /* setting HBA to idle */ 592 tmp &= ~PORT_CMD_START; 593 writel(tmp, port_mmio + PORT_CMD); 594 595 /* wait for engine to stop. This could be as long as 500 msec */ 596 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 597 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 598 if (tmp & PORT_CMD_LIST_ON) 599 return -EIO; 600 601 return 0; 602 } 603 EXPORT_SYMBOL_GPL(ahci_stop_engine); 604 605 static void ahci_start_fis_rx(struct ata_port *ap) 606 { 607 void __iomem *port_mmio = ahci_port_base(ap); 608 struct ahci_host_priv *hpriv = ap->host->private_data; 609 struct ahci_port_priv *pp = ap->private_data; 610 u32 tmp; 611 612 /* set FIS registers */ 613 if (hpriv->cap & HOST_CAP_64) 614 writel((pp->cmd_slot_dma >> 16) >> 16, 615 port_mmio + PORT_LST_ADDR_HI); 616 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 617 618 if (hpriv->cap & HOST_CAP_64) 619 writel((pp->rx_fis_dma >> 16) >> 16, 620 port_mmio + PORT_FIS_ADDR_HI); 621 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 622 623 /* enable FIS reception */ 624 tmp = readl(port_mmio + PORT_CMD); 625 tmp |= PORT_CMD_FIS_RX; 626 writel(tmp, port_mmio + PORT_CMD); 627 628 /* flush */ 629 readl(port_mmio + PORT_CMD); 630 } 631 632 static int ahci_stop_fis_rx(struct ata_port *ap) 633 { 634 void __iomem *port_mmio = ahci_port_base(ap); 635 u32 tmp; 636 637 /* disable FIS reception */ 638 tmp = readl(port_mmio + PORT_CMD); 639 tmp &= ~PORT_CMD_FIS_RX; 640 writel(tmp, port_mmio + PORT_CMD); 641 642 /* wait for completion, spec says 500ms, give it 1000 */ 643 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 644 PORT_CMD_FIS_ON, 10, 1000); 645 if (tmp & PORT_CMD_FIS_ON) 646 return -EBUSY; 647 648 return 0; 649 } 650 651 static void ahci_power_up(struct ata_port *ap) 652 { 653 struct ahci_host_priv *hpriv = ap->host->private_data; 654 void __iomem *port_mmio = ahci_port_base(ap); 655 u32 cmd; 656 657 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 658 659 /* spin up device */ 660 if (hpriv->cap & HOST_CAP_SSS) { 661 cmd |= PORT_CMD_SPIN_UP; 662 writel(cmd, port_mmio + PORT_CMD); 663 } 664 665 /* wake up link */ 666 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 667 } 668 669 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 670 unsigned int hints) 671 { 672 struct ata_port *ap = link->ap; 673 struct ahci_host_priv *hpriv = ap->host->private_data; 674 struct ahci_port_priv *pp = ap->private_data; 675 void __iomem *port_mmio = ahci_port_base(ap); 676 677 if (policy != ATA_LPM_MAX_POWER) { 678 /* 679 * Disable interrupts on Phy Ready. This keeps us from 680 * getting woken up due to spurious phy ready 681 * interrupts. 682 */ 683 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 684 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 685 686 sata_link_scr_lpm(link, policy, false); 687 } 688 689 if (hpriv->cap & HOST_CAP_ALPM) { 690 u32 cmd = readl(port_mmio + PORT_CMD); 691 692 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 693 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 694 cmd |= PORT_CMD_ICC_ACTIVE; 695 696 writel(cmd, port_mmio + PORT_CMD); 697 readl(port_mmio + PORT_CMD); 698 699 /* wait 10ms to be sure we've come out of LPM state */ 700 ata_msleep(ap, 10); 701 } else { 702 cmd |= PORT_CMD_ALPE; 703 if (policy == ATA_LPM_MIN_POWER) 704 cmd |= PORT_CMD_ASP; 705 706 /* write out new cmd value */ 707 writel(cmd, port_mmio + PORT_CMD); 708 } 709 } 710 711 /* set aggressive device sleep */ 712 if ((hpriv->cap2 & HOST_CAP2_SDS) && 713 (hpriv->cap2 & HOST_CAP2_SADM) && 714 (link->device->flags & ATA_DFLAG_DEVSLP)) { 715 if (policy == ATA_LPM_MIN_POWER) 716 ahci_set_aggressive_devslp(ap, true); 717 else 718 ahci_set_aggressive_devslp(ap, false); 719 } 720 721 if (policy == ATA_LPM_MAX_POWER) { 722 sata_link_scr_lpm(link, policy, false); 723 724 /* turn PHYRDY IRQ back on */ 725 pp->intr_mask |= PORT_IRQ_PHYRDY; 726 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 727 } 728 729 return 0; 730 } 731 732 #ifdef CONFIG_PM 733 static void ahci_power_down(struct ata_port *ap) 734 { 735 struct ahci_host_priv *hpriv = ap->host->private_data; 736 void __iomem *port_mmio = ahci_port_base(ap); 737 u32 cmd, scontrol; 738 739 if (!(hpriv->cap & HOST_CAP_SSS)) 740 return; 741 742 /* put device into listen mode, first set PxSCTL.DET to 0 */ 743 scontrol = readl(port_mmio + PORT_SCR_CTL); 744 scontrol &= ~0xf; 745 writel(scontrol, port_mmio + PORT_SCR_CTL); 746 747 /* then set PxCMD.SUD to 0 */ 748 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 749 cmd &= ~PORT_CMD_SPIN_UP; 750 writel(cmd, port_mmio + PORT_CMD); 751 } 752 #endif 753 754 static void ahci_start_port(struct ata_port *ap) 755 { 756 struct ahci_host_priv *hpriv = ap->host->private_data; 757 struct ahci_port_priv *pp = ap->private_data; 758 struct ata_link *link; 759 struct ahci_em_priv *emp; 760 ssize_t rc; 761 int i; 762 763 /* enable FIS reception */ 764 ahci_start_fis_rx(ap); 765 766 /* enable DMA */ 767 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE)) 768 ahci_start_engine(ap); 769 770 /* turn on LEDs */ 771 if (ap->flags & ATA_FLAG_EM) { 772 ata_for_each_link(link, ap, EDGE) { 773 emp = &pp->em_priv[link->pmp]; 774 775 /* EM Transmit bit maybe busy during init */ 776 for (i = 0; i < EM_MAX_RETRY; i++) { 777 rc = ahci_transmit_led_message(ap, 778 emp->led_state, 779 4); 780 if (rc == -EBUSY) 781 ata_msleep(ap, 1); 782 else 783 break; 784 } 785 } 786 } 787 788 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 789 ata_for_each_link(link, ap, EDGE) 790 ahci_init_sw_activity(link); 791 792 } 793 794 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 795 { 796 int rc; 797 798 /* disable DMA */ 799 rc = ahci_stop_engine(ap); 800 if (rc) { 801 *emsg = "failed to stop engine"; 802 return rc; 803 } 804 805 /* disable FIS reception */ 806 rc = ahci_stop_fis_rx(ap); 807 if (rc) { 808 *emsg = "failed stop FIS RX"; 809 return rc; 810 } 811 812 return 0; 813 } 814 815 int ahci_reset_controller(struct ata_host *host) 816 { 817 struct ahci_host_priv *hpriv = host->private_data; 818 void __iomem *mmio = hpriv->mmio; 819 u32 tmp; 820 821 /* we must be in AHCI mode, before using anything 822 * AHCI-specific, such as HOST_RESET. 823 */ 824 ahci_enable_ahci(mmio); 825 826 /* global controller reset */ 827 if (!ahci_skip_host_reset) { 828 tmp = readl(mmio + HOST_CTL); 829 if ((tmp & HOST_RESET) == 0) { 830 writel(tmp | HOST_RESET, mmio + HOST_CTL); 831 readl(mmio + HOST_CTL); /* flush */ 832 } 833 834 /* 835 * to perform host reset, OS should set HOST_RESET 836 * and poll until this bit is read to be "0". 837 * reset must complete within 1 second, or 838 * the hardware should be considered fried. 839 */ 840 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 841 HOST_RESET, 10, 1000); 842 843 if (tmp & HOST_RESET) { 844 dev_err(host->dev, "controller reset failed (0x%x)\n", 845 tmp); 846 return -EIO; 847 } 848 849 /* turn on AHCI mode */ 850 ahci_enable_ahci(mmio); 851 852 /* Some registers might be cleared on reset. Restore 853 * initial values. 854 */ 855 ahci_restore_initial_config(host); 856 } else 857 dev_info(host->dev, "skipping global host reset\n"); 858 859 return 0; 860 } 861 EXPORT_SYMBOL_GPL(ahci_reset_controller); 862 863 static void ahci_sw_activity(struct ata_link *link) 864 { 865 struct ata_port *ap = link->ap; 866 struct ahci_port_priv *pp = ap->private_data; 867 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 868 869 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 870 return; 871 872 emp->activity++; 873 if (!timer_pending(&emp->timer)) 874 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 875 } 876 877 static void ahci_sw_activity_blink(unsigned long arg) 878 { 879 struct ata_link *link = (struct ata_link *)arg; 880 struct ata_port *ap = link->ap; 881 struct ahci_port_priv *pp = ap->private_data; 882 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 883 unsigned long led_message = emp->led_state; 884 u32 activity_led_state; 885 unsigned long flags; 886 887 led_message &= EM_MSG_LED_VALUE; 888 led_message |= ap->port_no | (link->pmp << 8); 889 890 /* check to see if we've had activity. If so, 891 * toggle state of LED and reset timer. If not, 892 * turn LED to desired idle state. 893 */ 894 spin_lock_irqsave(ap->lock, flags); 895 if (emp->saved_activity != emp->activity) { 896 emp->saved_activity = emp->activity; 897 /* get the current LED state */ 898 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 899 900 if (activity_led_state) 901 activity_led_state = 0; 902 else 903 activity_led_state = 1; 904 905 /* clear old state */ 906 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 907 908 /* toggle state */ 909 led_message |= (activity_led_state << 16); 910 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 911 } else { 912 /* switch to idle */ 913 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 914 if (emp->blink_policy == BLINK_OFF) 915 led_message |= (1 << 16); 916 } 917 spin_unlock_irqrestore(ap->lock, flags); 918 ahci_transmit_led_message(ap, led_message, 4); 919 } 920 921 static void ahci_init_sw_activity(struct ata_link *link) 922 { 923 struct ata_port *ap = link->ap; 924 struct ahci_port_priv *pp = ap->private_data; 925 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 926 927 /* init activity stats, setup timer */ 928 emp->saved_activity = emp->activity = 0; 929 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); 930 931 /* check our blink policy and set flag for link if it's enabled */ 932 if (emp->blink_policy) 933 link->flags |= ATA_LFLAG_SW_ACTIVITY; 934 } 935 936 int ahci_reset_em(struct ata_host *host) 937 { 938 struct ahci_host_priv *hpriv = host->private_data; 939 void __iomem *mmio = hpriv->mmio; 940 u32 em_ctl; 941 942 em_ctl = readl(mmio + HOST_EM_CTL); 943 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 944 return -EINVAL; 945 946 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 947 return 0; 948 } 949 EXPORT_SYMBOL_GPL(ahci_reset_em); 950 951 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 952 ssize_t size) 953 { 954 struct ahci_host_priv *hpriv = ap->host->private_data; 955 struct ahci_port_priv *pp = ap->private_data; 956 void __iomem *mmio = hpriv->mmio; 957 u32 em_ctl; 958 u32 message[] = {0, 0}; 959 unsigned long flags; 960 int pmp; 961 struct ahci_em_priv *emp; 962 963 /* get the slot number from the message */ 964 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 965 if (pmp < EM_MAX_SLOTS) 966 emp = &pp->em_priv[pmp]; 967 else 968 return -EINVAL; 969 970 spin_lock_irqsave(ap->lock, flags); 971 972 /* 973 * if we are still busy transmitting a previous message, 974 * do not allow 975 */ 976 em_ctl = readl(mmio + HOST_EM_CTL); 977 if (em_ctl & EM_CTL_TM) { 978 spin_unlock_irqrestore(ap->lock, flags); 979 return -EBUSY; 980 } 981 982 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 983 /* 984 * create message header - this is all zero except for 985 * the message size, which is 4 bytes. 986 */ 987 message[0] |= (4 << 8); 988 989 /* ignore 0:4 of byte zero, fill in port info yourself */ 990 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 991 992 /* write message to EM_LOC */ 993 writel(message[0], mmio + hpriv->em_loc); 994 writel(message[1], mmio + hpriv->em_loc+4); 995 996 /* 997 * tell hardware to transmit the message 998 */ 999 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1000 } 1001 1002 /* save off new led state for port/slot */ 1003 emp->led_state = state; 1004 1005 spin_unlock_irqrestore(ap->lock, flags); 1006 return size; 1007 } 1008 1009 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1010 { 1011 struct ahci_port_priv *pp = ap->private_data; 1012 struct ata_link *link; 1013 struct ahci_em_priv *emp; 1014 int rc = 0; 1015 1016 ata_for_each_link(link, ap, EDGE) { 1017 emp = &pp->em_priv[link->pmp]; 1018 rc += sprintf(buf, "%lx\n", emp->led_state); 1019 } 1020 return rc; 1021 } 1022 1023 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1024 size_t size) 1025 { 1026 int state; 1027 int pmp; 1028 struct ahci_port_priv *pp = ap->private_data; 1029 struct ahci_em_priv *emp; 1030 1031 state = simple_strtoul(buf, NULL, 0); 1032 1033 /* get the slot number from the message */ 1034 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1035 if (pmp < EM_MAX_SLOTS) 1036 emp = &pp->em_priv[pmp]; 1037 else 1038 return -EINVAL; 1039 1040 /* mask off the activity bits if we are in sw_activity 1041 * mode, user should turn off sw_activity before setting 1042 * activity led through em_message 1043 */ 1044 if (emp->blink_policy) 1045 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1046 1047 return ahci_transmit_led_message(ap, state, size); 1048 } 1049 1050 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1051 { 1052 struct ata_link *link = dev->link; 1053 struct ata_port *ap = link->ap; 1054 struct ahci_port_priv *pp = ap->private_data; 1055 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1056 u32 port_led_state = emp->led_state; 1057 1058 /* save the desired Activity LED behavior */ 1059 if (val == OFF) { 1060 /* clear LFLAG */ 1061 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1062 1063 /* set the LED to OFF */ 1064 port_led_state &= EM_MSG_LED_VALUE_OFF; 1065 port_led_state |= (ap->port_no | (link->pmp << 8)); 1066 ahci_transmit_led_message(ap, port_led_state, 4); 1067 } else { 1068 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1069 if (val == BLINK_OFF) { 1070 /* set LED to ON for idle */ 1071 port_led_state &= EM_MSG_LED_VALUE_OFF; 1072 port_led_state |= (ap->port_no | (link->pmp << 8)); 1073 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1074 ahci_transmit_led_message(ap, port_led_state, 4); 1075 } 1076 } 1077 emp->blink_policy = val; 1078 return 0; 1079 } 1080 1081 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1082 { 1083 struct ata_link *link = dev->link; 1084 struct ata_port *ap = link->ap; 1085 struct ahci_port_priv *pp = ap->private_data; 1086 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1087 1088 /* display the saved value of activity behavior for this 1089 * disk. 1090 */ 1091 return sprintf(buf, "%d\n", emp->blink_policy); 1092 } 1093 1094 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1095 int port_no, void __iomem *mmio, 1096 void __iomem *port_mmio) 1097 { 1098 const char *emsg = NULL; 1099 int rc; 1100 u32 tmp; 1101 1102 /* make sure port is not active */ 1103 rc = ahci_deinit_port(ap, &emsg); 1104 if (rc) 1105 dev_warn(dev, "%s (%d)\n", emsg, rc); 1106 1107 /* clear SError */ 1108 tmp = readl(port_mmio + PORT_SCR_ERR); 1109 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1110 writel(tmp, port_mmio + PORT_SCR_ERR); 1111 1112 /* clear port IRQ */ 1113 tmp = readl(port_mmio + PORT_IRQ_STAT); 1114 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1115 if (tmp) 1116 writel(tmp, port_mmio + PORT_IRQ_STAT); 1117 1118 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1119 } 1120 1121 void ahci_init_controller(struct ata_host *host) 1122 { 1123 struct ahci_host_priv *hpriv = host->private_data; 1124 void __iomem *mmio = hpriv->mmio; 1125 int i; 1126 void __iomem *port_mmio; 1127 u32 tmp; 1128 1129 for (i = 0; i < host->n_ports; i++) { 1130 struct ata_port *ap = host->ports[i]; 1131 1132 port_mmio = ahci_port_base(ap); 1133 if (ata_port_is_dummy(ap)) 1134 continue; 1135 1136 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1137 } 1138 1139 tmp = readl(mmio + HOST_CTL); 1140 VPRINTK("HOST_CTL 0x%x\n", tmp); 1141 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1142 tmp = readl(mmio + HOST_CTL); 1143 VPRINTK("HOST_CTL 0x%x\n", tmp); 1144 } 1145 EXPORT_SYMBOL_GPL(ahci_init_controller); 1146 1147 static void ahci_dev_config(struct ata_device *dev) 1148 { 1149 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1150 1151 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1152 dev->max_sectors = 255; 1153 ata_dev_info(dev, 1154 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1155 } 1156 } 1157 1158 unsigned int ahci_dev_classify(struct ata_port *ap) 1159 { 1160 void __iomem *port_mmio = ahci_port_base(ap); 1161 struct ata_taskfile tf; 1162 u32 tmp; 1163 1164 tmp = readl(port_mmio + PORT_SIG); 1165 tf.lbah = (tmp >> 24) & 0xff; 1166 tf.lbam = (tmp >> 16) & 0xff; 1167 tf.lbal = (tmp >> 8) & 0xff; 1168 tf.nsect = (tmp) & 0xff; 1169 1170 return ata_dev_classify(&tf); 1171 } 1172 EXPORT_SYMBOL_GPL(ahci_dev_classify); 1173 1174 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1175 u32 opts) 1176 { 1177 dma_addr_t cmd_tbl_dma; 1178 1179 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1180 1181 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1182 pp->cmd_slot[tag].status = 0; 1183 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1184 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1185 } 1186 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1187 1188 int ahci_kick_engine(struct ata_port *ap) 1189 { 1190 void __iomem *port_mmio = ahci_port_base(ap); 1191 struct ahci_host_priv *hpriv = ap->host->private_data; 1192 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1193 u32 tmp; 1194 int busy, rc; 1195 1196 /* stop engine */ 1197 rc = ahci_stop_engine(ap); 1198 if (rc) 1199 goto out_restart; 1200 1201 /* need to do CLO? 1202 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1203 */ 1204 busy = status & (ATA_BUSY | ATA_DRQ); 1205 if (!busy && !sata_pmp_attached(ap)) { 1206 rc = 0; 1207 goto out_restart; 1208 } 1209 1210 if (!(hpriv->cap & HOST_CAP_CLO)) { 1211 rc = -EOPNOTSUPP; 1212 goto out_restart; 1213 } 1214 1215 /* perform CLO */ 1216 tmp = readl(port_mmio + PORT_CMD); 1217 tmp |= PORT_CMD_CLO; 1218 writel(tmp, port_mmio + PORT_CMD); 1219 1220 rc = 0; 1221 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1222 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1223 if (tmp & PORT_CMD_CLO) 1224 rc = -EIO; 1225 1226 /* restart engine */ 1227 out_restart: 1228 ahci_start_engine(ap); 1229 return rc; 1230 } 1231 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1232 1233 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1234 struct ata_taskfile *tf, int is_cmd, u16 flags, 1235 unsigned long timeout_msec) 1236 { 1237 const u32 cmd_fis_len = 5; /* five dwords */ 1238 struct ahci_port_priv *pp = ap->private_data; 1239 void __iomem *port_mmio = ahci_port_base(ap); 1240 u8 *fis = pp->cmd_tbl; 1241 u32 tmp; 1242 1243 /* prep the command */ 1244 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1245 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1246 1247 /* issue & wait */ 1248 writel(1, port_mmio + PORT_CMD_ISSUE); 1249 1250 if (timeout_msec) { 1251 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1252 0x1, 0x1, 1, timeout_msec); 1253 if (tmp & 0x1) { 1254 ahci_kick_engine(ap); 1255 return -EBUSY; 1256 } 1257 } else 1258 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1259 1260 return 0; 1261 } 1262 1263 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1264 int pmp, unsigned long deadline, 1265 int (*check_ready)(struct ata_link *link)) 1266 { 1267 struct ata_port *ap = link->ap; 1268 struct ahci_host_priv *hpriv = ap->host->private_data; 1269 const char *reason = NULL; 1270 unsigned long now, msecs; 1271 struct ata_taskfile tf; 1272 int rc; 1273 1274 DPRINTK("ENTER\n"); 1275 1276 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1277 rc = ahci_kick_engine(ap); 1278 if (rc && rc != -EOPNOTSUPP) 1279 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc); 1280 1281 ata_tf_init(link->device, &tf); 1282 1283 /* issue the first D2H Register FIS */ 1284 msecs = 0; 1285 now = jiffies; 1286 if (time_after(deadline, now)) 1287 msecs = jiffies_to_msecs(deadline - now); 1288 1289 tf.ctl |= ATA_SRST; 1290 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1291 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1292 rc = -EIO; 1293 reason = "1st FIS failed"; 1294 goto fail; 1295 } 1296 1297 /* spec says at least 5us, but be generous and sleep for 1ms */ 1298 ata_msleep(ap, 1); 1299 1300 /* issue the second D2H Register FIS */ 1301 tf.ctl &= ~ATA_SRST; 1302 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1303 1304 /* wait for link to become ready */ 1305 rc = ata_wait_after_reset(link, deadline, check_ready); 1306 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1307 /* 1308 * Workaround for cases where link online status can't 1309 * be trusted. Treat device readiness timeout as link 1310 * offline. 1311 */ 1312 ata_link_info(link, "device not ready, treating as offline\n"); 1313 *class = ATA_DEV_NONE; 1314 } else if (rc) { 1315 /* link occupied, -ENODEV too is an error */ 1316 reason = "device not ready"; 1317 goto fail; 1318 } else 1319 *class = ahci_dev_classify(ap); 1320 1321 DPRINTK("EXIT, class=%u\n", *class); 1322 return 0; 1323 1324 fail: 1325 ata_link_err(link, "softreset failed (%s)\n", reason); 1326 return rc; 1327 } 1328 1329 int ahci_check_ready(struct ata_link *link) 1330 { 1331 void __iomem *port_mmio = ahci_port_base(link->ap); 1332 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1333 1334 return ata_check_ready(status); 1335 } 1336 EXPORT_SYMBOL_GPL(ahci_check_ready); 1337 1338 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1339 unsigned long deadline) 1340 { 1341 int pmp = sata_srst_pmp(link); 1342 1343 DPRINTK("ENTER\n"); 1344 1345 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1346 } 1347 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1348 1349 static int ahci_bad_pmp_check_ready(struct ata_link *link) 1350 { 1351 void __iomem *port_mmio = ahci_port_base(link->ap); 1352 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1353 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1354 1355 /* 1356 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1357 * which can save timeout delay. 1358 */ 1359 if (irq_status & PORT_IRQ_BAD_PMP) 1360 return -EIO; 1361 1362 return ata_check_ready(status); 1363 } 1364 1365 int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 1366 unsigned long deadline) 1367 { 1368 struct ata_port *ap = link->ap; 1369 void __iomem *port_mmio = ahci_port_base(ap); 1370 int pmp = sata_srst_pmp(link); 1371 int rc; 1372 u32 irq_sts; 1373 1374 DPRINTK("ENTER\n"); 1375 1376 rc = ahci_do_softreset(link, class, pmp, deadline, 1377 ahci_bad_pmp_check_ready); 1378 1379 /* 1380 * Soft reset fails with IPMS set when PMP is enabled but 1381 * SATA HDD/ODD is connected to SATA port, do soft reset 1382 * again to port 0. 1383 */ 1384 if (rc == -EIO) { 1385 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1386 if (irq_sts & PORT_IRQ_BAD_PMP) { 1387 ata_link_warn(link, 1388 "applying PMP SRST workaround " 1389 "and retrying\n"); 1390 rc = ahci_do_softreset(link, class, 0, deadline, 1391 ahci_check_ready); 1392 } 1393 } 1394 1395 return rc; 1396 } 1397 1398 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1399 unsigned long deadline) 1400 { 1401 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1402 struct ata_port *ap = link->ap; 1403 struct ahci_port_priv *pp = ap->private_data; 1404 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1405 struct ata_taskfile tf; 1406 bool online; 1407 int rc; 1408 1409 DPRINTK("ENTER\n"); 1410 1411 ahci_stop_engine(ap); 1412 1413 /* clear D2H reception area to properly wait for D2H FIS */ 1414 ata_tf_init(link->device, &tf); 1415 tf.command = 0x80; 1416 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1417 1418 rc = sata_link_hardreset(link, timing, deadline, &online, 1419 ahci_check_ready); 1420 1421 ahci_start_engine(ap); 1422 1423 if (online) 1424 *class = ahci_dev_classify(ap); 1425 1426 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1427 return rc; 1428 } 1429 1430 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1431 { 1432 struct ata_port *ap = link->ap; 1433 void __iomem *port_mmio = ahci_port_base(ap); 1434 u32 new_tmp, tmp; 1435 1436 ata_std_postreset(link, class); 1437 1438 /* Make sure port's ATAPI bit is set appropriately */ 1439 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1440 if (*class == ATA_DEV_ATAPI) 1441 new_tmp |= PORT_CMD_ATAPI; 1442 else 1443 new_tmp &= ~PORT_CMD_ATAPI; 1444 if (new_tmp != tmp) { 1445 writel(new_tmp, port_mmio + PORT_CMD); 1446 readl(port_mmio + PORT_CMD); /* flush */ 1447 } 1448 } 1449 1450 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1451 { 1452 struct scatterlist *sg; 1453 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1454 unsigned int si; 1455 1456 VPRINTK("ENTER\n"); 1457 1458 /* 1459 * Next, the S/G list. 1460 */ 1461 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1462 dma_addr_t addr = sg_dma_address(sg); 1463 u32 sg_len = sg_dma_len(sg); 1464 1465 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1466 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1467 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1468 } 1469 1470 return si; 1471 } 1472 1473 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1474 { 1475 struct ata_port *ap = qc->ap; 1476 struct ahci_port_priv *pp = ap->private_data; 1477 1478 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1479 return ata_std_qc_defer(qc); 1480 else 1481 return sata_pmp_qc_defer_cmd_switch(qc); 1482 } 1483 1484 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1485 { 1486 struct ata_port *ap = qc->ap; 1487 struct ahci_port_priv *pp = ap->private_data; 1488 int is_atapi = ata_is_atapi(qc->tf.protocol); 1489 void *cmd_tbl; 1490 u32 opts; 1491 const u32 cmd_fis_len = 5; /* five dwords */ 1492 unsigned int n_elem; 1493 1494 /* 1495 * Fill in command table information. First, the header, 1496 * a SATA Register - Host to Device command FIS. 1497 */ 1498 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1499 1500 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1501 if (is_atapi) { 1502 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1503 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1504 } 1505 1506 n_elem = 0; 1507 if (qc->flags & ATA_QCFLAG_DMAMAP) 1508 n_elem = ahci_fill_sg(qc, cmd_tbl); 1509 1510 /* 1511 * Fill in command slot information. 1512 */ 1513 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1514 if (qc->tf.flags & ATA_TFLAG_WRITE) 1515 opts |= AHCI_CMD_WRITE; 1516 if (is_atapi) 1517 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1518 1519 ahci_fill_cmd_slot(pp, qc->tag, opts); 1520 } 1521 1522 static void ahci_fbs_dec_intr(struct ata_port *ap) 1523 { 1524 struct ahci_port_priv *pp = ap->private_data; 1525 void __iomem *port_mmio = ahci_port_base(ap); 1526 u32 fbs = readl(port_mmio + PORT_FBS); 1527 int retries = 3; 1528 1529 DPRINTK("ENTER\n"); 1530 BUG_ON(!pp->fbs_enabled); 1531 1532 /* time to wait for DEC is not specified by AHCI spec, 1533 * add a retry loop for safety. 1534 */ 1535 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1536 fbs = readl(port_mmio + PORT_FBS); 1537 while ((fbs & PORT_FBS_DEC) && retries--) { 1538 udelay(1); 1539 fbs = readl(port_mmio + PORT_FBS); 1540 } 1541 1542 if (fbs & PORT_FBS_DEC) 1543 dev_err(ap->host->dev, "failed to clear device error\n"); 1544 } 1545 1546 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1547 { 1548 struct ahci_host_priv *hpriv = ap->host->private_data; 1549 struct ahci_port_priv *pp = ap->private_data; 1550 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1551 struct ata_link *link = NULL; 1552 struct ata_queued_cmd *active_qc; 1553 struct ata_eh_info *active_ehi; 1554 bool fbs_need_dec = false; 1555 u32 serror; 1556 1557 /* determine active link with error */ 1558 if (pp->fbs_enabled) { 1559 void __iomem *port_mmio = ahci_port_base(ap); 1560 u32 fbs = readl(port_mmio + PORT_FBS); 1561 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1562 1563 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) && 1564 ata_link_online(&ap->pmp_link[pmp])) { 1565 link = &ap->pmp_link[pmp]; 1566 fbs_need_dec = true; 1567 } 1568 1569 } else 1570 ata_for_each_link(link, ap, EDGE) 1571 if (ata_link_active(link)) 1572 break; 1573 1574 if (!link) 1575 link = &ap->link; 1576 1577 active_qc = ata_qc_from_tag(ap, link->active_tag); 1578 active_ehi = &link->eh_info; 1579 1580 /* record irq stat */ 1581 ata_ehi_clear_desc(host_ehi); 1582 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1583 1584 /* AHCI needs SError cleared; otherwise, it might lock up */ 1585 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1586 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1587 host_ehi->serror |= serror; 1588 1589 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1590 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1591 irq_stat &= ~PORT_IRQ_IF_ERR; 1592 1593 if (irq_stat & PORT_IRQ_TF_ERR) { 1594 /* If qc is active, charge it; otherwise, the active 1595 * link. There's no active qc on NCQ errors. It will 1596 * be determined by EH by reading log page 10h. 1597 */ 1598 if (active_qc) 1599 active_qc->err_mask |= AC_ERR_DEV; 1600 else 1601 active_ehi->err_mask |= AC_ERR_DEV; 1602 1603 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1604 host_ehi->serror &= ~SERR_INTERNAL; 1605 } 1606 1607 if (irq_stat & PORT_IRQ_UNK_FIS) { 1608 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); 1609 1610 active_ehi->err_mask |= AC_ERR_HSM; 1611 active_ehi->action |= ATA_EH_RESET; 1612 ata_ehi_push_desc(active_ehi, 1613 "unknown FIS %08x %08x %08x %08x" , 1614 unk[0], unk[1], unk[2], unk[3]); 1615 } 1616 1617 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1618 active_ehi->err_mask |= AC_ERR_HSM; 1619 active_ehi->action |= ATA_EH_RESET; 1620 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1621 } 1622 1623 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1624 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1625 host_ehi->action |= ATA_EH_RESET; 1626 ata_ehi_push_desc(host_ehi, "host bus error"); 1627 } 1628 1629 if (irq_stat & PORT_IRQ_IF_ERR) { 1630 if (fbs_need_dec) 1631 active_ehi->err_mask |= AC_ERR_DEV; 1632 else { 1633 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1634 host_ehi->action |= ATA_EH_RESET; 1635 } 1636 1637 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1638 } 1639 1640 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1641 ata_ehi_hotplugged(host_ehi); 1642 ata_ehi_push_desc(host_ehi, "%s", 1643 irq_stat & PORT_IRQ_CONNECT ? 1644 "connection status changed" : "PHY RDY changed"); 1645 } 1646 1647 /* okay, let's hand over to EH */ 1648 1649 if (irq_stat & PORT_IRQ_FREEZE) 1650 ata_port_freeze(ap); 1651 else if (fbs_need_dec) { 1652 ata_link_abort(link); 1653 ahci_fbs_dec_intr(ap); 1654 } else 1655 ata_port_abort(ap); 1656 } 1657 1658 static void ahci_handle_port_interrupt(struct ata_port *ap, 1659 void __iomem *port_mmio, u32 status) 1660 { 1661 struct ata_eh_info *ehi = &ap->link.eh_info; 1662 struct ahci_port_priv *pp = ap->private_data; 1663 struct ahci_host_priv *hpriv = ap->host->private_data; 1664 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1665 u32 qc_active = 0; 1666 int rc; 1667 1668 /* ignore BAD_PMP while resetting */ 1669 if (unlikely(resetting)) 1670 status &= ~PORT_IRQ_BAD_PMP; 1671 1672 /* if LPM is enabled, PHYRDY doesn't mean anything */ 1673 if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) { 1674 status &= ~PORT_IRQ_PHYRDY; 1675 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1676 } 1677 1678 if (unlikely(status & PORT_IRQ_ERROR)) { 1679 ahci_error_intr(ap, status); 1680 return; 1681 } 1682 1683 if (status & PORT_IRQ_SDB_FIS) { 1684 /* If SNotification is available, leave notification 1685 * handling to sata_async_notification(). If not, 1686 * emulate it by snooping SDB FIS RX area. 1687 * 1688 * Snooping FIS RX area is probably cheaper than 1689 * poking SNotification but some constrollers which 1690 * implement SNotification, ICH9 for example, don't 1691 * store AN SDB FIS into receive area. 1692 */ 1693 if (hpriv->cap & HOST_CAP_SNTF) 1694 sata_async_notification(ap); 1695 else { 1696 /* If the 'N' bit in word 0 of the FIS is set, 1697 * we just received asynchronous notification. 1698 * Tell libata about it. 1699 * 1700 * Lack of SNotification should not appear in 1701 * ahci 1.2, so the workaround is unnecessary 1702 * when FBS is enabled. 1703 */ 1704 if (pp->fbs_enabled) 1705 WARN_ON_ONCE(1); 1706 else { 1707 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1708 u32 f0 = le32_to_cpu(f[0]); 1709 if (f0 & (1 << 15)) 1710 sata_async_notification(ap); 1711 } 1712 } 1713 } 1714 1715 /* pp->active_link is not reliable once FBS is enabled, both 1716 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1717 * NCQ and non-NCQ commands may be in flight at the same time. 1718 */ 1719 if (pp->fbs_enabled) { 1720 if (ap->qc_active) { 1721 qc_active = readl(port_mmio + PORT_SCR_ACT); 1722 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1723 } 1724 } else { 1725 /* pp->active_link is valid iff any command is in flight */ 1726 if (ap->qc_active && pp->active_link->sactive) 1727 qc_active = readl(port_mmio + PORT_SCR_ACT); 1728 else 1729 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1730 } 1731 1732 1733 rc = ata_qc_complete_multiple(ap, qc_active); 1734 1735 /* while resetting, invalid completions are expected */ 1736 if (unlikely(rc < 0 && !resetting)) { 1737 ehi->err_mask |= AC_ERR_HSM; 1738 ehi->action |= ATA_EH_RESET; 1739 ata_port_freeze(ap); 1740 } 1741 } 1742 1743 void ahci_port_intr(struct ata_port *ap) 1744 { 1745 void __iomem *port_mmio = ahci_port_base(ap); 1746 u32 status; 1747 1748 status = readl(port_mmio + PORT_IRQ_STAT); 1749 writel(status, port_mmio + PORT_IRQ_STAT); 1750 1751 ahci_handle_port_interrupt(ap, port_mmio, status); 1752 } 1753 1754 irqreturn_t ahci_thread_fn(int irq, void *dev_instance) 1755 { 1756 struct ata_port *ap = dev_instance; 1757 struct ahci_port_priv *pp = ap->private_data; 1758 void __iomem *port_mmio = ahci_port_base(ap); 1759 unsigned long flags; 1760 u32 status; 1761 1762 spin_lock_irqsave(&ap->host->lock, flags); 1763 status = pp->intr_status; 1764 if (status) 1765 pp->intr_status = 0; 1766 spin_unlock_irqrestore(&ap->host->lock, flags); 1767 1768 spin_lock_bh(ap->lock); 1769 ahci_handle_port_interrupt(ap, port_mmio, status); 1770 spin_unlock_bh(ap->lock); 1771 1772 return IRQ_HANDLED; 1773 } 1774 EXPORT_SYMBOL_GPL(ahci_thread_fn); 1775 1776 void ahci_hw_port_interrupt(struct ata_port *ap) 1777 { 1778 void __iomem *port_mmio = ahci_port_base(ap); 1779 struct ahci_port_priv *pp = ap->private_data; 1780 u32 status; 1781 1782 status = readl(port_mmio + PORT_IRQ_STAT); 1783 writel(status, port_mmio + PORT_IRQ_STAT); 1784 1785 pp->intr_status |= status; 1786 } 1787 1788 irqreturn_t ahci_hw_interrupt(int irq, void *dev_instance) 1789 { 1790 struct ata_port *ap_this = dev_instance; 1791 struct ahci_port_priv *pp = ap_this->private_data; 1792 struct ata_host *host = ap_this->host; 1793 struct ahci_host_priv *hpriv = host->private_data; 1794 void __iomem *mmio = hpriv->mmio; 1795 unsigned int i; 1796 u32 irq_stat, irq_masked; 1797 1798 VPRINTK("ENTER\n"); 1799 1800 spin_lock(&host->lock); 1801 1802 irq_stat = readl(mmio + HOST_IRQ_STAT); 1803 1804 if (!irq_stat) { 1805 u32 status = pp->intr_status; 1806 1807 spin_unlock(&host->lock); 1808 1809 VPRINTK("EXIT\n"); 1810 1811 return status ? IRQ_WAKE_THREAD : IRQ_NONE; 1812 } 1813 1814 irq_masked = irq_stat & hpriv->port_map; 1815 1816 for (i = 0; i < host->n_ports; i++) { 1817 struct ata_port *ap; 1818 1819 if (!(irq_masked & (1 << i))) 1820 continue; 1821 1822 ap = host->ports[i]; 1823 if (ap) { 1824 ahci_hw_port_interrupt(ap); 1825 VPRINTK("port %u\n", i); 1826 } else { 1827 VPRINTK("port %u (no irq)\n", i); 1828 if (ata_ratelimit()) 1829 dev_warn(host->dev, 1830 "interrupt on disabled port %u\n", i); 1831 } 1832 } 1833 1834 writel(irq_stat, mmio + HOST_IRQ_STAT); 1835 1836 spin_unlock(&host->lock); 1837 1838 VPRINTK("EXIT\n"); 1839 1840 return IRQ_WAKE_THREAD; 1841 } 1842 EXPORT_SYMBOL_GPL(ahci_hw_interrupt); 1843 1844 irqreturn_t ahci_interrupt(int irq, void *dev_instance) 1845 { 1846 struct ata_host *host = dev_instance; 1847 struct ahci_host_priv *hpriv; 1848 unsigned int i, handled = 0; 1849 void __iomem *mmio; 1850 u32 irq_stat, irq_masked; 1851 1852 VPRINTK("ENTER\n"); 1853 1854 hpriv = host->private_data; 1855 mmio = hpriv->mmio; 1856 1857 /* sigh. 0xffffffff is a valid return from h/w */ 1858 irq_stat = readl(mmio + HOST_IRQ_STAT); 1859 if (!irq_stat) 1860 return IRQ_NONE; 1861 1862 irq_masked = irq_stat & hpriv->port_map; 1863 1864 spin_lock(&host->lock); 1865 1866 for (i = 0; i < host->n_ports; i++) { 1867 struct ata_port *ap; 1868 1869 if (!(irq_masked & (1 << i))) 1870 continue; 1871 1872 ap = host->ports[i]; 1873 if (ap) { 1874 ahci_port_intr(ap); 1875 VPRINTK("port %u\n", i); 1876 } else { 1877 VPRINTK("port %u (no irq)\n", i); 1878 if (ata_ratelimit()) 1879 dev_warn(host->dev, 1880 "interrupt on disabled port %u\n", i); 1881 } 1882 1883 handled = 1; 1884 } 1885 1886 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1887 * it should be cleared after all the port events are cleared; 1888 * otherwise, it will raise a spurious interrupt after each 1889 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1890 * information. 1891 * 1892 * Also, use the unmasked value to clear interrupt as spurious 1893 * pending event on a dummy port might cause screaming IRQ. 1894 */ 1895 writel(irq_stat, mmio + HOST_IRQ_STAT); 1896 1897 spin_unlock(&host->lock); 1898 1899 VPRINTK("EXIT\n"); 1900 1901 return IRQ_RETVAL(handled); 1902 } 1903 EXPORT_SYMBOL_GPL(ahci_interrupt); 1904 1905 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1906 { 1907 struct ata_port *ap = qc->ap; 1908 void __iomem *port_mmio = ahci_port_base(ap); 1909 struct ahci_port_priv *pp = ap->private_data; 1910 1911 /* Keep track of the currently active link. It will be used 1912 * in completion path to determine whether NCQ phase is in 1913 * progress. 1914 */ 1915 pp->active_link = qc->dev->link; 1916 1917 if (qc->tf.protocol == ATA_PROT_NCQ) 1918 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 1919 1920 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 1921 u32 fbs = readl(port_mmio + PORT_FBS); 1922 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1923 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 1924 writel(fbs, port_mmio + PORT_FBS); 1925 pp->fbs_last_dev = qc->dev->link->pmp; 1926 } 1927 1928 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 1929 1930 ahci_sw_activity(qc->dev->link); 1931 1932 return 0; 1933 } 1934 1935 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 1936 { 1937 struct ahci_port_priv *pp = qc->ap->private_data; 1938 u8 *rx_fis = pp->rx_fis; 1939 1940 if (pp->fbs_enabled) 1941 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 1942 1943 /* 1944 * After a successful execution of an ATA PIO data-in command, 1945 * the device doesn't send D2H Reg FIS to update the TF and 1946 * the host should take TF and E_Status from the preceding PIO 1947 * Setup FIS. 1948 */ 1949 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 1950 !(qc->flags & ATA_QCFLAG_FAILED)) { 1951 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 1952 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 1953 } else 1954 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 1955 1956 return true; 1957 } 1958 1959 static void ahci_freeze(struct ata_port *ap) 1960 { 1961 void __iomem *port_mmio = ahci_port_base(ap); 1962 1963 /* turn IRQ off */ 1964 writel(0, port_mmio + PORT_IRQ_MASK); 1965 } 1966 1967 static void ahci_thaw(struct ata_port *ap) 1968 { 1969 struct ahci_host_priv *hpriv = ap->host->private_data; 1970 void __iomem *mmio = hpriv->mmio; 1971 void __iomem *port_mmio = ahci_port_base(ap); 1972 u32 tmp; 1973 struct ahci_port_priv *pp = ap->private_data; 1974 1975 /* clear IRQ */ 1976 tmp = readl(port_mmio + PORT_IRQ_STAT); 1977 writel(tmp, port_mmio + PORT_IRQ_STAT); 1978 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 1979 1980 /* turn IRQ back on */ 1981 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1982 } 1983 1984 static void ahci_error_handler(struct ata_port *ap) 1985 { 1986 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 1987 /* restart engine */ 1988 ahci_stop_engine(ap); 1989 ahci_start_engine(ap); 1990 } 1991 1992 sata_pmp_error_handler(ap); 1993 1994 if (!ata_dev_enabled(ap->link.device)) 1995 ahci_stop_engine(ap); 1996 } 1997 1998 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 1999 { 2000 struct ata_port *ap = qc->ap; 2001 2002 /* make DMA engine forget about the failed command */ 2003 if (qc->flags & ATA_QCFLAG_FAILED) 2004 ahci_kick_engine(ap); 2005 } 2006 2007 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep) 2008 { 2009 void __iomem *port_mmio = ahci_port_base(ap); 2010 struct ata_device *dev = ap->link.device; 2011 u32 devslp, dm, dito, mdat, deto; 2012 int rc; 2013 unsigned int err_mask; 2014 2015 devslp = readl(port_mmio + PORT_DEVSLP); 2016 if (!(devslp & PORT_DEVSLP_DSP)) { 2017 dev_err(ap->host->dev, "port does not support device sleep\n"); 2018 return; 2019 } 2020 2021 /* disable device sleep */ 2022 if (!sleep) { 2023 if (devslp & PORT_DEVSLP_ADSE) { 2024 writel(devslp & ~PORT_DEVSLP_ADSE, 2025 port_mmio + PORT_DEVSLP); 2026 err_mask = ata_dev_set_feature(dev, 2027 SETFEATURES_SATA_DISABLE, 2028 SATA_DEVSLP); 2029 if (err_mask && err_mask != AC_ERR_DEV) 2030 ata_dev_warn(dev, "failed to disable DEVSLP\n"); 2031 } 2032 return; 2033 } 2034 2035 /* device sleep was already enabled */ 2036 if (devslp & PORT_DEVSLP_ADSE) 2037 return; 2038 2039 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */ 2040 rc = ahci_stop_engine(ap); 2041 if (rc) 2042 return; 2043 2044 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET; 2045 dito = devslp_idle_timeout / (dm + 1); 2046 if (dito > 0x3ff) 2047 dito = 0x3ff; 2048 2049 /* Use the nominal value 10 ms if the read MDAT is zero, 2050 * the nominal value of DETO is 20 ms. 2051 */ 2052 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] & 2053 ATA_LOG_DEVSLP_VALID_MASK) { 2054 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] & 2055 ATA_LOG_DEVSLP_MDAT_MASK; 2056 if (!mdat) 2057 mdat = 10; 2058 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO]; 2059 if (!deto) 2060 deto = 20; 2061 } else { 2062 mdat = 10; 2063 deto = 20; 2064 } 2065 2066 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) | 2067 (mdat << PORT_DEVSLP_MDAT_OFFSET) | 2068 (deto << PORT_DEVSLP_DETO_OFFSET) | 2069 PORT_DEVSLP_ADSE); 2070 writel(devslp, port_mmio + PORT_DEVSLP); 2071 2072 ahci_start_engine(ap); 2073 2074 /* enable device sleep feature for the drive */ 2075 err_mask = ata_dev_set_feature(dev, 2076 SETFEATURES_SATA_ENABLE, 2077 SATA_DEVSLP); 2078 if (err_mask && err_mask != AC_ERR_DEV) 2079 ata_dev_warn(dev, "failed to enable DEVSLP\n"); 2080 } 2081 2082 static void ahci_enable_fbs(struct ata_port *ap) 2083 { 2084 struct ahci_port_priv *pp = ap->private_data; 2085 void __iomem *port_mmio = ahci_port_base(ap); 2086 u32 fbs; 2087 int rc; 2088 2089 if (!pp->fbs_supported) 2090 return; 2091 2092 fbs = readl(port_mmio + PORT_FBS); 2093 if (fbs & PORT_FBS_EN) { 2094 pp->fbs_enabled = true; 2095 pp->fbs_last_dev = -1; /* initialization */ 2096 return; 2097 } 2098 2099 rc = ahci_stop_engine(ap); 2100 if (rc) 2101 return; 2102 2103 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 2104 fbs = readl(port_mmio + PORT_FBS); 2105 if (fbs & PORT_FBS_EN) { 2106 dev_info(ap->host->dev, "FBS is enabled\n"); 2107 pp->fbs_enabled = true; 2108 pp->fbs_last_dev = -1; /* initialization */ 2109 } else 2110 dev_err(ap->host->dev, "Failed to enable FBS\n"); 2111 2112 ahci_start_engine(ap); 2113 } 2114 2115 static void ahci_disable_fbs(struct ata_port *ap) 2116 { 2117 struct ahci_port_priv *pp = ap->private_data; 2118 void __iomem *port_mmio = ahci_port_base(ap); 2119 u32 fbs; 2120 int rc; 2121 2122 if (!pp->fbs_supported) 2123 return; 2124 2125 fbs = readl(port_mmio + PORT_FBS); 2126 if ((fbs & PORT_FBS_EN) == 0) { 2127 pp->fbs_enabled = false; 2128 return; 2129 } 2130 2131 rc = ahci_stop_engine(ap); 2132 if (rc) 2133 return; 2134 2135 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 2136 fbs = readl(port_mmio + PORT_FBS); 2137 if (fbs & PORT_FBS_EN) 2138 dev_err(ap->host->dev, "Failed to disable FBS\n"); 2139 else { 2140 dev_info(ap->host->dev, "FBS is disabled\n"); 2141 pp->fbs_enabled = false; 2142 } 2143 2144 ahci_start_engine(ap); 2145 } 2146 2147 static void ahci_pmp_attach(struct ata_port *ap) 2148 { 2149 void __iomem *port_mmio = ahci_port_base(ap); 2150 struct ahci_port_priv *pp = ap->private_data; 2151 u32 cmd; 2152 2153 cmd = readl(port_mmio + PORT_CMD); 2154 cmd |= PORT_CMD_PMP; 2155 writel(cmd, port_mmio + PORT_CMD); 2156 2157 ahci_enable_fbs(ap); 2158 2159 pp->intr_mask |= PORT_IRQ_BAD_PMP; 2160 2161 /* 2162 * We must not change the port interrupt mask register if the 2163 * port is marked frozen, the value in pp->intr_mask will be 2164 * restored later when the port is thawed. 2165 * 2166 * Note that during initialization, the port is marked as 2167 * frozen since the irq handler is not yet registered. 2168 */ 2169 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2170 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2171 } 2172 2173 static void ahci_pmp_detach(struct ata_port *ap) 2174 { 2175 void __iomem *port_mmio = ahci_port_base(ap); 2176 struct ahci_port_priv *pp = ap->private_data; 2177 u32 cmd; 2178 2179 ahci_disable_fbs(ap); 2180 2181 cmd = readl(port_mmio + PORT_CMD); 2182 cmd &= ~PORT_CMD_PMP; 2183 writel(cmd, port_mmio + PORT_CMD); 2184 2185 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 2186 2187 /* see comment above in ahci_pmp_attach() */ 2188 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2189 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2190 } 2191 2192 int ahci_port_resume(struct ata_port *ap) 2193 { 2194 ahci_power_up(ap); 2195 ahci_start_port(ap); 2196 2197 if (sata_pmp_attached(ap)) 2198 ahci_pmp_attach(ap); 2199 else 2200 ahci_pmp_detach(ap); 2201 2202 return 0; 2203 } 2204 EXPORT_SYMBOL_GPL(ahci_port_resume); 2205 2206 #ifdef CONFIG_PM 2207 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2208 { 2209 const char *emsg = NULL; 2210 int rc; 2211 2212 rc = ahci_deinit_port(ap, &emsg); 2213 if (rc == 0) 2214 ahci_power_down(ap); 2215 else { 2216 ata_port_err(ap, "%s (%d)\n", emsg, rc); 2217 ata_port_freeze(ap); 2218 } 2219 2220 return rc; 2221 } 2222 #endif 2223 2224 static int ahci_port_start(struct ata_port *ap) 2225 { 2226 struct ahci_host_priv *hpriv = ap->host->private_data; 2227 struct device *dev = ap->host->dev; 2228 struct ahci_port_priv *pp; 2229 void *mem; 2230 dma_addr_t mem_dma; 2231 size_t dma_sz, rx_fis_sz; 2232 2233 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2234 if (!pp) 2235 return -ENOMEM; 2236 2237 /* check FBS capability */ 2238 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2239 void __iomem *port_mmio = ahci_port_base(ap); 2240 u32 cmd = readl(port_mmio + PORT_CMD); 2241 if (cmd & PORT_CMD_FBSCP) 2242 pp->fbs_supported = true; 2243 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2244 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 2245 ap->port_no); 2246 pp->fbs_supported = true; 2247 } else 2248 dev_warn(dev, "port %d is not capable of FBS\n", 2249 ap->port_no); 2250 } 2251 2252 if (pp->fbs_supported) { 2253 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2254 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2255 } else { 2256 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2257 rx_fis_sz = AHCI_RX_FIS_SZ; 2258 } 2259 2260 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2261 if (!mem) 2262 return -ENOMEM; 2263 memset(mem, 0, dma_sz); 2264 2265 /* 2266 * First item in chunk of DMA memory: 32-slot command table, 2267 * 32 bytes each in size 2268 */ 2269 pp->cmd_slot = mem; 2270 pp->cmd_slot_dma = mem_dma; 2271 2272 mem += AHCI_CMD_SLOT_SZ; 2273 mem_dma += AHCI_CMD_SLOT_SZ; 2274 2275 /* 2276 * Second item: Received-FIS area 2277 */ 2278 pp->rx_fis = mem; 2279 pp->rx_fis_dma = mem_dma; 2280 2281 mem += rx_fis_sz; 2282 mem_dma += rx_fis_sz; 2283 2284 /* 2285 * Third item: data area for storing a single command 2286 * and its scatter-gather table 2287 */ 2288 pp->cmd_tbl = mem; 2289 pp->cmd_tbl_dma = mem_dma; 2290 2291 /* 2292 * Save off initial list of interrupts to be enabled. 2293 * This could be changed later 2294 */ 2295 pp->intr_mask = DEF_PORT_IRQ; 2296 2297 /* 2298 * Switch to per-port locking in case each port has its own MSI vector. 2299 */ 2300 if ((hpriv->flags & AHCI_HFLAG_MULTI_MSI)) { 2301 spin_lock_init(&pp->lock); 2302 ap->lock = &pp->lock; 2303 } 2304 2305 ap->private_data = pp; 2306 2307 /* engage engines, captain */ 2308 return ahci_port_resume(ap); 2309 } 2310 2311 static void ahci_port_stop(struct ata_port *ap) 2312 { 2313 const char *emsg = NULL; 2314 int rc; 2315 2316 /* de-initialize port */ 2317 rc = ahci_deinit_port(ap, &emsg); 2318 if (rc) 2319 ata_port_warn(ap, "%s (%d)\n", emsg, rc); 2320 } 2321 2322 void ahci_print_info(struct ata_host *host, const char *scc_s) 2323 { 2324 struct ahci_host_priv *hpriv = host->private_data; 2325 void __iomem *mmio = hpriv->mmio; 2326 u32 vers, cap, cap2, impl, speed; 2327 const char *speed_s; 2328 2329 vers = readl(mmio + HOST_VERSION); 2330 cap = hpriv->cap; 2331 cap2 = hpriv->cap2; 2332 impl = hpriv->port_map; 2333 2334 speed = (cap >> 20) & 0xf; 2335 if (speed == 1) 2336 speed_s = "1.5"; 2337 else if (speed == 2) 2338 speed_s = "3"; 2339 else if (speed == 3) 2340 speed_s = "6"; 2341 else 2342 speed_s = "?"; 2343 2344 dev_info(host->dev, 2345 "AHCI %02x%02x.%02x%02x " 2346 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2347 , 2348 2349 (vers >> 24) & 0xff, 2350 (vers >> 16) & 0xff, 2351 (vers >> 8) & 0xff, 2352 vers & 0xff, 2353 2354 ((cap >> 8) & 0x1f) + 1, 2355 (cap & 0x1f) + 1, 2356 speed_s, 2357 impl, 2358 scc_s); 2359 2360 dev_info(host->dev, 2361 "flags: " 2362 "%s%s%s%s%s%s%s" 2363 "%s%s%s%s%s%s%s" 2364 "%s%s%s%s%s%s%s" 2365 "%s%s\n" 2366 , 2367 2368 cap & HOST_CAP_64 ? "64bit " : "", 2369 cap & HOST_CAP_NCQ ? "ncq " : "", 2370 cap & HOST_CAP_SNTF ? "sntf " : "", 2371 cap & HOST_CAP_MPS ? "ilck " : "", 2372 cap & HOST_CAP_SSS ? "stag " : "", 2373 cap & HOST_CAP_ALPM ? "pm " : "", 2374 cap & HOST_CAP_LED ? "led " : "", 2375 cap & HOST_CAP_CLO ? "clo " : "", 2376 cap & HOST_CAP_ONLY ? "only " : "", 2377 cap & HOST_CAP_PMP ? "pmp " : "", 2378 cap & HOST_CAP_FBS ? "fbs " : "", 2379 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2380 cap & HOST_CAP_SSC ? "slum " : "", 2381 cap & HOST_CAP_PART ? "part " : "", 2382 cap & HOST_CAP_CCC ? "ccc " : "", 2383 cap & HOST_CAP_EMS ? "ems " : "", 2384 cap & HOST_CAP_SXS ? "sxs " : "", 2385 cap2 & HOST_CAP2_DESO ? "deso " : "", 2386 cap2 & HOST_CAP2_SADM ? "sadm " : "", 2387 cap2 & HOST_CAP2_SDS ? "sds " : "", 2388 cap2 & HOST_CAP2_APST ? "apst " : "", 2389 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2390 cap2 & HOST_CAP2_BOH ? "boh " : "" 2391 ); 2392 } 2393 EXPORT_SYMBOL_GPL(ahci_print_info); 2394 2395 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2396 struct ata_port_info *pi) 2397 { 2398 u8 messages; 2399 void __iomem *mmio = hpriv->mmio; 2400 u32 em_loc = readl(mmio + HOST_EM_LOC); 2401 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2402 2403 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2404 return; 2405 2406 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2407 2408 if (messages) { 2409 /* store em_loc */ 2410 hpriv->em_loc = ((em_loc >> 16) * 4); 2411 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2412 hpriv->em_msg_type = messages; 2413 pi->flags |= ATA_FLAG_EM; 2414 if (!(em_ctl & EM_CTL_ALHD)) 2415 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2416 } 2417 } 2418 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2419 2420 MODULE_AUTHOR("Jeff Garzik"); 2421 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2422 MODULE_LICENSE("GPL"); 2423