1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ 14 #define ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ 15 16 /* 17 ***************************************** 18 * DCORE0_MME_CTRL_LO 19 * (Prototype: MME_CTRL_LO) 20 ***************************************** 21 */ 22 23 /* DCORE0_MME_CTRL_LO_ARCH_STATUS */ 24 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_SHIFT 0 25 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_MASK 0x1F 26 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_SHIFT 5 27 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_MASK 0x20 28 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_SHIFT 6 29 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_MASK 0x40 30 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SHIFT 7 31 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_MASK 0x180 32 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_SHIFT 9 33 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK 0x3E00 34 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_SHIFT 14 35 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK 0xC000 36 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_SHIFT 16 37 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x30000 38 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_SHIFT 18 39 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK 0x7C0000 40 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_SHIFT 23 41 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_MASK 0x3800000 42 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_SHIFT 30 43 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_MASK 0x40000000 44 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_SHIFT 31 45 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_MASK 0x80000000 46 47 /* DCORE0_MME_CTRL_LO_CMD */ 48 #define DCORE0_MME_CTRL_LO_CMD_AGU_IN_SHIFT 0 49 #define DCORE0_MME_CTRL_LO_CMD_AGU_IN_MASK 0x1F 50 #define DCORE0_MME_CTRL_LO_CMD_EU_SHIFT 5 51 #define DCORE0_MME_CTRL_LO_CMD_EU_MASK 0x20 52 #define DCORE0_MME_CTRL_LO_CMD_AP_SHIFT 6 53 #define DCORE0_MME_CTRL_LO_CMD_AP_MASK 0x40 54 #define DCORE0_MME_CTRL_LO_CMD_AGU_COUT_SHIFT 7 55 #define DCORE0_MME_CTRL_LO_CMD_AGU_COUT_MASK 0x180 56 #define DCORE0_MME_CTRL_LO_CMD_COPY_AND_INC_SHIFT 9 57 #define DCORE0_MME_CTRL_LO_CMD_COPY_AND_INC_MASK 0x200 58 #define DCORE0_MME_CTRL_LO_CMD_DESC_SEL_SHIFT 10 59 #define DCORE0_MME_CTRL_LO_CMD_DESC_SEL_MASK 0xC00 60 #define DCORE0_MME_CTRL_LO_CMD_MASK_IDLE_IND_SHIFT 12 61 #define DCORE0_MME_CTRL_LO_CMD_MASK_IDLE_IND_MASK 0x1000 62 #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW0_SHIFT 13 63 #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW0_MASK 0x2000 64 #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW1_4_SHIFT 14 65 #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW1_4_MASK 0x4000 66 #define DCORE0_MME_CTRL_LO_CMD_NULL_DESC_SHIFT 15 67 #define DCORE0_MME_CTRL_LO_CMD_NULL_DESC_MASK 0x8000 68 69 /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 */ 70 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK0_SHIFT 0 71 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK0_MASK 0x3F 72 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN0_SHIFT 6 73 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN0_MASK 0x40 74 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK1_SHIFT 8 75 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK1_MASK 0x3F00 76 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN1_SHIFT 14 77 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN1_MASK 0x4000 78 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_SHIFT 15 79 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_MASK 0x8000 80 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_SHIFT 16 81 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_MASK 0x10000 82 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_SHIFT 17 83 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_MASK 0x20000 84 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_SHIFT 18 85 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_MASK 0x40000 86 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_SHIFT 19 87 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_MASK 0x80000 88 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_SHIFT 20 89 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_MASK 0x100000 90 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_SHIFT 21 91 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_MASK 0x200000 92 93 /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 */ 94 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_SHIFT 0 95 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_MASK 0xFFFFFFFF 96 97 /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 */ 98 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_VALUE_SHIFT 0 99 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_VALUE_MASK 0x7FFF 100 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_RESERVED_SHIFT 15 101 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_RESERVED_MASK 0x3FFF8000 102 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_PERF_EN_SHIFT 30 103 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_PERF_EN_MASK 0x40000000 104 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_OP_SHIFT 31 105 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_OP_MASK 0x80000000 106 107 /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 */ 108 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1_V_SHIFT 0 109 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1_V_MASK 0xFFFFFFFF 110 111 /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 */ 112 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_VALUE_SHIFT 0 113 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_VALUE_MASK 0x7FFF 114 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_RESERVED_SHIFT 15 115 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_RESERVED_MASK 0x3FFF8000 116 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_PERF_EN_SHIFT 30 117 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_PERF_EN_MASK 0x40000000 118 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_OP_SHIFT 31 119 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_OP_MASK 0x80000000 120 121 /* DCORE0_MME_CTRL_LO_ARCH_A_SS */ 122 #define DCORE0_MME_CTRL_LO_ARCH_A_SS_MINUS_1_SHIFT 0 123 #define DCORE0_MME_CTRL_LO_ARCH_A_SS_MINUS_1_MASK 0xFFFFFFFF 124 125 /* DCORE0_MME_CTRL_LO_ARCH_B_SS */ 126 #define DCORE0_MME_CTRL_LO_ARCH_B_SS_MINUS_1_SHIFT 0 127 #define DCORE0_MME_CTRL_LO_ARCH_B_SS_MINUS_1_MASK 0xFFFFFFFF 128 129 /* DCORE0_MME_CTRL_LO_ARCH_COUT_SS */ 130 #define DCORE0_MME_CTRL_LO_ARCH_COUT_SS_MINUS_1_SHIFT 0 131 #define DCORE0_MME_CTRL_LO_ARCH_COUT_SS_MINUS_1_MASK 0xFFFFFFFF 132 133 /* DCORE0_MME_CTRL_LO_QM_STALL */ 134 #define DCORE0_MME_CTRL_LO_QM_STALL_V_SHIFT 0 135 #define DCORE0_MME_CTRL_LO_QM_STALL_V_MASK 0x1 136 137 /* DCORE0_MME_CTRL_LO_LOG_SHADOW_LO */ 138 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_0_SHIFT 0 139 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_0_MASK 0x1FF 140 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_1_SHIFT 9 141 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_1_MASK 0x3FE00 142 143 /* DCORE0_MME_CTRL_LO_LOG_SHADOW_HI */ 144 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_2_SHIFT 0 145 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_2_MASK 0x1FF 146 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_3_SHIFT 9 147 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_3_MASK 0x3FE00 148 149 /* DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH */ 150 #define DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH_V_SHIFT 0 151 #define DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH_V_MASK 0x1F 152 153 /* DCORE0_MME_CTRL_LO_REDUN */ 154 #define DCORE0_MME_CTRL_LO_REDUN_FMA_SHIFT 0 155 #define DCORE0_MME_CTRL_LO_REDUN_FMA_MASK 0x3F 156 157 /* DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH */ 158 #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO0_SHIFT 0 159 #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO0_MASK 0x1F 160 #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO1_SHIFT 5 161 #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO1_MASK 0x3E0 162 #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO2_SHIFT 10 163 #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO2_MASK 0x7C00 164 165 /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 */ 166 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_SHIFT 0 167 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_MASK 0xFF 168 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE0_SHIFT 8 169 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE0_MASK 0x1F00 170 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE1_SHIFT 13 171 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE1_MASK 0x3E000 172 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE2_SHIFT 18 173 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE2_MASK 0x7C0000 174 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE3_SHIFT 23 175 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE3_MASK 0xF800000 176 177 /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 */ 178 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE4_SHIFT 0 179 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE4_MASK 0x1F 180 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE_HI_SHIFT 5 181 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE_HI_MASK 0x3E0 182 183 /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 */ 184 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_DLY_SHIFT 0 185 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_DLY_MASK 0xFFF 186 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_EN_SHIFT 31 187 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_EN_MASK 0x80000000 188 189 /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 */ 190 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_DLY_SHIFT 0 191 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_DLY_MASK 0xFFF 192 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_EN_SHIFT 31 193 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_EN_MASK 0x80000000 194 195 /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 */ 196 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_DLY_SHIFT 0 197 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_DLY_MASK 0xFFF 198 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_EN_SHIFT 31 199 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_EN_MASK 0x80000000 200 201 /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I */ 202 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_DLY_SHIFT 0 203 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_DLY_MASK 0xFFF 204 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_EN_SHIFT 31 205 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_EN_MASK 0x80000000 206 207 /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 */ 208 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_DLY_SHIFT 0 209 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_DLY_MASK 0xFFF 210 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_EN_SHIFT 31 211 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_EN_MASK 0x80000000 212 213 /* DCORE0_MME_CTRL_LO_PCU_RL_DESC0 */ 214 #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_RST_TOKEN_SHIFT 0 215 #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_RST_TOKEN_MASK 0xFFFF 216 #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_TIMEOUT_SHIFT 16 217 #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_TIMEOUT_MASK 0xFF0000 218 #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_DUMMY2REAL_PERIOD_SHIFT 24 219 #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_DUMMY2REAL_PERIOD_MASK 0xFF000000 220 221 /* DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE */ 222 #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_INC_VAL_SHIFT 0 223 #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_INC_VAL_MASK 0xFFFF 224 #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_DEC_VAL_SHIFT 16 225 #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_DEC_VAL_MASK 0xFFFF0000 226 227 /* DCORE0_MME_CTRL_LO_PCU_RL_TH */ 228 #define DCORE0_MME_CTRL_LO_PCU_RL_TH_POOL_TH_DEC_SHIFT 0 229 #define DCORE0_MME_CTRL_LO_PCU_RL_TH_POOL_TH_DEC_MASK 0xFFFF 230 #define DCORE0_MME_CTRL_LO_PCU_RL_TH_DUMMY_REAL_DIFF_TH_SHIFT 16 231 #define DCORE0_MME_CTRL_LO_PCU_RL_TH_DUMMY_REAL_DIFF_TH_MASK 0xFFFF0000 232 233 /* DCORE0_MME_CTRL_LO_PCU_RL_MIN */ 234 #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_AVG_MIN_TO_FORCE_DUMMY_SHIFT 0 235 #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_AVG_MIN_TO_FORCE_DUMMY_MASK 0xFFFF 236 #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_TOKEN_MIN_VAL_SHIFT 16 237 #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_TOKEN_MIN_VAL_MASK 0xFFFF0000 238 239 /* DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN */ 240 #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_PCU_DISABLE_SHIFT 0 241 #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_PCU_DISABLE_MASK 0x1 242 #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_MIN_VAL_PROT_EN_SHIFT 1 243 #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_MIN_VAL_PROT_EN_MASK 0x2 244 245 /* DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE */ 246 #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_ALL_MACS_SHIFT 0 247 #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_ALL_MACS_MASK 0x7 248 #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_REAL_MACS_SHIFT 3 249 #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_REAL_MACS_MASK 0x18 250 251 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16 */ 252 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_ODD_SHIFT 0 253 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_ODD_MASK 0xFFFF 254 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_EVEN_SHIFT 16 255 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_EVEN_MASK 0xFFFF0000 256 257 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16 */ 258 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_ODD_SHIFT 0 259 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_ODD_MASK 0xFFFF 260 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_EVEN_SHIFT 16 261 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_EVEN_MASK 0xFFFF0000 262 263 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16 */ 264 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_ODD_SHIFT 0 265 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_ODD_MASK 0xFFFF 266 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_EVEN_SHIFT 16 267 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_EVEN_MASK 0xFFFF0000 268 269 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16 */ 270 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_ODD_SHIFT 0 271 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_ODD_MASK 0xFFFF 272 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_EVEN_SHIFT 16 273 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_EVEN_MASK 0xFFFF0000 274 275 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_F8 */ 276 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_ODD_SHIFT 0 277 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_ODD_MASK 0xFF 278 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_EVEN_SHIFT 8 279 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_EVEN_MASK 0xFF00 280 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_ODD_SHIFT 16 281 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_ODD_MASK 0xFF0000 282 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_EVEN_SHIFT 24 283 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_EVEN_MASK 0xFF000000 284 285 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD */ 286 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD_V_SHIFT 0 287 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD_V_MASK 0xFFFFFFFF 288 289 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN */ 290 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN_V_SHIFT 0 291 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN_V_MASK 0xFFFFFFFF 292 293 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD */ 294 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD_V_SHIFT 0 295 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD_V_MASK 0xFFFFFFFF 296 297 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN */ 298 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN_V_SHIFT 0 299 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN_V_MASK 0xFFFFFFFF 300 301 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD */ 302 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD_V_SHIFT 0 303 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD_V_MASK 0xFFFFFFFF 304 305 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN */ 306 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN_V_SHIFT 0 307 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN_V_MASK 0xFFFFFFFF 308 309 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD */ 310 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD_V_SHIFT 0 311 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD_V_MASK 0xFFFFFFFF 312 313 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN */ 314 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN_V_SHIFT 0 315 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN_V_MASK 0xFFFFFFFF 316 317 /* DCORE0_MME_CTRL_LO_PROT */ 318 #define DCORE0_MME_CTRL_LO_PROT_VALUE_SHIFT 0 319 #define DCORE0_MME_CTRL_LO_PROT_VALUE_MASK 0x7 320 321 /* DCORE0_MME_CTRL_LO_EU */ 322 #define DCORE0_MME_CTRL_LO_EU_POWER_SAVE_DISABLE_SHIFT 0 323 #define DCORE0_MME_CTRL_LO_EU_POWER_SAVE_DISABLE_MASK 0x1 324 #define DCORE0_MME_CTRL_LO_EU_FP_PYR_CLOSE_CGATE_EN_SHIFT 1 325 #define DCORE0_MME_CTRL_LO_EU_FP_PYR_CLOSE_CGATE_EN_MASK 0x2 326 #define DCORE0_MME_CTRL_LO_EU_FP_CLS_CLOSE_CGATE_EN_SHIFT 2 327 #define DCORE0_MME_CTRL_LO_EU_FP_CLS_CLOSE_CGATE_EN_MASK 0x4 328 #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_DLY_SHIFT 8 329 #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_DLY_MASK 0xFFF00 330 #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_ON_DESC_SHIFT 20 331 #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_ON_DESC_MASK 0x100000 332 #define DCORE0_MME_CTRL_LO_EU_FP_ROLLUP_CDC_STALL_DIS_SHIFT 21 333 #define DCORE0_MME_CTRL_LO_EU_FP_ROLLUP_CDC_STALL_DIS_MASK 0x200000 334 335 /* DCORE0_MME_CTRL_LO_SBTE */ 336 #define DCORE0_MME_CTRL_LO_SBTE_CLOSE_CGATE_SHIFT 0 337 #define DCORE0_MME_CTRL_LO_SBTE_CLOSE_CGATE_MASK 0x1F 338 339 /* DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR */ 340 #define DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR_V_SHIFT 0 341 #define DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF 342 343 /* DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR */ 344 #define DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR_V_SHIFT 0 345 #define DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR_V_MASK 0xFFFFFFFF 346 347 /* DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC */ 348 #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_VAL_SHIFT 0 349 #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_VAL_MASK 0xFFFFF 350 #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_SEL_SHIFT 31 351 #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_SEL_MASK 0x80000000 352 353 /* DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 */ 354 #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32_V_NMB__SHIFT 0 355 #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32_V_NMB__MASK 0xFFFFFFFF 356 357 /* DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 */ 358 #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33_V_NMB__SHIFT 0 359 #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33_V_NMB__MASK 0x1 360 361 /* DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS */ 362 #define DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS_FMA_SHIFT 0 363 #define DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS_FMA_MASK 0x1 364 365 /* DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN */ 366 #define DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN_V_SHIFT 0 367 #define DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN_V_MASK 0x1 368 369 /* DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS */ 370 #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_AXI_SHIFT 0 371 #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_AXI_MASK 0x1 372 #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_APB_SHIFT 1 373 #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_APB_MASK 0x2 374 375 /* DCORE0_MME_CTRL_LO_AGU */ 376 #define DCORE0_MME_CTRL_LO_AGU_COUT_H_FROM_SPATIAL_LOOP_SHIFT 0 377 #define DCORE0_MME_CTRL_LO_AGU_COUT_H_FROM_SPATIAL_LOOP_MASK 0x1 378 379 /* DCORE0_MME_CTRL_LO_QM */ 380 #define DCORE0_MME_CTRL_LO_QM_STOP_ON_SBTE_ERR_SHIFT 0 381 #define DCORE0_MME_CTRL_LO_QM_STOP_ON_SBTE_ERR_MASK 0x1 382 #define DCORE0_MME_CTRL_LO_QM_EXT_ADDR_ERR_EN_SHIFT 1 383 #define DCORE0_MME_CTRL_LO_QM_EXT_ADDR_ERR_EN_MASK 0x2 384 385 /* DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS */ 386 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT0_SHIFT 0 387 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT0_MASK 0xF 388 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT1_SHIFT 4 389 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT1_MASK 0xF0 390 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AP_BRAIN_SHIFT 8 391 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AP_BRAIN_MASK 0xF00 392 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_EU_BRAIN_SHIFT 12 393 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_EU_BRAIN_MASK 0xF000 394 395 /* DCORE0_MME_CTRL_LO_INTR_CAUSE */ 396 #define DCORE0_MME_CTRL_LO_INTR_CAUSE_V_SHIFT 0 397 #define DCORE0_MME_CTRL_LO_INTR_CAUSE_V_MASK 0xFFFF 398 399 /* DCORE0_MME_CTRL_LO_INTR_MASK */ 400 #define DCORE0_MME_CTRL_LO_INTR_MASK_V_SHIFT 0 401 #define DCORE0_MME_CTRL_LO_INTR_MASK_V_MASK 0x3FFFFF 402 403 /* DCORE0_MME_CTRL_LO_INTR_CLEAR */ 404 #define DCORE0_MME_CTRL_LO_INTR_CLEAR_V_SHIFT 0 405 #define DCORE0_MME_CTRL_LO_INTR_CLEAR_V_MASK 0xFFFF 406 407 /* DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC */ 408 #define DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC_V_SHIFT 0 409 #define DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC_V_MASK 0x1 410 411 /* DCORE0_MME_CTRL_LO_BIST */ 412 #define DCORE0_MME_CTRL_LO_BIST_FUNC_MODE_SHIFT 0 413 #define DCORE0_MME_CTRL_LO_BIST_FUNC_MODE_MASK 0x1 414 #define DCORE0_MME_CTRL_LO_BIST_APB_SW_MODE_SHIFT 1 415 #define DCORE0_MME_CTRL_LO_BIST_APB_SW_MODE_MASK 0x2 416 417 /* DCORE0_MME_CTRL_LO_EU_RL_ENABLE */ 418 #define DCORE0_MME_CTRL_LO_EU_RL_ENABLE_V_SHIFT 0 419 #define DCORE0_MME_CTRL_LO_EU_RL_ENABLE_V_MASK 0x1 420 421 /* DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL */ 422 #define DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL_STAT_SHIFT 0 423 #define DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL_STAT_MASK 0x1 424 425 /* DCORE0_MME_CTRL_LO_EU_RL_CFG */ 426 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_RST_TOKEN_SHIFT 0 427 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_RST_TOKEN_MASK 0xFF 428 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_TIMEOUT_SHIFT 8 429 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_TIMEOUT_MASK 0xFF00 430 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_SATURATION_SHIFT 16 431 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_SATURATION_MASK 0xFF0000 432 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_DATA_SIZE_SHIFT 24 433 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_DATA_SIZE_MASK 0xFF000000 434 435 /* DCORE0_MME_CTRL_LO_PCU_DBG_DW0 */ 436 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_FSM_STATE_SHIFT 0 437 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_FSM_STATE_MASK 0x1 438 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_REAL_POOL_TOKENS_SHIFT 8 439 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_REAL_POOL_TOKENS_MASK 0xFFFFF00 440 441 /* DCORE0_MME_CTRL_LO_PCU_DBG_DW1 */ 442 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW1_ALL_POOL_TOKENS_SHIFT 0 443 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW1_ALL_POOL_TOKENS_MASK 0xFFFFF 444 445 /* DCORE0_MME_CTRL_LO_PCU_DBG_DW2 */ 446 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_BUBBLE_CYC_CNTR_SHIFT 0 447 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_BUBBLE_CYC_CNTR_MASK 0xFFFF 448 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_DUMMY_CYC_CNTR_SHIFT 16 449 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_DUMMY_CYC_CNTR_MASK 0xFFFF0000 450 451 /* DCORE0_MME_CTRL_LO_PCU_DBG_DW3 */ 452 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_REAL_MACS_HISTORY_SHIFT 0 453 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_REAL_MACS_HISTORY_MASK 0xFFFF 454 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_ALL_MACS_HISTORY_SHIFT 16 455 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_ALL_MACS_HISTORY_MASK 0xFFFF0000 456 457 /* DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID */ 458 #define DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID_B_SHIFT 0 459 #define DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID_B_MASK 0xFFFFFFFF 460 461 /* DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM */ 462 #define DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM_V_SHIFT 0 463 #define DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM_V_MASK 0x3FFFFFFF 464 465 #endif /* ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ */ 466