xref: /linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_kdma_masks.h (revision 58f6259b7a08f8d47d4629609703d358b042f0fd)
1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_ARC_FARM_KDMA_MASKS_H_
14 #define ASIC_REG_ARC_FARM_KDMA_MASKS_H_
15 
16 /*
17  *****************************************
18  *   ARC_FARM_KDMA
19  *   (Prototype: DMA_CORE)
20  *****************************************
21  */
22 
23 /* ARC_FARM_KDMA_CFG_0 */
24 #define ARC_FARM_KDMA_CFG_0_EN_SHIFT 0
25 #define ARC_FARM_KDMA_CFG_0_EN_MASK 0x1
26 
27 /* ARC_FARM_KDMA_CFG_1 */
28 #define ARC_FARM_KDMA_CFG_1_HALT_SHIFT 0
29 #define ARC_FARM_KDMA_CFG_1_HALT_MASK 0x1
30 #define ARC_FARM_KDMA_CFG_1_FLUSH_SHIFT 1
31 #define ARC_FARM_KDMA_CFG_1_FLUSH_MASK 0x2
32 
33 /* ARC_FARM_KDMA_PROT */
34 #define ARC_FARM_KDMA_PROT_VAL_SHIFT 0
35 #define ARC_FARM_KDMA_PROT_VAL_MASK 0x1
36 #define ARC_FARM_KDMA_PROT_ERR_VAL_SHIFT 1
37 #define ARC_FARM_KDMA_PROT_ERR_VAL_MASK 0x2
38 
39 /* ARC_FARM_KDMA_CKG */
40 #define ARC_FARM_KDMA_CKG_HBW_RBUF_SHIFT 0
41 #define ARC_FARM_KDMA_CKG_HBW_RBUF_MASK 0x1
42 #define ARC_FARM_KDMA_CKG_LBW_RBUF_KDMA_SHIFT 1
43 #define ARC_FARM_KDMA_CKG_LBW_RBUF_KDMA_MASK 0x2
44 #define ARC_FARM_KDMA_CKG_TE_SHIFT 2
45 #define ARC_FARM_KDMA_CKG_TE_MASK 0x4
46 
47 /* ARC_FARM_KDMA_RD_GLBL */
48 #define ARC_FARM_KDMA_RD_GLBL_LBW_VIA_HBW_SHIFT 0
49 #define ARC_FARM_KDMA_RD_GLBL_LBW_VIA_HBW_MASK 0x1
50 #define ARC_FARM_KDMA_RD_GLBL_HBW_FORCE_MISS_SHIFT 4
51 #define ARC_FARM_KDMA_RD_GLBL_HBW_FORCE_MISS_MASK 0x10
52 #define ARC_FARM_KDMA_RD_GLBL_LBW_FORCE_MISS_SHIFT 5
53 #define ARC_FARM_KDMA_RD_GLBL_LBW_FORCE_MISS_MASK 0x20
54 
55 /* ARC_FARM_KDMA_RD_HBW_MAX_OUTSTAND */
56 #define ARC_FARM_KDMA_RD_HBW_MAX_OUTSTAND_VAL_SHIFT 0
57 #define ARC_FARM_KDMA_RD_HBW_MAX_OUTSTAND_VAL_MASK 0xFFF
58 
59 /* ARC_FARM_KDMA_RD_HBW_MAX_SIZE */
60 #define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_DATA_SHIFT 0
61 #define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_DATA_MASK 0xFFF
62 #define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_MD_SHIFT 16
63 #define ARC_FARM_KDMA_RD_HBW_MAX_SIZE_MD_MASK 0xFFF0000
64 
65 /* ARC_FARM_KDMA_RD_HBW_ARCACHE */
66 #define ARC_FARM_KDMA_RD_HBW_ARCACHE_VAL_SHIFT 0
67 #define ARC_FARM_KDMA_RD_HBW_ARCACHE_VAL_MASK 0xF
68 
69 /* ARC_FARM_KDMA_RD_HBW_INFLIGHTS */
70 #define ARC_FARM_KDMA_RD_HBW_INFLIGHTS_VAL_SHIFT 0
71 #define ARC_FARM_KDMA_RD_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
72 
73 /* ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG */
74 #define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_TOUT_SHIFT 0
75 #define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF
76 #define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_SAT_SHIFT 16
77 #define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
78 #define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_EN_SHIFT 31
79 #define ARC_FARM_KDMA_RD_HBW_RATE_LIM_CFG_EN_MASK 0x80000000
80 
81 /* ARC_FARM_KDMA_RD_LBW_MAX_OUTSTAND */
82 #define ARC_FARM_KDMA_RD_LBW_MAX_OUTSTAND_VAL_SHIFT 0
83 #define ARC_FARM_KDMA_RD_LBW_MAX_OUTSTAND_VAL_MASK 0xFFF
84 
85 /* ARC_FARM_KDMA_RD_LBW_MAX_SIZE */
86 #define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_DATA_SHIFT 0
87 #define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_DATA_MASK 0xFFF
88 #define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_MD_SHIFT 16
89 #define ARC_FARM_KDMA_RD_LBW_MAX_SIZE_MD_MASK 0xFFF0000
90 
91 /* ARC_FARM_KDMA_RD_LBW_ARCACHE */
92 #define ARC_FARM_KDMA_RD_LBW_ARCACHE_VAL_SHIFT 0
93 #define ARC_FARM_KDMA_RD_LBW_ARCACHE_VAL_MASK 0xF
94 
95 /* ARC_FARM_KDMA_RD_LBW_INFLIGHTS */
96 #define ARC_FARM_KDMA_RD_LBW_INFLIGHTS_VAL_SHIFT 0
97 #define ARC_FARM_KDMA_RD_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
98 
99 /* ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG */
100 #define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_TOUT_SHIFT 0
101 #define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF
102 #define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_SAT_SHIFT 16
103 #define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
104 #define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_EN_SHIFT 31
105 #define ARC_FARM_KDMA_RD_LBW_RATE_LIM_CFG_EN_MASK 0x80000000
106 
107 /* ARC_FARM_KDMA_WR_HBW_MAX_OUTSTAND */
108 #define ARC_FARM_KDMA_WR_HBW_MAX_OUTSTAND_VAL_SHIFT 0
109 #define ARC_FARM_KDMA_WR_HBW_MAX_OUTSTAND_VAL_MASK 0xFFFF
110 
111 /* ARC_FARM_KDMA_WR_HBW_MAX_AWID */
112 #define ARC_FARM_KDMA_WR_HBW_MAX_AWID_VAL_SHIFT 0
113 #define ARC_FARM_KDMA_WR_HBW_MAX_AWID_VAL_MASK 0x3FFF
114 
115 /* ARC_FARM_KDMA_WR_HBW_AWCACHE */
116 #define ARC_FARM_KDMA_WR_HBW_AWCACHE_VAL_SHIFT 0
117 #define ARC_FARM_KDMA_WR_HBW_AWCACHE_VAL_MASK 0xF
118 
119 /* ARC_FARM_KDMA_WR_HBW_INFLIGHTS */
120 #define ARC_FARM_KDMA_WR_HBW_INFLIGHTS_VAL_SHIFT 0
121 #define ARC_FARM_KDMA_WR_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
122 
123 /* ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG */
124 #define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_TOUT_SHIFT 0
125 #define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF
126 #define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_SAT_SHIFT 16
127 #define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
128 #define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_EN_SHIFT 31
129 #define ARC_FARM_KDMA_WR_HBW_RATE_LIM_CFG_EN_MASK 0x80000000
130 
131 /* ARC_FARM_KDMA_WR_LBW_MAX_OUTSTAND */
132 #define ARC_FARM_KDMA_WR_LBW_MAX_OUTSTAND_VAL_SHIFT 0
133 #define ARC_FARM_KDMA_WR_LBW_MAX_OUTSTAND_VAL_MASK 0xFFFF
134 
135 /* ARC_FARM_KDMA_WR_LBW_MAX_AWID */
136 #define ARC_FARM_KDMA_WR_LBW_MAX_AWID_VAL_SHIFT 0
137 #define ARC_FARM_KDMA_WR_LBW_MAX_AWID_VAL_MASK 0x7F
138 
139 /* ARC_FARM_KDMA_WR_LBW_AWCACHE */
140 #define ARC_FARM_KDMA_WR_LBW_AWCACHE_VAL_SHIFT 0
141 #define ARC_FARM_KDMA_WR_LBW_AWCACHE_VAL_MASK 0xF
142 
143 /* ARC_FARM_KDMA_WR_LBW_INFLIGHTS */
144 #define ARC_FARM_KDMA_WR_LBW_INFLIGHTS_VAL_SHIFT 0
145 #define ARC_FARM_KDMA_WR_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF
146 
147 /* ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG */
148 #define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_TOUT_SHIFT 0
149 #define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF
150 #define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_SAT_SHIFT 16
151 #define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
152 #define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_EN_SHIFT 31
153 #define ARC_FARM_KDMA_WR_LBW_RATE_LIM_CFG_EN_MASK 0x80000000
154 
155 /* ARC_FARM_KDMA_WR_COMP_MAX_OUTSTAND */
156 #define ARC_FARM_KDMA_WR_COMP_MAX_OUTSTAND_VAL_SHIFT 0
157 #define ARC_FARM_KDMA_WR_COMP_MAX_OUTSTAND_VAL_MASK 0x1F
158 
159 /* ARC_FARM_KDMA_WR_COMP_AWUSER */
160 #define ARC_FARM_KDMA_WR_COMP_AWUSER_VAL_SHIFT 0
161 #define ARC_FARM_KDMA_WR_COMP_AWUSER_VAL_MASK 0xFFFFFFFF
162 
163 /* ARC_FARM_KDMA_ERR_CFG */
164 #define ARC_FARM_KDMA_ERR_CFG_ERR_MSG_EN_SHIFT 0
165 #define ARC_FARM_KDMA_ERR_CFG_ERR_MSG_EN_MASK 0x1
166 #define ARC_FARM_KDMA_ERR_CFG_STOP_ON_ERR_SHIFT 1
167 #define ARC_FARM_KDMA_ERR_CFG_STOP_ON_ERR_MASK 0x2
168 
169 /* ARC_FARM_KDMA_ERR_CAUSE */
170 #define ARC_FARM_KDMA_ERR_CAUSE_HBW_RD_ERR_SHIFT 0
171 #define ARC_FARM_KDMA_ERR_CAUSE_HBW_RD_ERR_MASK 0x1
172 #define ARC_FARM_KDMA_ERR_CAUSE_HBW_WR_ERR_SHIFT 1
173 #define ARC_FARM_KDMA_ERR_CAUSE_HBW_WR_ERR_MASK 0x2
174 #define ARC_FARM_KDMA_ERR_CAUSE_LBW_MSG_WR_ERR_SHIFT 2
175 #define ARC_FARM_KDMA_ERR_CAUSE_LBW_MSG_WR_ERR_MASK 0x4
176 #define ARC_FARM_KDMA_ERR_CAUSE_DESC_OVF_SHIFT 3
177 #define ARC_FARM_KDMA_ERR_CAUSE_DESC_OVF_MASK 0x8
178 #define ARC_FARM_KDMA_ERR_CAUSE_LBW_RD_ERR_SHIFT 4
179 #define ARC_FARM_KDMA_ERR_CAUSE_LBW_RD_ERR_MASK 0x10
180 #define ARC_FARM_KDMA_ERR_CAUSE_LBW_WR_ERR_SHIFT 5
181 #define ARC_FARM_KDMA_ERR_CAUSE_LBW_WR_ERR_MASK 0x20
182 #define ARC_FARM_KDMA_ERR_CAUSE_TE_DESC_FIFO_OVFL_SHIFT 6
183 #define ARC_FARM_KDMA_ERR_CAUSE_TE_DESC_FIFO_OVFL_MASK 0x40
184 #define ARC_FARM_KDMA_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_SHIFT 7
185 #define ARC_FARM_KDMA_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_MASK 0x80
186 
187 /* ARC_FARM_KDMA_ERRMSG_ADDR_LO */
188 #define ARC_FARM_KDMA_ERRMSG_ADDR_LO_VAL_SHIFT 0
189 #define ARC_FARM_KDMA_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF
190 
191 /* ARC_FARM_KDMA_ERRMSG_ADDR_HI */
192 #define ARC_FARM_KDMA_ERRMSG_ADDR_HI_VAL_SHIFT 0
193 #define ARC_FARM_KDMA_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF
194 
195 /* ARC_FARM_KDMA_ERRMSG_WDATA */
196 #define ARC_FARM_KDMA_ERRMSG_WDATA_VAL_SHIFT 0
197 #define ARC_FARM_KDMA_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF
198 
199 /* ARC_FARM_KDMA_STS0 */
200 #define ARC_FARM_KDMA_STS0_RD_REQ_CNT_SHIFT 0
201 #define ARC_FARM_KDMA_STS0_RD_REQ_CNT_MASK 0x7FFF
202 #define ARC_FARM_KDMA_STS0_WR_REQ_CNT_SHIFT 16
203 #define ARC_FARM_KDMA_STS0_WR_REQ_CNT_MASK 0x7FFF0000
204 #define ARC_FARM_KDMA_STS0_BUSY_SHIFT 31
205 #define ARC_FARM_KDMA_STS0_BUSY_MASK 0x80000000
206 
207 /* ARC_FARM_KDMA_STS1 */
208 #define ARC_FARM_KDMA_STS1_IS_HALT_SHIFT 0
209 #define ARC_FARM_KDMA_STS1_IS_HALT_MASK 0x1
210 
211 /* ARC_FARM_KDMA_STS_RD_CTX_SEL */
212 #define ARC_FARM_KDMA_STS_RD_CTX_SEL_VAL_SHIFT 0
213 #define ARC_FARM_KDMA_STS_RD_CTX_SEL_VAL_MASK 0x7
214 #define ARC_FARM_KDMA_STS_RD_CTX_SEL_STRIDE_SHIFT 8
215 #define ARC_FARM_KDMA_STS_RD_CTX_SEL_STRIDE_MASK 0x100
216 
217 /* ARC_FARM_KDMA_STS_RD_CTX_SIZE */
218 #define ARC_FARM_KDMA_STS_RD_CTX_SIZE_VAL_SHIFT 0
219 #define ARC_FARM_KDMA_STS_RD_CTX_SIZE_VAL_MASK 0xFFFFFFFF
220 
221 /* ARC_FARM_KDMA_STS_RD_CTX_BASE_LO */
222 #define ARC_FARM_KDMA_STS_RD_CTX_BASE_LO_VAL_SHIFT 0
223 #define ARC_FARM_KDMA_STS_RD_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF
224 
225 /* ARC_FARM_KDMA_STS_RD_CTX_BASE_HI */
226 #define ARC_FARM_KDMA_STS_RD_CTX_BASE_HI_VAL_SHIFT 0
227 #define ARC_FARM_KDMA_STS_RD_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF
228 
229 /* ARC_FARM_KDMA_STS_RD_CTX_ID */
230 #define ARC_FARM_KDMA_STS_RD_CTX_ID_VAL_SHIFT 0
231 #define ARC_FARM_KDMA_STS_RD_CTX_ID_VAL_MASK 0xFFFF
232 
233 /* ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_LO */
234 #define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_LO_VAL_SHIFT 0
235 #define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_LO_VAL_MASK 0xFFFFFFFF
236 
237 /* ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_HI */
238 #define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_HI_VAL_SHIFT 0
239 #define ARC_FARM_KDMA_STS_RD_HB_AXI_ADDR_HI_VAL_MASK 0xFFFFFFFF
240 
241 /* ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR */
242 #define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VAL_SHIFT 0
243 #define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF
244 #define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_RDY_SHIFT 30
245 #define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_RDY_MASK 0x40000000
246 #define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VLD_SHIFT 31
247 #define ARC_FARM_KDMA_STS_RD_LB_AXI_ADDR_VLD_MASK 0x80000000
248 
249 /* ARC_FARM_KDMA_STS_WR_CTX_SEL */
250 #define ARC_FARM_KDMA_STS_WR_CTX_SEL_VAL_SHIFT 0
251 #define ARC_FARM_KDMA_STS_WR_CTX_SEL_VAL_MASK 0x7
252 #define ARC_FARM_KDMA_STS_WR_CTX_SEL_STRIDE_SHIFT 8
253 #define ARC_FARM_KDMA_STS_WR_CTX_SEL_STRIDE_MASK 0x100
254 
255 /* ARC_FARM_KDMA_STS_WR_CTX_SIZE */
256 #define ARC_FARM_KDMA_STS_WR_CTX_SIZE_VAL_SHIFT 0
257 #define ARC_FARM_KDMA_STS_WR_CTX_SIZE_VAL_MASK 0xFFFFFFFF
258 
259 /* ARC_FARM_KDMA_STS_WR_CTX_BASE_LO */
260 #define ARC_FARM_KDMA_STS_WR_CTX_BASE_LO_VAL_SHIFT 0
261 #define ARC_FARM_KDMA_STS_WR_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF
262 
263 /* ARC_FARM_KDMA_STS_WR_CTX_BASE_HI */
264 #define ARC_FARM_KDMA_STS_WR_CTX_BASE_HI_VAL_SHIFT 0
265 #define ARC_FARM_KDMA_STS_WR_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF
266 
267 /* ARC_FARM_KDMA_STS_WR_CTX_ID */
268 #define ARC_FARM_KDMA_STS_WR_CTX_ID_VAL_SHIFT 0
269 #define ARC_FARM_KDMA_STS_WR_CTX_ID_VAL_MASK 0xFFFFFFFF
270 
271 /* ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO */
272 #define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VAL_SHIFT 0
273 #define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VAL_MASK 0x3FFFF
274 #define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_RDY_SHIFT 30
275 #define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_RDY_MASK 0x40000000
276 #define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VLD_SHIFT 31
277 #define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_LO_VLD_MASK 0x80000000
278 
279 /* ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI */
280 #define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VAL_SHIFT 0
281 #define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VAL_MASK 0x3FFFF
282 #define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_RDY_SHIFT 30
283 #define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_RDY_MASK 0x40000000
284 #define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VLD_SHIFT 31
285 #define ARC_FARM_KDMA_STS_WR_HB_AXI_ADDR_HI_VLD_MASK 0x80000000
286 
287 /* ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR */
288 #define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VAL_SHIFT 0
289 #define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF
290 #define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_RDY_SHIFT 30
291 #define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_RDY_MASK 0x40000000
292 #define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VLD_SHIFT 31
293 #define ARC_FARM_KDMA_STS_WR_LB_AXI_ADDR_VLD_MASK 0x80000000
294 
295 /* ARC_FARM_KDMA_PWRLP_CFG */
296 #define ARC_FARM_KDMA_PWRLP_CFG_GLBL_EN_SHIFT 0
297 #define ARC_FARM_KDMA_PWRLP_CFG_GLBL_EN_MASK 0x1
298 #define ARC_FARM_KDMA_PWRLP_CFG_CLR_SHIFT 4
299 #define ARC_FARM_KDMA_PWRLP_CFG_CLR_MASK 0x10
300 
301 /* ARC_FARM_KDMA_PWRLP_STS */
302 #define ARC_FARM_KDMA_PWRLP_STS_RLVL_SHIFT 0
303 #define ARC_FARM_KDMA_PWRLP_STS_RLVL_MASK 0x7F
304 #define ARC_FARM_KDMA_PWRLP_STS_WLVL_SHIFT 8
305 #define ARC_FARM_KDMA_PWRLP_STS_WLVL_MASK 0x7F00
306 #define ARC_FARM_KDMA_PWRLP_STS_RCNT_SHIFT 16
307 #define ARC_FARM_KDMA_PWRLP_STS_RCNT_MASK 0x7F0000
308 #define ARC_FARM_KDMA_PWRLP_STS_WCNT_SHIFT 23
309 #define ARC_FARM_KDMA_PWRLP_STS_WCNT_MASK 0x3F800000
310 #define ARC_FARM_KDMA_PWRLP_STS_RFULL_SHIFT 30
311 #define ARC_FARM_KDMA_PWRLP_STS_RFULL_MASK 0x40000000
312 #define ARC_FARM_KDMA_PWRLP_STS_WFULL_SHIFT 31
313 #define ARC_FARM_KDMA_PWRLP_STS_WFULL_MASK 0x80000000
314 
315 /* ARC_FARM_KDMA_DBG_DESC_CNT */
316 #define ARC_FARM_KDMA_DBG_DESC_CNT_VAL_SHIFT 0
317 #define ARC_FARM_KDMA_DBG_DESC_CNT_VAL_MASK 0xFFFFFFFF
318 
319 /* ARC_FARM_KDMA_DBG_STS */
320 #define ARC_FARM_KDMA_DBG_STS_RD_CTX_FULL_SHIFT 0
321 #define ARC_FARM_KDMA_DBG_STS_RD_CTX_FULL_MASK 0x1
322 #define ARC_FARM_KDMA_DBG_STS_WR_CTX_FULL_SHIFT 1
323 #define ARC_FARM_KDMA_DBG_STS_WR_CTX_FULL_MASK 0x2
324 #define ARC_FARM_KDMA_DBG_STS_WR_COMP_FULL_SHIFT 2
325 #define ARC_FARM_KDMA_DBG_STS_WR_COMP_FULL_MASK 0x4
326 #define ARC_FARM_KDMA_DBG_STS_RD_CTX_EMPTY_SHIFT 3
327 #define ARC_FARM_KDMA_DBG_STS_RD_CTX_EMPTY_MASK 0x8
328 #define ARC_FARM_KDMA_DBG_STS_WR_CTX_EMPTY_SHIFT 4
329 #define ARC_FARM_KDMA_DBG_STS_WR_CTX_EMPTY_MASK 0x10
330 #define ARC_FARM_KDMA_DBG_STS_WR_COMP_EMPTY_SHIFT 5
331 #define ARC_FARM_KDMA_DBG_STS_WR_COMP_EMPTY_MASK 0x20
332 #define ARC_FARM_KDMA_DBG_STS_TE_EMPTY_SHIFT 6
333 #define ARC_FARM_KDMA_DBG_STS_TE_EMPTY_MASK 0x40
334 #define ARC_FARM_KDMA_DBG_STS_TE_BUSY_SHIFT 7
335 #define ARC_FARM_KDMA_DBG_STS_TE_BUSY_MASK 0x80
336 #define ARC_FARM_KDMA_DBG_STS_GSKT_EMPTY_SHIFT 8
337 #define ARC_FARM_KDMA_DBG_STS_GSKT_EMPTY_MASK 0x100
338 #define ARC_FARM_KDMA_DBG_STS_GSKT_FULL_SHIFT 9
339 #define ARC_FARM_KDMA_DBG_STS_GSKT_FULL_MASK 0x200
340 #define ARC_FARM_KDMA_DBG_STS_RD_AGU_CS_SHIFT 10
341 #define ARC_FARM_KDMA_DBG_STS_RD_AGU_CS_MASK 0x400
342 #define ARC_FARM_KDMA_DBG_STS_WR_AGU_CS_SHIFT 11
343 #define ARC_FARM_KDMA_DBG_STS_WR_AGU_CS_MASK 0x800
344 
345 /* ARC_FARM_KDMA_DBG_BUF_STS */
346 #define ARC_FARM_KDMA_DBG_BUF_STS_HBW_FULLNESS_SHIFT 0
347 #define ARC_FARM_KDMA_DBG_BUF_STS_HBW_FULLNESS_MASK 0xFFF
348 #define ARC_FARM_KDMA_DBG_BUF_STS_LBW_FULLNESS_SHIFT 16
349 #define ARC_FARM_KDMA_DBG_BUF_STS_LBW_FULLNESS_MASK 0xFFF0000
350 
351 /* ARC_FARM_KDMA_DBG_RD_DESC_ID */
352 #define ARC_FARM_KDMA_DBG_RD_DESC_ID_VAL_SHIFT 0
353 #define ARC_FARM_KDMA_DBG_RD_DESC_ID_VAL_MASK 0xFFFF
354 
355 /* ARC_FARM_KDMA_DBG_WR_DESC_ID */
356 #define ARC_FARM_KDMA_DBG_WR_DESC_ID_VAL_SHIFT 0
357 #define ARC_FARM_KDMA_DBG_WR_DESC_ID_VAL_MASK 0xFFFF
358 
359 /* ARC_FARM_KDMA_APB_DMA_LBW_BASE */
360 #define ARC_FARM_KDMA_APB_DMA_LBW_BASE_VAL_SHIFT 0
361 #define ARC_FARM_KDMA_APB_DMA_LBW_BASE_VAL_MASK 0xFFFF
362 
363 /* ARC_FARM_KDMA_APB_MSTR_IF_LBW_BASE */
364 #define ARC_FARM_KDMA_APB_MSTR_IF_LBW_BASE_VAL_SHIFT 0
365 #define ARC_FARM_KDMA_APB_MSTR_IF_LBW_BASE_VAL_MASK 0xFFFF
366 
367 /* ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG */
368 #define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_Y_X_FORCE_SHIFT 0
369 #define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_Y_X_FORCE_MASK 0x1FF
370 #define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_FORCE_EN_SHIFT 9
371 #define ARC_FARM_KDMA_E2E_CRED_ASYNC_CFG_FORCE_EN_MASK 0x200
372 
373 /* ARC_FARM_KDMA_DBG_APB_ENABLER */
374 #define ARC_FARM_KDMA_DBG_APB_ENABLER_DIS_SHIFT 0
375 #define ARC_FARM_KDMA_DBG_APB_ENABLER_DIS_MASK 0x1
376 
377 /* ARC_FARM_KDMA_L2H_CMPR_LO */
378 #define ARC_FARM_KDMA_L2H_CMPR_LO_VAL_SHIFT 20
379 #define ARC_FARM_KDMA_L2H_CMPR_LO_VAL_MASK 0xFFF00000
380 
381 /* ARC_FARM_KDMA_L2H_CMPR_HI */
382 #define ARC_FARM_KDMA_L2H_CMPR_HI_VAL_SHIFT 0
383 #define ARC_FARM_KDMA_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF
384 
385 /* ARC_FARM_KDMA_L2H_MASK_LO */
386 #define ARC_FARM_KDMA_L2H_MASK_LO_VAL_SHIFT 20
387 #define ARC_FARM_KDMA_L2H_MASK_LO_VAL_MASK 0xFFF00000
388 
389 /* ARC_FARM_KDMA_L2H_MASK_HI */
390 #define ARC_FARM_KDMA_L2H_MASK_HI_VAL_SHIFT 0
391 #define ARC_FARM_KDMA_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF
392 
393 /* ARC_FARM_KDMA_IDLE_IND_MASK */
394 #define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_SHIFT 0
395 #define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_MASK 0x1
396 #define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_SHIFT 1
397 #define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_MASK 0x2
398 #define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_SHIFT 2
399 #define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_MASK 0x4
400 #define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_SHIFT 3
401 #define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_MASK 0x8
402 #define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_CNT_STS_SHIFT 8
403 #define ARC_FARM_KDMA_IDLE_IND_MASK_DESC_CNT_STS_MASK 0x1F00
404 #define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_CNT_STS_SHIFT 16
405 #define ARC_FARM_KDMA_IDLE_IND_MASK_COMP_CNT_STS_MASK 0x1F0000
406 #define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_EMPTY_SHIFT 24
407 #define ARC_FARM_KDMA_IDLE_IND_MASK_INSTAGE_EMPTY_MASK 0x1000000
408 #define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_IDLE_STS_SHIFT 25
409 #define ARC_FARM_KDMA_IDLE_IND_MASK_CORE_IDLE_STS_MASK 0x2000000
410 
411 /* ARC_FARM_KDMA_APB_ENABLER */
412 #define ARC_FARM_KDMA_APB_ENABLER_DIS_SHIFT 0
413 #define ARC_FARM_KDMA_APB_ENABLER_DIS_MASK 0x1
414 
415 #endif /* ASIC_REG_ARC_FARM_KDMA_MASKS_H_ */
416