1 /* 2 * Low-Level PCI Access for i386 machines 3 * 4 * Copyright 1993, 1994 Drew Eckhardt 5 * Visionary Computing 6 * (Unix and Linux consulting and custom programming) 7 * Drew@Colorado.EDU 8 * +1 (303) 786-7975 9 * 10 * Drew's work was sponsored by: 11 * iX Multiuser Multitasking Magazine 12 * Hannover, Germany 13 * hm@ix.de 14 * 15 * Copyright 1997--2000 Martin Mares <mj@ucw.cz> 16 * 17 * For more information, please consult the following manuals (look at 18 * http://www.pcisig.com/ for how to get them): 19 * 20 * PCI BIOS Specification 21 * PCI Local Bus Specification 22 * PCI to PCI Bridge Specification 23 * PCI System Design Guide 24 * 25 */ 26 27 #include <linux/types.h> 28 #include <linux/kernel.h> 29 #include <linux/pci.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/errno.h> 33 #include <linux/bootmem.h> 34 35 #include <asm/pat.h> 36 #include <asm/e820.h> 37 #include <asm/pci_x86.h> 38 #include <asm/io_apic.h> 39 40 41 static int 42 skip_isa_ioresource_align(struct pci_dev *dev) { 43 44 if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) && 45 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 46 return 1; 47 return 0; 48 } 49 50 /* 51 * We need to avoid collisions with `mirrored' VGA ports 52 * and other strange ISA hardware, so we always want the 53 * addresses to be allocated in the 0x000-0x0ff region 54 * modulo 0x400. 55 * 56 * Why? Because some silly external IO cards only decode 57 * the low 10 bits of the IO address. The 0x00-0xff region 58 * is reserved for motherboard devices that decode all 16 59 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 60 * but we want to try to avoid allocating at 0x2900-0x2bff 61 * which might have be mirrored at 0x0100-0x03ff.. 62 */ 63 resource_size_t 64 pcibios_align_resource(void *data, const struct resource *res, 65 resource_size_t size, resource_size_t align) 66 { 67 struct pci_dev *dev = data; 68 resource_size_t start = res->start; 69 70 if (res->flags & IORESOURCE_IO) { 71 if (skip_isa_ioresource_align(dev)) 72 return start; 73 if (start & 0x300) 74 start = (start + 0x3ff) & ~0x3ff; 75 } 76 return start; 77 } 78 EXPORT_SYMBOL(pcibios_align_resource); 79 80 /* 81 * Handle resources of PCI devices. If the world were perfect, we could 82 * just allocate all the resource regions and do nothing more. It isn't. 83 * On the other hand, we cannot just re-allocate all devices, as it would 84 * require us to know lots of host bridge internals. So we attempt to 85 * keep as much of the original configuration as possible, but tweak it 86 * when it's found to be wrong. 87 * 88 * Known BIOS problems we have to work around: 89 * - I/O or memory regions not configured 90 * - regions configured, but not enabled in the command register 91 * - bogus I/O addresses above 64K used 92 * - expansion ROMs left enabled (this may sound harmless, but given 93 * the fact the PCI specs explicitly allow address decoders to be 94 * shared between expansion ROMs and other resource regions, it's 95 * at least dangerous) 96 * - bad resource sizes or overlaps with other regions 97 * 98 * Our solution: 99 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 100 * This gives us fixed barriers on where we can allocate. 101 * (2) Allocate resources for all enabled devices. If there is 102 * a collision, just mark the resource as unallocated. Also 103 * disable expansion ROMs during this step. 104 * (3) Try to allocate resources for disabled devices. If the 105 * resources were assigned correctly, everything goes well, 106 * if they weren't, they won't disturb allocation of other 107 * resources. 108 * (4) Assign new addresses to resources which were either 109 * not configured at all or misconfigured. If explicitly 110 * requested by the user, configure expansion ROM address 111 * as well. 112 */ 113 114 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) 115 { 116 struct pci_bus *bus; 117 struct pci_dev *dev; 118 int idx; 119 struct resource *r; 120 121 /* Depth-First Search on bus tree */ 122 list_for_each_entry(bus, bus_list, node) { 123 if ((dev = bus->self)) { 124 for (idx = PCI_BRIDGE_RESOURCES; 125 idx < PCI_NUM_RESOURCES; idx++) { 126 r = &dev->resource[idx]; 127 if (!r->flags) 128 continue; 129 if (!r->start || 130 pci_claim_resource(dev, idx) < 0) { 131 /* 132 * Something is wrong with the region. 133 * Invalidate the resource to prevent 134 * child resource allocations in this 135 * range. 136 */ 137 r->start = r->end = 0; 138 r->flags = 0; 139 } 140 } 141 } 142 pcibios_allocate_bus_resources(&bus->children); 143 } 144 } 145 146 struct pci_check_idx_range { 147 int start; 148 int end; 149 }; 150 151 static void __init pcibios_allocate_resources(int pass) 152 { 153 struct pci_dev *dev = NULL; 154 int idx, disabled, i; 155 u16 command; 156 struct resource *r; 157 158 struct pci_check_idx_range idx_range[] = { 159 { PCI_STD_RESOURCES, PCI_STD_RESOURCE_END }, 160 #ifdef CONFIG_PCI_IOV 161 { PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END }, 162 #endif 163 }; 164 165 for_each_pci_dev(dev) { 166 pci_read_config_word(dev, PCI_COMMAND, &command); 167 for (i = 0; i < ARRAY_SIZE(idx_range); i++) 168 for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) { 169 r = &dev->resource[idx]; 170 if (r->parent) /* Already allocated */ 171 continue; 172 if (!r->start) /* Address not assigned at all */ 173 continue; 174 if (r->flags & IORESOURCE_IO) 175 disabled = !(command & PCI_COMMAND_IO); 176 else 177 disabled = !(command & PCI_COMMAND_MEMORY); 178 if (pass == disabled) { 179 dev_dbg(&dev->dev, 180 "BAR %d: reserving %pr (d=%d, p=%d)\n", 181 idx, r, disabled, pass); 182 if (pci_claim_resource(dev, idx) < 0) { 183 /* We'll assign a new address later */ 184 dev->fw_addr[idx] = r->start; 185 r->end -= r->start; 186 r->start = 0; 187 } 188 } 189 } 190 if (!pass) { 191 r = &dev->resource[PCI_ROM_RESOURCE]; 192 if (r->flags & IORESOURCE_ROM_ENABLE) { 193 /* Turn the ROM off, leave the resource region, 194 * but keep it unregistered. */ 195 u32 reg; 196 dev_dbg(&dev->dev, "disabling ROM %pR\n", r); 197 r->flags &= ~IORESOURCE_ROM_ENABLE; 198 pci_read_config_dword(dev, 199 dev->rom_base_reg, ®); 200 pci_write_config_dword(dev, dev->rom_base_reg, 201 reg & ~PCI_ROM_ADDRESS_ENABLE); 202 } 203 } 204 } 205 } 206 207 static int __init pcibios_assign_resources(void) 208 { 209 struct pci_dev *dev = NULL; 210 struct resource *r; 211 212 if (!(pci_probe & PCI_ASSIGN_ROMS)) { 213 /* 214 * Try to use BIOS settings for ROMs, otherwise let 215 * pci_assign_unassigned_resources() allocate the new 216 * addresses. 217 */ 218 for_each_pci_dev(dev) { 219 r = &dev->resource[PCI_ROM_RESOURCE]; 220 if (!r->flags || !r->start) 221 continue; 222 if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) { 223 r->end -= r->start; 224 r->start = 0; 225 } 226 } 227 } 228 229 pci_assign_unassigned_resources(); 230 231 return 0; 232 } 233 234 void __init pcibios_resource_survey(void) 235 { 236 DBG("PCI: Allocating resources\n"); 237 pcibios_allocate_bus_resources(&pci_root_buses); 238 pcibios_allocate_resources(0); 239 pcibios_allocate_resources(1); 240 241 e820_reserve_resources_late(); 242 /* 243 * Insert the IO APIC resources after PCI initialization has 244 * occured to handle IO APICS that are mapped in on a BAR in 245 * PCI space, but before trying to assign unassigned pci res. 246 */ 247 ioapic_insert_resources(); 248 } 249 250 /** 251 * called in fs_initcall (one below subsys_initcall), 252 * give a chance for motherboard reserve resources 253 */ 254 fs_initcall(pcibios_assign_resources); 255 256 /* 257 * If we set up a device for bus mastering, we need to check the latency 258 * timer as certain crappy BIOSes forget to set it properly. 259 */ 260 unsigned int pcibios_max_latency = 255; 261 262 void pcibios_set_master(struct pci_dev *dev) 263 { 264 u8 lat; 265 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 266 if (lat < 16) 267 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 268 else if (lat > pcibios_max_latency) 269 lat = pcibios_max_latency; 270 else 271 return; 272 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat); 273 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 274 } 275 276 static const struct vm_operations_struct pci_mmap_ops = { 277 .access = generic_access_phys, 278 }; 279 280 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 281 enum pci_mmap_state mmap_state, int write_combine) 282 { 283 unsigned long prot; 284 285 /* I/O space cannot be accessed via normal processor loads and 286 * stores on this platform. 287 */ 288 if (mmap_state == pci_mmap_io) 289 return -EINVAL; 290 291 prot = pgprot_val(vma->vm_page_prot); 292 293 /* 294 * Return error if pat is not enabled and write_combine is requested. 295 * Caller can followup with UC MINUS request and add a WC mtrr if there 296 * is a free mtrr slot. 297 */ 298 if (!pat_enabled && write_combine) 299 return -EINVAL; 300 301 if (pat_enabled && write_combine) 302 prot |= _PAGE_CACHE_WC; 303 else if (pat_enabled || boot_cpu_data.x86 > 3) 304 /* 305 * ioremap() and ioremap_nocache() defaults to UC MINUS for now. 306 * To avoid attribute conflicts, request UC MINUS here 307 * aswell. 308 */ 309 prot |= _PAGE_CACHE_UC_MINUS; 310 311 prot |= _PAGE_IOMAP; /* creating a mapping for IO */ 312 313 vma->vm_page_prot = __pgprot(prot); 314 315 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 316 vma->vm_end - vma->vm_start, 317 vma->vm_page_prot)) 318 return -EAGAIN; 319 320 vma->vm_ops = &pci_mmap_ops; 321 322 return 0; 323 } 324