1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "assigned-dev.h" 31 #include "pmu.h" 32 #include "hyperv.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/export.h> 40 #include <linux/moduleparam.h> 41 #include <linux/mman.h> 42 #include <linux/highmem.h> 43 #include <linux/iommu.h> 44 #include <linux/intel-iommu.h> 45 #include <linux/cpufreq.h> 46 #include <linux/user-return-notifier.h> 47 #include <linux/srcu.h> 48 #include <linux/slab.h> 49 #include <linux/perf_event.h> 50 #include <linux/uaccess.h> 51 #include <linux/hash.h> 52 #include <linux/pci.h> 53 #include <linux/timekeeper_internal.h> 54 #include <linux/pvclock_gtod.h> 55 #include <linux/kvm_irqfd.h> 56 #include <linux/irqbypass.h> 57 #include <trace/events/kvm.h> 58 59 #include <asm/debugreg.h> 60 #include <asm/msr.h> 61 #include <asm/desc.h> 62 #include <asm/mce.h> 63 #include <linux/kernel_stat.h> 64 #include <asm/fpu/internal.h> /* Ugh! */ 65 #include <asm/pvclock.h> 66 #include <asm/div64.h> 67 #include <asm/irq_remapping.h> 68 69 #define CREATE_TRACE_POINTS 70 #include "trace.h" 71 72 #define MAX_IO_MSRS 256 73 #define KVM_MAX_MCE_BANKS 32 74 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 75 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 76 77 #define emul_to_vcpu(ctxt) \ 78 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 79 80 /* EFER defaults: 81 * - enable syscall per default because its emulated by KVM 82 * - enable LME and LMA per default on 64 bit KVM 83 */ 84 #ifdef CONFIG_X86_64 85 static 86 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 87 #else 88 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 89 #endif 90 91 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 92 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 93 94 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 95 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 96 97 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 98 static void process_nmi(struct kvm_vcpu *vcpu); 99 static void enter_smm(struct kvm_vcpu *vcpu); 100 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 101 102 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 103 EXPORT_SYMBOL_GPL(kvm_x86_ops); 104 105 static bool __read_mostly ignore_msrs = 0; 106 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 107 108 unsigned int min_timer_period_us = 500; 109 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 110 111 static bool __read_mostly kvmclock_periodic_sync = true; 112 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 113 114 bool __read_mostly kvm_has_tsc_control; 115 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 116 u32 __read_mostly kvm_max_guest_tsc_khz; 117 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 118 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 119 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 120 u64 __read_mostly kvm_max_tsc_scaling_ratio; 121 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 122 u64 __read_mostly kvm_default_tsc_scaling_ratio; 123 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 124 125 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 126 static u32 __read_mostly tsc_tolerance_ppm = 250; 127 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 128 129 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 130 unsigned int __read_mostly lapic_timer_advance_ns = 0; 131 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 132 133 static bool __read_mostly vector_hashing = true; 134 module_param(vector_hashing, bool, S_IRUGO); 135 136 static bool __read_mostly backwards_tsc_observed = false; 137 138 #define KVM_NR_SHARED_MSRS 16 139 140 struct kvm_shared_msrs_global { 141 int nr; 142 u32 msrs[KVM_NR_SHARED_MSRS]; 143 }; 144 145 struct kvm_shared_msrs { 146 struct user_return_notifier urn; 147 bool registered; 148 struct kvm_shared_msr_values { 149 u64 host; 150 u64 curr; 151 } values[KVM_NR_SHARED_MSRS]; 152 }; 153 154 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 155 static struct kvm_shared_msrs __percpu *shared_msrs; 156 157 struct kvm_stats_debugfs_item debugfs_entries[] = { 158 { "pf_fixed", VCPU_STAT(pf_fixed) }, 159 { "pf_guest", VCPU_STAT(pf_guest) }, 160 { "tlb_flush", VCPU_STAT(tlb_flush) }, 161 { "invlpg", VCPU_STAT(invlpg) }, 162 { "exits", VCPU_STAT(exits) }, 163 { "io_exits", VCPU_STAT(io_exits) }, 164 { "mmio_exits", VCPU_STAT(mmio_exits) }, 165 { "signal_exits", VCPU_STAT(signal_exits) }, 166 { "irq_window", VCPU_STAT(irq_window_exits) }, 167 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 168 { "halt_exits", VCPU_STAT(halt_exits) }, 169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 172 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 173 { "hypercalls", VCPU_STAT(hypercalls) }, 174 { "request_irq", VCPU_STAT(request_irq_exits) }, 175 { "irq_exits", VCPU_STAT(irq_exits) }, 176 { "host_state_reload", VCPU_STAT(host_state_reload) }, 177 { "efer_reload", VCPU_STAT(efer_reload) }, 178 { "fpu_reload", VCPU_STAT(fpu_reload) }, 179 { "insn_emulation", VCPU_STAT(insn_emulation) }, 180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 181 { "irq_injections", VCPU_STAT(irq_injections) }, 182 { "nmi_injections", VCPU_STAT(nmi_injections) }, 183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 184 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 187 { "mmu_flooded", VM_STAT(mmu_flooded) }, 188 { "mmu_recycled", VM_STAT(mmu_recycled) }, 189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 190 { "mmu_unsync", VM_STAT(mmu_unsync) }, 191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 192 { "largepages", VM_STAT(lpages) }, 193 { NULL } 194 }; 195 196 u64 __read_mostly host_xcr0; 197 198 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 199 200 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 201 { 202 int i; 203 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 204 vcpu->arch.apf.gfns[i] = ~0; 205 } 206 207 static void kvm_on_user_return(struct user_return_notifier *urn) 208 { 209 unsigned slot; 210 struct kvm_shared_msrs *locals 211 = container_of(urn, struct kvm_shared_msrs, urn); 212 struct kvm_shared_msr_values *values; 213 unsigned long flags; 214 215 /* 216 * Disabling irqs at this point since the following code could be 217 * interrupted and executed through kvm_arch_hardware_disable() 218 */ 219 local_irq_save(flags); 220 if (locals->registered) { 221 locals->registered = false; 222 user_return_notifier_unregister(urn); 223 } 224 local_irq_restore(flags); 225 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 226 values = &locals->values[slot]; 227 if (values->host != values->curr) { 228 wrmsrl(shared_msrs_global.msrs[slot], values->host); 229 values->curr = values->host; 230 } 231 } 232 } 233 234 static void shared_msr_update(unsigned slot, u32 msr) 235 { 236 u64 value; 237 unsigned int cpu = smp_processor_id(); 238 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 239 240 /* only read, and nobody should modify it at this time, 241 * so don't need lock */ 242 if (slot >= shared_msrs_global.nr) { 243 printk(KERN_ERR "kvm: invalid MSR slot!"); 244 return; 245 } 246 rdmsrl_safe(msr, &value); 247 smsr->values[slot].host = value; 248 smsr->values[slot].curr = value; 249 } 250 251 void kvm_define_shared_msr(unsigned slot, u32 msr) 252 { 253 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 254 shared_msrs_global.msrs[slot] = msr; 255 if (slot >= shared_msrs_global.nr) 256 shared_msrs_global.nr = slot + 1; 257 } 258 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 259 260 static void kvm_shared_msr_cpu_online(void) 261 { 262 unsigned i; 263 264 for (i = 0; i < shared_msrs_global.nr; ++i) 265 shared_msr_update(i, shared_msrs_global.msrs[i]); 266 } 267 268 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 269 { 270 unsigned int cpu = smp_processor_id(); 271 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 272 int err; 273 274 if (((value ^ smsr->values[slot].curr) & mask) == 0) 275 return 0; 276 smsr->values[slot].curr = value; 277 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 278 if (err) 279 return 1; 280 281 if (!smsr->registered) { 282 smsr->urn.on_user_return = kvm_on_user_return; 283 user_return_notifier_register(&smsr->urn); 284 smsr->registered = true; 285 } 286 return 0; 287 } 288 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 289 290 static void drop_user_return_notifiers(void) 291 { 292 unsigned int cpu = smp_processor_id(); 293 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 294 295 if (smsr->registered) 296 kvm_on_user_return(&smsr->urn); 297 } 298 299 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 300 { 301 return vcpu->arch.apic_base; 302 } 303 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 304 305 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 306 { 307 u64 old_state = vcpu->arch.apic_base & 308 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 309 u64 new_state = msr_info->data & 310 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 311 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 312 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); 313 314 if (!msr_info->host_initiated && 315 ((msr_info->data & reserved_bits) != 0 || 316 new_state == X2APIC_ENABLE || 317 (new_state == MSR_IA32_APICBASE_ENABLE && 318 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 319 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 320 old_state == 0))) 321 return 1; 322 323 kvm_lapic_set_base(vcpu, msr_info->data); 324 return 0; 325 } 326 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 327 328 asmlinkage __visible void kvm_spurious_fault(void) 329 { 330 /* Fault while not rebooting. We want the trace. */ 331 BUG(); 332 } 333 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 334 335 #define EXCPT_BENIGN 0 336 #define EXCPT_CONTRIBUTORY 1 337 #define EXCPT_PF 2 338 339 static int exception_class(int vector) 340 { 341 switch (vector) { 342 case PF_VECTOR: 343 return EXCPT_PF; 344 case DE_VECTOR: 345 case TS_VECTOR: 346 case NP_VECTOR: 347 case SS_VECTOR: 348 case GP_VECTOR: 349 return EXCPT_CONTRIBUTORY; 350 default: 351 break; 352 } 353 return EXCPT_BENIGN; 354 } 355 356 #define EXCPT_FAULT 0 357 #define EXCPT_TRAP 1 358 #define EXCPT_ABORT 2 359 #define EXCPT_INTERRUPT 3 360 361 static int exception_type(int vector) 362 { 363 unsigned int mask; 364 365 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 366 return EXCPT_INTERRUPT; 367 368 mask = 1 << vector; 369 370 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 371 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 372 return EXCPT_TRAP; 373 374 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 375 return EXCPT_ABORT; 376 377 /* Reserved exceptions will result in fault */ 378 return EXCPT_FAULT; 379 } 380 381 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 382 unsigned nr, bool has_error, u32 error_code, 383 bool reinject) 384 { 385 u32 prev_nr; 386 int class1, class2; 387 388 kvm_make_request(KVM_REQ_EVENT, vcpu); 389 390 if (!vcpu->arch.exception.pending) { 391 queue: 392 if (has_error && !is_protmode(vcpu)) 393 has_error = false; 394 vcpu->arch.exception.pending = true; 395 vcpu->arch.exception.has_error_code = has_error; 396 vcpu->arch.exception.nr = nr; 397 vcpu->arch.exception.error_code = error_code; 398 vcpu->arch.exception.reinject = reinject; 399 return; 400 } 401 402 /* to check exception */ 403 prev_nr = vcpu->arch.exception.nr; 404 if (prev_nr == DF_VECTOR) { 405 /* triple fault -> shutdown */ 406 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 407 return; 408 } 409 class1 = exception_class(prev_nr); 410 class2 = exception_class(nr); 411 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 412 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 413 /* generate double fault per SDM Table 5-5 */ 414 vcpu->arch.exception.pending = true; 415 vcpu->arch.exception.has_error_code = true; 416 vcpu->arch.exception.nr = DF_VECTOR; 417 vcpu->arch.exception.error_code = 0; 418 } else 419 /* replace previous exception with a new one in a hope 420 that instruction re-execution will regenerate lost 421 exception */ 422 goto queue; 423 } 424 425 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 426 { 427 kvm_multiple_exception(vcpu, nr, false, 0, false); 428 } 429 EXPORT_SYMBOL_GPL(kvm_queue_exception); 430 431 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 432 { 433 kvm_multiple_exception(vcpu, nr, false, 0, true); 434 } 435 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 436 437 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 438 { 439 if (err) 440 kvm_inject_gp(vcpu, 0); 441 else 442 return kvm_skip_emulated_instruction(vcpu); 443 444 return 1; 445 } 446 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 447 448 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 449 { 450 ++vcpu->stat.pf_guest; 451 vcpu->arch.cr2 = fault->address; 452 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 453 } 454 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 455 456 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 457 { 458 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 459 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 460 else 461 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 462 463 return fault->nested_page_fault; 464 } 465 466 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 467 { 468 atomic_inc(&vcpu->arch.nmi_queued); 469 kvm_make_request(KVM_REQ_NMI, vcpu); 470 } 471 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 472 473 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 474 { 475 kvm_multiple_exception(vcpu, nr, true, error_code, false); 476 } 477 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 478 479 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 480 { 481 kvm_multiple_exception(vcpu, nr, true, error_code, true); 482 } 483 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 484 485 /* 486 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 487 * a #GP and return false. 488 */ 489 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 490 { 491 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 492 return true; 493 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 494 return false; 495 } 496 EXPORT_SYMBOL_GPL(kvm_require_cpl); 497 498 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 499 { 500 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 501 return true; 502 503 kvm_queue_exception(vcpu, UD_VECTOR); 504 return false; 505 } 506 EXPORT_SYMBOL_GPL(kvm_require_dr); 507 508 /* 509 * This function will be used to read from the physical memory of the currently 510 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 511 * can read from guest physical or from the guest's guest physical memory. 512 */ 513 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 514 gfn_t ngfn, void *data, int offset, int len, 515 u32 access) 516 { 517 struct x86_exception exception; 518 gfn_t real_gfn; 519 gpa_t ngpa; 520 521 ngpa = gfn_to_gpa(ngfn); 522 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 523 if (real_gfn == UNMAPPED_GVA) 524 return -EFAULT; 525 526 real_gfn = gpa_to_gfn(real_gfn); 527 528 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 529 } 530 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 531 532 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 533 void *data, int offset, int len, u32 access) 534 { 535 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 536 data, offset, len, access); 537 } 538 539 /* 540 * Load the pae pdptrs. Return true is they are all valid. 541 */ 542 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 543 { 544 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 545 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 546 int i; 547 int ret; 548 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 549 550 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 551 offset * sizeof(u64), sizeof(pdpte), 552 PFERR_USER_MASK|PFERR_WRITE_MASK); 553 if (ret < 0) { 554 ret = 0; 555 goto out; 556 } 557 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 558 if ((pdpte[i] & PT_PRESENT_MASK) && 559 (pdpte[i] & 560 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { 561 ret = 0; 562 goto out; 563 } 564 } 565 ret = 1; 566 567 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 568 __set_bit(VCPU_EXREG_PDPTR, 569 (unsigned long *)&vcpu->arch.regs_avail); 570 __set_bit(VCPU_EXREG_PDPTR, 571 (unsigned long *)&vcpu->arch.regs_dirty); 572 out: 573 574 return ret; 575 } 576 EXPORT_SYMBOL_GPL(load_pdptrs); 577 578 bool pdptrs_changed(struct kvm_vcpu *vcpu) 579 { 580 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 581 bool changed = true; 582 int offset; 583 gfn_t gfn; 584 int r; 585 586 if (is_long_mode(vcpu) || !is_pae(vcpu)) 587 return false; 588 589 if (!test_bit(VCPU_EXREG_PDPTR, 590 (unsigned long *)&vcpu->arch.regs_avail)) 591 return true; 592 593 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; 594 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); 595 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 596 PFERR_USER_MASK | PFERR_WRITE_MASK); 597 if (r < 0) 598 goto out; 599 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 600 out: 601 602 return changed; 603 } 604 EXPORT_SYMBOL_GPL(pdptrs_changed); 605 606 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 607 { 608 unsigned long old_cr0 = kvm_read_cr0(vcpu); 609 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 610 611 cr0 |= X86_CR0_ET; 612 613 #ifdef CONFIG_X86_64 614 if (cr0 & 0xffffffff00000000UL) 615 return 1; 616 #endif 617 618 cr0 &= ~CR0_RESERVED_BITS; 619 620 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 621 return 1; 622 623 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 624 return 1; 625 626 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 627 #ifdef CONFIG_X86_64 628 if ((vcpu->arch.efer & EFER_LME)) { 629 int cs_db, cs_l; 630 631 if (!is_pae(vcpu)) 632 return 1; 633 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 634 if (cs_l) 635 return 1; 636 } else 637 #endif 638 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 639 kvm_read_cr3(vcpu))) 640 return 1; 641 } 642 643 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 644 return 1; 645 646 kvm_x86_ops->set_cr0(vcpu, cr0); 647 648 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 649 kvm_clear_async_pf_completion_queue(vcpu); 650 kvm_async_pf_hash_reset(vcpu); 651 } 652 653 if ((cr0 ^ old_cr0) & update_bits) 654 kvm_mmu_reset_context(vcpu); 655 656 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 657 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 658 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 659 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 660 661 return 0; 662 } 663 EXPORT_SYMBOL_GPL(kvm_set_cr0); 664 665 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 666 { 667 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 668 } 669 EXPORT_SYMBOL_GPL(kvm_lmsw); 670 671 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 672 { 673 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 674 !vcpu->guest_xcr0_loaded) { 675 /* kvm_set_xcr() also depends on this */ 676 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 677 vcpu->guest_xcr0_loaded = 1; 678 } 679 } 680 681 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 682 { 683 if (vcpu->guest_xcr0_loaded) { 684 if (vcpu->arch.xcr0 != host_xcr0) 685 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 686 vcpu->guest_xcr0_loaded = 0; 687 } 688 } 689 690 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 691 { 692 u64 xcr0 = xcr; 693 u64 old_xcr0 = vcpu->arch.xcr0; 694 u64 valid_bits; 695 696 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 697 if (index != XCR_XFEATURE_ENABLED_MASK) 698 return 1; 699 if (!(xcr0 & XFEATURE_MASK_FP)) 700 return 1; 701 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 702 return 1; 703 704 /* 705 * Do not allow the guest to set bits that we do not support 706 * saving. However, xcr0 bit 0 is always set, even if the 707 * emulated CPU does not support XSAVE (see fx_init). 708 */ 709 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 710 if (xcr0 & ~valid_bits) 711 return 1; 712 713 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 714 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 715 return 1; 716 717 if (xcr0 & XFEATURE_MASK_AVX512) { 718 if (!(xcr0 & XFEATURE_MASK_YMM)) 719 return 1; 720 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 721 return 1; 722 } 723 vcpu->arch.xcr0 = xcr0; 724 725 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 726 kvm_update_cpuid(vcpu); 727 return 0; 728 } 729 730 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 731 { 732 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 733 __kvm_set_xcr(vcpu, index, xcr)) { 734 kvm_inject_gp(vcpu, 0); 735 return 1; 736 } 737 return 0; 738 } 739 EXPORT_SYMBOL_GPL(kvm_set_xcr); 740 741 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 742 { 743 unsigned long old_cr4 = kvm_read_cr4(vcpu); 744 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 745 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 746 747 if (cr4 & CR4_RESERVED_BITS) 748 return 1; 749 750 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) 751 return 1; 752 753 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) 754 return 1; 755 756 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) 757 return 1; 758 759 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) 760 return 1; 761 762 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE)) 763 return 1; 764 765 if (is_long_mode(vcpu)) { 766 if (!(cr4 & X86_CR4_PAE)) 767 return 1; 768 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 769 && ((cr4 ^ old_cr4) & pdptr_bits) 770 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 771 kvm_read_cr3(vcpu))) 772 return 1; 773 774 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 775 if (!guest_cpuid_has_pcid(vcpu)) 776 return 1; 777 778 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 779 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 780 return 1; 781 } 782 783 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 784 return 1; 785 786 if (((cr4 ^ old_cr4) & pdptr_bits) || 787 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 788 kvm_mmu_reset_context(vcpu); 789 790 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 791 kvm_update_cpuid(vcpu); 792 793 return 0; 794 } 795 EXPORT_SYMBOL_GPL(kvm_set_cr4); 796 797 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 798 { 799 #ifdef CONFIG_X86_64 800 cr3 &= ~CR3_PCID_INVD; 801 #endif 802 803 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 804 kvm_mmu_sync_roots(vcpu); 805 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 806 return 0; 807 } 808 809 if (is_long_mode(vcpu)) { 810 if (cr3 & CR3_L_MODE_RESERVED_BITS) 811 return 1; 812 } else if (is_pae(vcpu) && is_paging(vcpu) && 813 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 814 return 1; 815 816 vcpu->arch.cr3 = cr3; 817 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 818 kvm_mmu_new_cr3(vcpu); 819 return 0; 820 } 821 EXPORT_SYMBOL_GPL(kvm_set_cr3); 822 823 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 824 { 825 if (cr8 & CR8_RESERVED_BITS) 826 return 1; 827 if (lapic_in_kernel(vcpu)) 828 kvm_lapic_set_tpr(vcpu, cr8); 829 else 830 vcpu->arch.cr8 = cr8; 831 return 0; 832 } 833 EXPORT_SYMBOL_GPL(kvm_set_cr8); 834 835 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 836 { 837 if (lapic_in_kernel(vcpu)) 838 return kvm_lapic_get_cr8(vcpu); 839 else 840 return vcpu->arch.cr8; 841 } 842 EXPORT_SYMBOL_GPL(kvm_get_cr8); 843 844 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 845 { 846 int i; 847 848 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 849 for (i = 0; i < KVM_NR_DB_REGS; i++) 850 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 851 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 852 } 853 } 854 855 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 856 { 857 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 858 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 859 } 860 861 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 862 { 863 unsigned long dr7; 864 865 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 866 dr7 = vcpu->arch.guest_debug_dr7; 867 else 868 dr7 = vcpu->arch.dr7; 869 kvm_x86_ops->set_dr7(vcpu, dr7); 870 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 871 if (dr7 & DR7_BP_EN_MASK) 872 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 873 } 874 875 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 876 { 877 u64 fixed = DR6_FIXED_1; 878 879 if (!guest_cpuid_has_rtm(vcpu)) 880 fixed |= DR6_RTM; 881 return fixed; 882 } 883 884 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 885 { 886 switch (dr) { 887 case 0 ... 3: 888 vcpu->arch.db[dr] = val; 889 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 890 vcpu->arch.eff_db[dr] = val; 891 break; 892 case 4: 893 /* fall through */ 894 case 6: 895 if (val & 0xffffffff00000000ULL) 896 return -1; /* #GP */ 897 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 898 kvm_update_dr6(vcpu); 899 break; 900 case 5: 901 /* fall through */ 902 default: /* 7 */ 903 if (val & 0xffffffff00000000ULL) 904 return -1; /* #GP */ 905 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 906 kvm_update_dr7(vcpu); 907 break; 908 } 909 910 return 0; 911 } 912 913 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 914 { 915 if (__kvm_set_dr(vcpu, dr, val)) { 916 kvm_inject_gp(vcpu, 0); 917 return 1; 918 } 919 return 0; 920 } 921 EXPORT_SYMBOL_GPL(kvm_set_dr); 922 923 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 924 { 925 switch (dr) { 926 case 0 ... 3: 927 *val = vcpu->arch.db[dr]; 928 break; 929 case 4: 930 /* fall through */ 931 case 6: 932 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 933 *val = vcpu->arch.dr6; 934 else 935 *val = kvm_x86_ops->get_dr6(vcpu); 936 break; 937 case 5: 938 /* fall through */ 939 default: /* 7 */ 940 *val = vcpu->arch.dr7; 941 break; 942 } 943 return 0; 944 } 945 EXPORT_SYMBOL_GPL(kvm_get_dr); 946 947 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 948 { 949 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 950 u64 data; 951 int err; 952 953 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 954 if (err) 955 return err; 956 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 957 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 958 return err; 959 } 960 EXPORT_SYMBOL_GPL(kvm_rdpmc); 961 962 /* 963 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 964 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 965 * 966 * This list is modified at module load time to reflect the 967 * capabilities of the host cpu. This capabilities test skips MSRs that are 968 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 969 * may depend on host virtualization features rather than host cpu features. 970 */ 971 972 static u32 msrs_to_save[] = { 973 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 974 MSR_STAR, 975 #ifdef CONFIG_X86_64 976 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 977 #endif 978 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 979 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 980 }; 981 982 static unsigned num_msrs_to_save; 983 984 static u32 emulated_msrs[] = { 985 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 986 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 987 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 988 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 989 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 990 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 991 HV_X64_MSR_RESET, 992 HV_X64_MSR_VP_INDEX, 993 HV_X64_MSR_VP_RUNTIME, 994 HV_X64_MSR_SCONTROL, 995 HV_X64_MSR_STIMER0_CONFIG, 996 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 997 MSR_KVM_PV_EOI_EN, 998 999 MSR_IA32_TSC_ADJUST, 1000 MSR_IA32_TSCDEADLINE, 1001 MSR_IA32_MISC_ENABLE, 1002 MSR_IA32_MCG_STATUS, 1003 MSR_IA32_MCG_CTL, 1004 MSR_IA32_MCG_EXT_CTL, 1005 MSR_IA32_SMBASE, 1006 }; 1007 1008 static unsigned num_emulated_msrs; 1009 1010 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1011 { 1012 if (efer & efer_reserved_bits) 1013 return false; 1014 1015 if (efer & EFER_FFXSR) { 1016 struct kvm_cpuid_entry2 *feat; 1017 1018 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 1019 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) 1020 return false; 1021 } 1022 1023 if (efer & EFER_SVME) { 1024 struct kvm_cpuid_entry2 *feat; 1025 1026 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 1027 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) 1028 return false; 1029 } 1030 1031 return true; 1032 } 1033 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1034 1035 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 1036 { 1037 u64 old_efer = vcpu->arch.efer; 1038 1039 if (!kvm_valid_efer(vcpu, efer)) 1040 return 1; 1041 1042 if (is_paging(vcpu) 1043 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1044 return 1; 1045 1046 efer &= ~EFER_LMA; 1047 efer |= vcpu->arch.efer & EFER_LMA; 1048 1049 kvm_x86_ops->set_efer(vcpu, efer); 1050 1051 /* Update reserved bits */ 1052 if ((efer ^ old_efer) & EFER_NX) 1053 kvm_mmu_reset_context(vcpu); 1054 1055 return 0; 1056 } 1057 1058 void kvm_enable_efer_bits(u64 mask) 1059 { 1060 efer_reserved_bits &= ~mask; 1061 } 1062 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1063 1064 /* 1065 * Writes msr value into into the appropriate "register". 1066 * Returns 0 on success, non-0 otherwise. 1067 * Assumes vcpu_load() was already called. 1068 */ 1069 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1070 { 1071 switch (msr->index) { 1072 case MSR_FS_BASE: 1073 case MSR_GS_BASE: 1074 case MSR_KERNEL_GS_BASE: 1075 case MSR_CSTAR: 1076 case MSR_LSTAR: 1077 if (is_noncanonical_address(msr->data)) 1078 return 1; 1079 break; 1080 case MSR_IA32_SYSENTER_EIP: 1081 case MSR_IA32_SYSENTER_ESP: 1082 /* 1083 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1084 * non-canonical address is written on Intel but not on 1085 * AMD (which ignores the top 32-bits, because it does 1086 * not implement 64-bit SYSENTER). 1087 * 1088 * 64-bit code should hence be able to write a non-canonical 1089 * value on AMD. Making the address canonical ensures that 1090 * vmentry does not fail on Intel after writing a non-canonical 1091 * value, and that something deterministic happens if the guest 1092 * invokes 64-bit SYSENTER. 1093 */ 1094 msr->data = get_canonical(msr->data); 1095 } 1096 return kvm_x86_ops->set_msr(vcpu, msr); 1097 } 1098 EXPORT_SYMBOL_GPL(kvm_set_msr); 1099 1100 /* 1101 * Adapt set_msr() to msr_io()'s calling convention 1102 */ 1103 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1104 { 1105 struct msr_data msr; 1106 int r; 1107 1108 msr.index = index; 1109 msr.host_initiated = true; 1110 r = kvm_get_msr(vcpu, &msr); 1111 if (r) 1112 return r; 1113 1114 *data = msr.data; 1115 return 0; 1116 } 1117 1118 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1119 { 1120 struct msr_data msr; 1121 1122 msr.data = *data; 1123 msr.index = index; 1124 msr.host_initiated = true; 1125 return kvm_set_msr(vcpu, &msr); 1126 } 1127 1128 #ifdef CONFIG_X86_64 1129 struct pvclock_gtod_data { 1130 seqcount_t seq; 1131 1132 struct { /* extract of a clocksource struct */ 1133 int vclock_mode; 1134 u64 cycle_last; 1135 u64 mask; 1136 u32 mult; 1137 u32 shift; 1138 } clock; 1139 1140 u64 boot_ns; 1141 u64 nsec_base; 1142 }; 1143 1144 static struct pvclock_gtod_data pvclock_gtod_data; 1145 1146 static void update_pvclock_gtod(struct timekeeper *tk) 1147 { 1148 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1149 u64 boot_ns; 1150 1151 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1152 1153 write_seqcount_begin(&vdata->seq); 1154 1155 /* copy pvclock gtod data */ 1156 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1157 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1158 vdata->clock.mask = tk->tkr_mono.mask; 1159 vdata->clock.mult = tk->tkr_mono.mult; 1160 vdata->clock.shift = tk->tkr_mono.shift; 1161 1162 vdata->boot_ns = boot_ns; 1163 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1164 1165 write_seqcount_end(&vdata->seq); 1166 } 1167 #endif 1168 1169 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1170 { 1171 /* 1172 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1173 * vcpu_enter_guest. This function is only called from 1174 * the physical CPU that is running vcpu. 1175 */ 1176 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1177 } 1178 1179 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1180 { 1181 int version; 1182 int r; 1183 struct pvclock_wall_clock wc; 1184 struct timespec64 boot; 1185 1186 if (!wall_clock) 1187 return; 1188 1189 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1190 if (r) 1191 return; 1192 1193 if (version & 1) 1194 ++version; /* first time write, random junk */ 1195 1196 ++version; 1197 1198 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1199 return; 1200 1201 /* 1202 * The guest calculates current wall clock time by adding 1203 * system time (updated by kvm_guest_time_update below) to the 1204 * wall clock specified here. guest system time equals host 1205 * system time for us, thus we must fill in host boot time here. 1206 */ 1207 getboottime64(&boot); 1208 1209 if (kvm->arch.kvmclock_offset) { 1210 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset); 1211 boot = timespec64_sub(boot, ts); 1212 } 1213 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */ 1214 wc.nsec = boot.tv_nsec; 1215 wc.version = version; 1216 1217 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1218 1219 version++; 1220 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1221 } 1222 1223 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1224 { 1225 do_shl32_div32(dividend, divisor); 1226 return dividend; 1227 } 1228 1229 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1230 s8 *pshift, u32 *pmultiplier) 1231 { 1232 uint64_t scaled64; 1233 int32_t shift = 0; 1234 uint64_t tps64; 1235 uint32_t tps32; 1236 1237 tps64 = base_hz; 1238 scaled64 = scaled_hz; 1239 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1240 tps64 >>= 1; 1241 shift--; 1242 } 1243 1244 tps32 = (uint32_t)tps64; 1245 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1246 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1247 scaled64 >>= 1; 1248 else 1249 tps32 <<= 1; 1250 shift++; 1251 } 1252 1253 *pshift = shift; 1254 *pmultiplier = div_frac(scaled64, tps32); 1255 1256 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", 1257 __func__, base_hz, scaled_hz, shift, *pmultiplier); 1258 } 1259 1260 #ifdef CONFIG_X86_64 1261 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1262 #endif 1263 1264 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1265 static unsigned long max_tsc_khz; 1266 1267 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1268 { 1269 u64 v = (u64)khz * (1000000 + ppm); 1270 do_div(v, 1000000); 1271 return v; 1272 } 1273 1274 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1275 { 1276 u64 ratio; 1277 1278 /* Guest TSC same frequency as host TSC? */ 1279 if (!scale) { 1280 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1281 return 0; 1282 } 1283 1284 /* TSC scaling supported? */ 1285 if (!kvm_has_tsc_control) { 1286 if (user_tsc_khz > tsc_khz) { 1287 vcpu->arch.tsc_catchup = 1; 1288 vcpu->arch.tsc_always_catchup = 1; 1289 return 0; 1290 } else { 1291 WARN(1, "user requested TSC rate below hardware speed\n"); 1292 return -1; 1293 } 1294 } 1295 1296 /* TSC scaling required - calculate ratio */ 1297 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1298 user_tsc_khz, tsc_khz); 1299 1300 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1301 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1302 user_tsc_khz); 1303 return -1; 1304 } 1305 1306 vcpu->arch.tsc_scaling_ratio = ratio; 1307 return 0; 1308 } 1309 1310 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1311 { 1312 u32 thresh_lo, thresh_hi; 1313 int use_scaling = 0; 1314 1315 /* tsc_khz can be zero if TSC calibration fails */ 1316 if (user_tsc_khz == 0) { 1317 /* set tsc_scaling_ratio to a safe value */ 1318 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1319 return -1; 1320 } 1321 1322 /* Compute a scale to convert nanoseconds in TSC cycles */ 1323 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1324 &vcpu->arch.virtual_tsc_shift, 1325 &vcpu->arch.virtual_tsc_mult); 1326 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1327 1328 /* 1329 * Compute the variation in TSC rate which is acceptable 1330 * within the range of tolerance and decide if the 1331 * rate being applied is within that bounds of the hardware 1332 * rate. If so, no scaling or compensation need be done. 1333 */ 1334 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1335 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1336 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1337 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1338 use_scaling = 1; 1339 } 1340 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1341 } 1342 1343 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1344 { 1345 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1346 vcpu->arch.virtual_tsc_mult, 1347 vcpu->arch.virtual_tsc_shift); 1348 tsc += vcpu->arch.this_tsc_write; 1349 return tsc; 1350 } 1351 1352 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1353 { 1354 #ifdef CONFIG_X86_64 1355 bool vcpus_matched; 1356 struct kvm_arch *ka = &vcpu->kvm->arch; 1357 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1358 1359 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1360 atomic_read(&vcpu->kvm->online_vcpus)); 1361 1362 /* 1363 * Once the masterclock is enabled, always perform request in 1364 * order to update it. 1365 * 1366 * In order to enable masterclock, the host clocksource must be TSC 1367 * and the vcpus need to have matched TSCs. When that happens, 1368 * perform request to enable masterclock. 1369 */ 1370 if (ka->use_master_clock || 1371 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) 1372 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1373 1374 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1375 atomic_read(&vcpu->kvm->online_vcpus), 1376 ka->use_master_clock, gtod->clock.vclock_mode); 1377 #endif 1378 } 1379 1380 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1381 { 1382 u64 curr_offset = vcpu->arch.tsc_offset; 1383 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1384 } 1385 1386 /* 1387 * Multiply tsc by a fixed point number represented by ratio. 1388 * 1389 * The most significant 64-N bits (mult) of ratio represent the 1390 * integral part of the fixed point number; the remaining N bits 1391 * (frac) represent the fractional part, ie. ratio represents a fixed 1392 * point number (mult + frac * 2^(-N)). 1393 * 1394 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1395 */ 1396 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1397 { 1398 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1399 } 1400 1401 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1402 { 1403 u64 _tsc = tsc; 1404 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1405 1406 if (ratio != kvm_default_tsc_scaling_ratio) 1407 _tsc = __scale_tsc(ratio, tsc); 1408 1409 return _tsc; 1410 } 1411 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1412 1413 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1414 { 1415 u64 tsc; 1416 1417 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1418 1419 return target_tsc - tsc; 1420 } 1421 1422 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1423 { 1424 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 1425 } 1426 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1427 1428 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1429 { 1430 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1431 vcpu->arch.tsc_offset = offset; 1432 } 1433 1434 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1435 { 1436 struct kvm *kvm = vcpu->kvm; 1437 u64 offset, ns, elapsed; 1438 unsigned long flags; 1439 s64 usdiff; 1440 bool matched; 1441 bool already_matched; 1442 u64 data = msr->data; 1443 1444 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1445 offset = kvm_compute_tsc_offset(vcpu, data); 1446 ns = ktime_get_boot_ns(); 1447 elapsed = ns - kvm->arch.last_tsc_nsec; 1448 1449 if (vcpu->arch.virtual_tsc_khz) { 1450 int faulted = 0; 1451 1452 /* n.b - signed multiplication and division required */ 1453 usdiff = data - kvm->arch.last_tsc_write; 1454 #ifdef CONFIG_X86_64 1455 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; 1456 #else 1457 /* do_div() only does unsigned */ 1458 asm("1: idivl %[divisor]\n" 1459 "2: xor %%edx, %%edx\n" 1460 " movl $0, %[faulted]\n" 1461 "3:\n" 1462 ".section .fixup,\"ax\"\n" 1463 "4: movl $1, %[faulted]\n" 1464 " jmp 3b\n" 1465 ".previous\n" 1466 1467 _ASM_EXTABLE(1b, 4b) 1468 1469 : "=A"(usdiff), [faulted] "=r" (faulted) 1470 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); 1471 1472 #endif 1473 do_div(elapsed, 1000); 1474 usdiff -= elapsed; 1475 if (usdiff < 0) 1476 usdiff = -usdiff; 1477 1478 /* idivl overflow => difference is larger than USEC_PER_SEC */ 1479 if (faulted) 1480 usdiff = USEC_PER_SEC; 1481 } else 1482 usdiff = USEC_PER_SEC; /* disable TSC match window below */ 1483 1484 /* 1485 * Special case: TSC write with a small delta (1 second) of virtual 1486 * cycle time against real time is interpreted as an attempt to 1487 * synchronize the CPU. 1488 * 1489 * For a reliable TSC, we can match TSC offsets, and for an unstable 1490 * TSC, we add elapsed time in this computation. We could let the 1491 * compensation code attempt to catch up if we fall behind, but 1492 * it's better to try to match offsets from the beginning. 1493 */ 1494 if (usdiff < USEC_PER_SEC && 1495 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1496 if (!check_tsc_unstable()) { 1497 offset = kvm->arch.cur_tsc_offset; 1498 pr_debug("kvm: matched tsc offset for %llu\n", data); 1499 } else { 1500 u64 delta = nsec_to_cycles(vcpu, elapsed); 1501 data += delta; 1502 offset = kvm_compute_tsc_offset(vcpu, data); 1503 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1504 } 1505 matched = true; 1506 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1507 } else { 1508 /* 1509 * We split periods of matched TSC writes into generations. 1510 * For each generation, we track the original measured 1511 * nanosecond time, offset, and write, so if TSCs are in 1512 * sync, we can match exact offset, and if not, we can match 1513 * exact software computation in compute_guest_tsc() 1514 * 1515 * These values are tracked in kvm->arch.cur_xxx variables. 1516 */ 1517 kvm->arch.cur_tsc_generation++; 1518 kvm->arch.cur_tsc_nsec = ns; 1519 kvm->arch.cur_tsc_write = data; 1520 kvm->arch.cur_tsc_offset = offset; 1521 matched = false; 1522 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1523 kvm->arch.cur_tsc_generation, data); 1524 } 1525 1526 /* 1527 * We also track th most recent recorded KHZ, write and time to 1528 * allow the matching interval to be extended at each write. 1529 */ 1530 kvm->arch.last_tsc_nsec = ns; 1531 kvm->arch.last_tsc_write = data; 1532 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1533 1534 vcpu->arch.last_guest_tsc = data; 1535 1536 /* Keep track of which generation this VCPU has synchronized to */ 1537 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1538 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1539 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1540 1541 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) 1542 update_ia32_tsc_adjust_msr(vcpu, offset); 1543 kvm_vcpu_write_tsc_offset(vcpu, offset); 1544 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1545 1546 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1547 if (!matched) { 1548 kvm->arch.nr_vcpus_matched_tsc = 0; 1549 } else if (!already_matched) { 1550 kvm->arch.nr_vcpus_matched_tsc++; 1551 } 1552 1553 kvm_track_tsc_matching(vcpu); 1554 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1555 } 1556 1557 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1558 1559 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1560 s64 adjustment) 1561 { 1562 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment); 1563 } 1564 1565 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1566 { 1567 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1568 WARN_ON(adjustment < 0); 1569 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1570 adjust_tsc_offset_guest(vcpu, adjustment); 1571 } 1572 1573 #ifdef CONFIG_X86_64 1574 1575 static u64 read_tsc(void) 1576 { 1577 u64 ret = (u64)rdtsc_ordered(); 1578 u64 last = pvclock_gtod_data.clock.cycle_last; 1579 1580 if (likely(ret >= last)) 1581 return ret; 1582 1583 /* 1584 * GCC likes to generate cmov here, but this branch is extremely 1585 * predictable (it's just a function of time and the likely is 1586 * very likely) and there's a data dependence, so force GCC 1587 * to generate a branch instead. I don't barrier() because 1588 * we don't actually need a barrier, and if this function 1589 * ever gets inlined it will generate worse code. 1590 */ 1591 asm volatile (""); 1592 return last; 1593 } 1594 1595 static inline u64 vgettsc(u64 *cycle_now) 1596 { 1597 long v; 1598 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1599 1600 *cycle_now = read_tsc(); 1601 1602 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1603 return v * gtod->clock.mult; 1604 } 1605 1606 static int do_monotonic_boot(s64 *t, u64 *cycle_now) 1607 { 1608 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1609 unsigned long seq; 1610 int mode; 1611 u64 ns; 1612 1613 do { 1614 seq = read_seqcount_begin(>od->seq); 1615 mode = gtod->clock.vclock_mode; 1616 ns = gtod->nsec_base; 1617 ns += vgettsc(cycle_now); 1618 ns >>= gtod->clock.shift; 1619 ns += gtod->boot_ns; 1620 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1621 *t = ns; 1622 1623 return mode; 1624 } 1625 1626 /* returns true if host is using tsc clocksource */ 1627 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now) 1628 { 1629 /* checked again under seqlock below */ 1630 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1631 return false; 1632 1633 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; 1634 } 1635 #endif 1636 1637 /* 1638 * 1639 * Assuming a stable TSC across physical CPUS, and a stable TSC 1640 * across virtual CPUs, the following condition is possible. 1641 * Each numbered line represents an event visible to both 1642 * CPUs at the next numbered event. 1643 * 1644 * "timespecX" represents host monotonic time. "tscX" represents 1645 * RDTSC value. 1646 * 1647 * VCPU0 on CPU0 | VCPU1 on CPU1 1648 * 1649 * 1. read timespec0,tsc0 1650 * 2. | timespec1 = timespec0 + N 1651 * | tsc1 = tsc0 + M 1652 * 3. transition to guest | transition to guest 1653 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1654 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1655 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1656 * 1657 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1658 * 1659 * - ret0 < ret1 1660 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1661 * ... 1662 * - 0 < N - M => M < N 1663 * 1664 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1665 * always the case (the difference between two distinct xtime instances 1666 * might be smaller then the difference between corresponding TSC reads, 1667 * when updating guest vcpus pvclock areas). 1668 * 1669 * To avoid that problem, do not allow visibility of distinct 1670 * system_timestamp/tsc_timestamp values simultaneously: use a master 1671 * copy of host monotonic time values. Update that master copy 1672 * in lockstep. 1673 * 1674 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1675 * 1676 */ 1677 1678 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1679 { 1680 #ifdef CONFIG_X86_64 1681 struct kvm_arch *ka = &kvm->arch; 1682 int vclock_mode; 1683 bool host_tsc_clocksource, vcpus_matched; 1684 1685 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1686 atomic_read(&kvm->online_vcpus)); 1687 1688 /* 1689 * If the host uses TSC clock, then passthrough TSC as stable 1690 * to the guest. 1691 */ 1692 host_tsc_clocksource = kvm_get_time_and_clockread( 1693 &ka->master_kernel_ns, 1694 &ka->master_cycle_now); 1695 1696 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1697 && !backwards_tsc_observed 1698 && !ka->boot_vcpu_runs_old_kvmclock; 1699 1700 if (ka->use_master_clock) 1701 atomic_set(&kvm_guest_has_master_clock, 1); 1702 1703 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1704 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1705 vcpus_matched); 1706 #endif 1707 } 1708 1709 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 1710 { 1711 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 1712 } 1713 1714 static void kvm_gen_update_masterclock(struct kvm *kvm) 1715 { 1716 #ifdef CONFIG_X86_64 1717 int i; 1718 struct kvm_vcpu *vcpu; 1719 struct kvm_arch *ka = &kvm->arch; 1720 1721 spin_lock(&ka->pvclock_gtod_sync_lock); 1722 kvm_make_mclock_inprogress_request(kvm); 1723 /* no guest entries from this point */ 1724 pvclock_update_vm_gtod_copy(kvm); 1725 1726 kvm_for_each_vcpu(i, vcpu, kvm) 1727 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1728 1729 /* guest entries allowed */ 1730 kvm_for_each_vcpu(i, vcpu, kvm) 1731 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); 1732 1733 spin_unlock(&ka->pvclock_gtod_sync_lock); 1734 #endif 1735 } 1736 1737 static u64 __get_kvmclock_ns(struct kvm *kvm) 1738 { 1739 struct kvm_arch *ka = &kvm->arch; 1740 struct pvclock_vcpu_time_info hv_clock; 1741 1742 spin_lock(&ka->pvclock_gtod_sync_lock); 1743 if (!ka->use_master_clock) { 1744 spin_unlock(&ka->pvclock_gtod_sync_lock); 1745 return ktime_get_boot_ns() + ka->kvmclock_offset; 1746 } 1747 1748 hv_clock.tsc_timestamp = ka->master_cycle_now; 1749 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 1750 spin_unlock(&ka->pvclock_gtod_sync_lock); 1751 1752 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 1753 &hv_clock.tsc_shift, 1754 &hv_clock.tsc_to_system_mul); 1755 return __pvclock_read_cycles(&hv_clock, rdtsc()); 1756 } 1757 1758 u64 get_kvmclock_ns(struct kvm *kvm) 1759 { 1760 unsigned long flags; 1761 s64 ns; 1762 1763 local_irq_save(flags); 1764 ns = __get_kvmclock_ns(kvm); 1765 local_irq_restore(flags); 1766 1767 return ns; 1768 } 1769 1770 static void kvm_setup_pvclock_page(struct kvm_vcpu *v) 1771 { 1772 struct kvm_vcpu_arch *vcpu = &v->arch; 1773 struct pvclock_vcpu_time_info guest_hv_clock; 1774 1775 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1776 &guest_hv_clock, sizeof(guest_hv_clock)))) 1777 return; 1778 1779 /* This VCPU is paused, but it's legal for a guest to read another 1780 * VCPU's kvmclock, so we really have to follow the specification where 1781 * it says that version is odd if data is being modified, and even after 1782 * it is consistent. 1783 * 1784 * Version field updates must be kept separate. This is because 1785 * kvm_write_guest_cached might use a "rep movs" instruction, and 1786 * writes within a string instruction are weakly ordered. So there 1787 * are three writes overall. 1788 * 1789 * As a small optimization, only write the version field in the first 1790 * and third write. The vcpu->pv_time cache is still valid, because the 1791 * version field is the first in the struct. 1792 */ 1793 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1794 1795 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1796 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1797 &vcpu->hv_clock, 1798 sizeof(vcpu->hv_clock.version)); 1799 1800 smp_wmb(); 1801 1802 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1803 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1804 1805 if (vcpu->pvclock_set_guest_stopped_request) { 1806 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 1807 vcpu->pvclock_set_guest_stopped_request = false; 1808 } 1809 1810 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1811 1812 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1813 &vcpu->hv_clock, 1814 sizeof(vcpu->hv_clock)); 1815 1816 smp_wmb(); 1817 1818 vcpu->hv_clock.version++; 1819 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1820 &vcpu->hv_clock, 1821 sizeof(vcpu->hv_clock.version)); 1822 } 1823 1824 static int kvm_guest_time_update(struct kvm_vcpu *v) 1825 { 1826 unsigned long flags, tgt_tsc_khz; 1827 struct kvm_vcpu_arch *vcpu = &v->arch; 1828 struct kvm_arch *ka = &v->kvm->arch; 1829 s64 kernel_ns; 1830 u64 tsc_timestamp, host_tsc; 1831 u8 pvclock_flags; 1832 bool use_master_clock; 1833 1834 kernel_ns = 0; 1835 host_tsc = 0; 1836 1837 /* 1838 * If the host uses TSC clock, then passthrough TSC as stable 1839 * to the guest. 1840 */ 1841 spin_lock(&ka->pvclock_gtod_sync_lock); 1842 use_master_clock = ka->use_master_clock; 1843 if (use_master_clock) { 1844 host_tsc = ka->master_cycle_now; 1845 kernel_ns = ka->master_kernel_ns; 1846 } 1847 spin_unlock(&ka->pvclock_gtod_sync_lock); 1848 1849 /* Keep irq disabled to prevent changes to the clock */ 1850 local_irq_save(flags); 1851 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 1852 if (unlikely(tgt_tsc_khz == 0)) { 1853 local_irq_restore(flags); 1854 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1855 return 1; 1856 } 1857 if (!use_master_clock) { 1858 host_tsc = rdtsc(); 1859 kernel_ns = ktime_get_boot_ns(); 1860 } 1861 1862 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 1863 1864 /* 1865 * We may have to catch up the TSC to match elapsed wall clock 1866 * time for two reasons, even if kvmclock is used. 1867 * 1) CPU could have been running below the maximum TSC rate 1868 * 2) Broken TSC compensation resets the base at each VCPU 1869 * entry to avoid unknown leaps of TSC even when running 1870 * again on the same CPU. This may cause apparent elapsed 1871 * time to disappear, and the guest to stand still or run 1872 * very slowly. 1873 */ 1874 if (vcpu->tsc_catchup) { 1875 u64 tsc = compute_guest_tsc(v, kernel_ns); 1876 if (tsc > tsc_timestamp) { 1877 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1878 tsc_timestamp = tsc; 1879 } 1880 } 1881 1882 local_irq_restore(flags); 1883 1884 /* With all the info we got, fill in the values */ 1885 1886 if (kvm_has_tsc_control) 1887 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 1888 1889 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 1890 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 1891 &vcpu->hv_clock.tsc_shift, 1892 &vcpu->hv_clock.tsc_to_system_mul); 1893 vcpu->hw_tsc_khz = tgt_tsc_khz; 1894 } 1895 1896 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1897 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1898 vcpu->last_guest_tsc = tsc_timestamp; 1899 1900 /* If the host uses TSC clocksource, then it is stable */ 1901 pvclock_flags = 0; 1902 if (use_master_clock) 1903 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1904 1905 vcpu->hv_clock.flags = pvclock_flags; 1906 1907 if (vcpu->pv_time_enabled) 1908 kvm_setup_pvclock_page(v); 1909 if (v == kvm_get_vcpu(v->kvm, 0)) 1910 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 1911 return 0; 1912 } 1913 1914 /* 1915 * kvmclock updates which are isolated to a given vcpu, such as 1916 * vcpu->cpu migration, should not allow system_timestamp from 1917 * the rest of the vcpus to remain static. Otherwise ntp frequency 1918 * correction applies to one vcpu's system_timestamp but not 1919 * the others. 1920 * 1921 * So in those cases, request a kvmclock update for all vcpus. 1922 * We need to rate-limit these requests though, as they can 1923 * considerably slow guests that have a large number of vcpus. 1924 * The time for a remote vcpu to update its kvmclock is bound 1925 * by the delay we use to rate-limit the updates. 1926 */ 1927 1928 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1929 1930 static void kvmclock_update_fn(struct work_struct *work) 1931 { 1932 int i; 1933 struct delayed_work *dwork = to_delayed_work(work); 1934 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1935 kvmclock_update_work); 1936 struct kvm *kvm = container_of(ka, struct kvm, arch); 1937 struct kvm_vcpu *vcpu; 1938 1939 kvm_for_each_vcpu(i, vcpu, kvm) { 1940 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1941 kvm_vcpu_kick(vcpu); 1942 } 1943 } 1944 1945 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1946 { 1947 struct kvm *kvm = v->kvm; 1948 1949 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1950 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1951 KVMCLOCK_UPDATE_DELAY); 1952 } 1953 1954 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 1955 1956 static void kvmclock_sync_fn(struct work_struct *work) 1957 { 1958 struct delayed_work *dwork = to_delayed_work(work); 1959 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1960 kvmclock_sync_work); 1961 struct kvm *kvm = container_of(ka, struct kvm, arch); 1962 1963 if (!kvmclock_periodic_sync) 1964 return; 1965 1966 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 1967 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 1968 KVMCLOCK_SYNC_PERIOD); 1969 } 1970 1971 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1972 { 1973 u64 mcg_cap = vcpu->arch.mcg_cap; 1974 unsigned bank_num = mcg_cap & 0xff; 1975 1976 switch (msr) { 1977 case MSR_IA32_MCG_STATUS: 1978 vcpu->arch.mcg_status = data; 1979 break; 1980 case MSR_IA32_MCG_CTL: 1981 if (!(mcg_cap & MCG_CTL_P)) 1982 return 1; 1983 if (data != 0 && data != ~(u64)0) 1984 return -1; 1985 vcpu->arch.mcg_ctl = data; 1986 break; 1987 default: 1988 if (msr >= MSR_IA32_MC0_CTL && 1989 msr < MSR_IA32_MCx_CTL(bank_num)) { 1990 u32 offset = msr - MSR_IA32_MC0_CTL; 1991 /* only 0 or all 1s can be written to IA32_MCi_CTL 1992 * some Linux kernels though clear bit 10 in bank 4 to 1993 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 1994 * this to avoid an uncatched #GP in the guest 1995 */ 1996 if ((offset & 0x3) == 0 && 1997 data != 0 && (data | (1 << 10)) != ~(u64)0) 1998 return -1; 1999 vcpu->arch.mce_banks[offset] = data; 2000 break; 2001 } 2002 return 1; 2003 } 2004 return 0; 2005 } 2006 2007 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 2008 { 2009 struct kvm *kvm = vcpu->kvm; 2010 int lm = is_long_mode(vcpu); 2011 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 2012 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 2013 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 2014 : kvm->arch.xen_hvm_config.blob_size_32; 2015 u32 page_num = data & ~PAGE_MASK; 2016 u64 page_addr = data & PAGE_MASK; 2017 u8 *page; 2018 int r; 2019 2020 r = -E2BIG; 2021 if (page_num >= blob_size) 2022 goto out; 2023 r = -ENOMEM; 2024 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 2025 if (IS_ERR(page)) { 2026 r = PTR_ERR(page); 2027 goto out; 2028 } 2029 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 2030 goto out_free; 2031 r = 0; 2032 out_free: 2033 kfree(page); 2034 out: 2035 return r; 2036 } 2037 2038 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2039 { 2040 gpa_t gpa = data & ~0x3f; 2041 2042 /* Bits 2:5 are reserved, Should be zero */ 2043 if (data & 0x3c) 2044 return 1; 2045 2046 vcpu->arch.apf.msr_val = data; 2047 2048 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2049 kvm_clear_async_pf_completion_queue(vcpu); 2050 kvm_async_pf_hash_reset(vcpu); 2051 return 0; 2052 } 2053 2054 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2055 sizeof(u32))) 2056 return 1; 2057 2058 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2059 kvm_async_pf_wakeup_all(vcpu); 2060 return 0; 2061 } 2062 2063 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2064 { 2065 vcpu->arch.pv_time_enabled = false; 2066 } 2067 2068 static void record_steal_time(struct kvm_vcpu *vcpu) 2069 { 2070 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2071 return; 2072 2073 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2074 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2075 return; 2076 2077 vcpu->arch.st.steal.preempted = 0; 2078 2079 if (vcpu->arch.st.steal.version & 1) 2080 vcpu->arch.st.steal.version += 1; /* first time write, random junk */ 2081 2082 vcpu->arch.st.steal.version += 1; 2083 2084 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2085 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2086 2087 smp_wmb(); 2088 2089 vcpu->arch.st.steal.steal += current->sched_info.run_delay - 2090 vcpu->arch.st.last_steal; 2091 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2092 2093 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2094 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2095 2096 smp_wmb(); 2097 2098 vcpu->arch.st.steal.version += 1; 2099 2100 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2101 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2102 } 2103 2104 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2105 { 2106 bool pr = false; 2107 u32 msr = msr_info->index; 2108 u64 data = msr_info->data; 2109 2110 switch (msr) { 2111 case MSR_AMD64_NB_CFG: 2112 case MSR_IA32_UCODE_REV: 2113 case MSR_IA32_UCODE_WRITE: 2114 case MSR_VM_HSAVE_PA: 2115 case MSR_AMD64_PATCH_LOADER: 2116 case MSR_AMD64_BU_CFG2: 2117 break; 2118 2119 case MSR_EFER: 2120 return set_efer(vcpu, data); 2121 case MSR_K7_HWCR: 2122 data &= ~(u64)0x40; /* ignore flush filter disable */ 2123 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2124 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2125 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2126 if (data != 0) { 2127 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2128 data); 2129 return 1; 2130 } 2131 break; 2132 case MSR_FAM10H_MMIO_CONF_BASE: 2133 if (data != 0) { 2134 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2135 "0x%llx\n", data); 2136 return 1; 2137 } 2138 break; 2139 case MSR_IA32_DEBUGCTLMSR: 2140 if (!data) { 2141 /* We support the non-activated case already */ 2142 break; 2143 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2144 /* Values other than LBR and BTF are vendor-specific, 2145 thus reserved and should throw a #GP */ 2146 return 1; 2147 } 2148 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2149 __func__, data); 2150 break; 2151 case 0x200 ... 0x2ff: 2152 return kvm_mtrr_set_msr(vcpu, msr, data); 2153 case MSR_IA32_APICBASE: 2154 return kvm_set_apic_base(vcpu, msr_info); 2155 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2156 return kvm_x2apic_msr_write(vcpu, msr, data); 2157 case MSR_IA32_TSCDEADLINE: 2158 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2159 break; 2160 case MSR_IA32_TSC_ADJUST: 2161 if (guest_cpuid_has_tsc_adjust(vcpu)) { 2162 if (!msr_info->host_initiated) { 2163 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2164 adjust_tsc_offset_guest(vcpu, adj); 2165 } 2166 vcpu->arch.ia32_tsc_adjust_msr = data; 2167 } 2168 break; 2169 case MSR_IA32_MISC_ENABLE: 2170 vcpu->arch.ia32_misc_enable_msr = data; 2171 break; 2172 case MSR_IA32_SMBASE: 2173 if (!msr_info->host_initiated) 2174 return 1; 2175 vcpu->arch.smbase = data; 2176 break; 2177 case MSR_KVM_WALL_CLOCK_NEW: 2178 case MSR_KVM_WALL_CLOCK: 2179 vcpu->kvm->arch.wall_clock = data; 2180 kvm_write_wall_clock(vcpu->kvm, data); 2181 break; 2182 case MSR_KVM_SYSTEM_TIME_NEW: 2183 case MSR_KVM_SYSTEM_TIME: { 2184 struct kvm_arch *ka = &vcpu->kvm->arch; 2185 2186 kvmclock_reset(vcpu); 2187 2188 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2189 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2190 2191 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2192 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, 2193 &vcpu->requests); 2194 2195 ka->boot_vcpu_runs_old_kvmclock = tmp; 2196 } 2197 2198 vcpu->arch.time = data; 2199 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2200 2201 /* we verify if the enable bit is set... */ 2202 if (!(data & 1)) 2203 break; 2204 2205 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2206 &vcpu->arch.pv_time, data & ~1ULL, 2207 sizeof(struct pvclock_vcpu_time_info))) 2208 vcpu->arch.pv_time_enabled = false; 2209 else 2210 vcpu->arch.pv_time_enabled = true; 2211 2212 break; 2213 } 2214 case MSR_KVM_ASYNC_PF_EN: 2215 if (kvm_pv_enable_async_pf(vcpu, data)) 2216 return 1; 2217 break; 2218 case MSR_KVM_STEAL_TIME: 2219 2220 if (unlikely(!sched_info_on())) 2221 return 1; 2222 2223 if (data & KVM_STEAL_RESERVED_MASK) 2224 return 1; 2225 2226 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2227 data & KVM_STEAL_VALID_BITS, 2228 sizeof(struct kvm_steal_time))) 2229 return 1; 2230 2231 vcpu->arch.st.msr_val = data; 2232 2233 if (!(data & KVM_MSR_ENABLED)) 2234 break; 2235 2236 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2237 2238 break; 2239 case MSR_KVM_PV_EOI_EN: 2240 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2241 return 1; 2242 break; 2243 2244 case MSR_IA32_MCG_CTL: 2245 case MSR_IA32_MCG_STATUS: 2246 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2247 return set_msr_mce(vcpu, msr, data); 2248 2249 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2250 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2251 pr = true; /* fall through */ 2252 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2253 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2254 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2255 return kvm_pmu_set_msr(vcpu, msr_info); 2256 2257 if (pr || data != 0) 2258 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2259 "0x%x data 0x%llx\n", msr, data); 2260 break; 2261 case MSR_K7_CLK_CTL: 2262 /* 2263 * Ignore all writes to this no longer documented MSR. 2264 * Writes are only relevant for old K7 processors, 2265 * all pre-dating SVM, but a recommended workaround from 2266 * AMD for these chips. It is possible to specify the 2267 * affected processor models on the command line, hence 2268 * the need to ignore the workaround. 2269 */ 2270 break; 2271 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2272 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2273 case HV_X64_MSR_CRASH_CTL: 2274 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2275 return kvm_hv_set_msr_common(vcpu, msr, data, 2276 msr_info->host_initiated); 2277 case MSR_IA32_BBL_CR_CTL3: 2278 /* Drop writes to this legacy MSR -- see rdmsr 2279 * counterpart for further detail. 2280 */ 2281 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data); 2282 break; 2283 case MSR_AMD64_OSVW_ID_LENGTH: 2284 if (!guest_cpuid_has_osvw(vcpu)) 2285 return 1; 2286 vcpu->arch.osvw.length = data; 2287 break; 2288 case MSR_AMD64_OSVW_STATUS: 2289 if (!guest_cpuid_has_osvw(vcpu)) 2290 return 1; 2291 vcpu->arch.osvw.status = data; 2292 break; 2293 default: 2294 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2295 return xen_hvm_config(vcpu, data); 2296 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2297 return kvm_pmu_set_msr(vcpu, msr_info); 2298 if (!ignore_msrs) { 2299 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", 2300 msr, data); 2301 return 1; 2302 } else { 2303 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 2304 msr, data); 2305 break; 2306 } 2307 } 2308 return 0; 2309 } 2310 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2311 2312 2313 /* 2314 * Reads an msr value (of 'msr_index') into 'pdata'. 2315 * Returns 0 on success, non-0 otherwise. 2316 * Assumes vcpu_load() was already called. 2317 */ 2318 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2319 { 2320 return kvm_x86_ops->get_msr(vcpu, msr); 2321 } 2322 EXPORT_SYMBOL_GPL(kvm_get_msr); 2323 2324 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2325 { 2326 u64 data; 2327 u64 mcg_cap = vcpu->arch.mcg_cap; 2328 unsigned bank_num = mcg_cap & 0xff; 2329 2330 switch (msr) { 2331 case MSR_IA32_P5_MC_ADDR: 2332 case MSR_IA32_P5_MC_TYPE: 2333 data = 0; 2334 break; 2335 case MSR_IA32_MCG_CAP: 2336 data = vcpu->arch.mcg_cap; 2337 break; 2338 case MSR_IA32_MCG_CTL: 2339 if (!(mcg_cap & MCG_CTL_P)) 2340 return 1; 2341 data = vcpu->arch.mcg_ctl; 2342 break; 2343 case MSR_IA32_MCG_STATUS: 2344 data = vcpu->arch.mcg_status; 2345 break; 2346 default: 2347 if (msr >= MSR_IA32_MC0_CTL && 2348 msr < MSR_IA32_MCx_CTL(bank_num)) { 2349 u32 offset = msr - MSR_IA32_MC0_CTL; 2350 data = vcpu->arch.mce_banks[offset]; 2351 break; 2352 } 2353 return 1; 2354 } 2355 *pdata = data; 2356 return 0; 2357 } 2358 2359 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2360 { 2361 switch (msr_info->index) { 2362 case MSR_IA32_PLATFORM_ID: 2363 case MSR_IA32_EBL_CR_POWERON: 2364 case MSR_IA32_DEBUGCTLMSR: 2365 case MSR_IA32_LASTBRANCHFROMIP: 2366 case MSR_IA32_LASTBRANCHTOIP: 2367 case MSR_IA32_LASTINTFROMIP: 2368 case MSR_IA32_LASTINTTOIP: 2369 case MSR_K8_SYSCFG: 2370 case MSR_K8_TSEG_ADDR: 2371 case MSR_K8_TSEG_MASK: 2372 case MSR_K7_HWCR: 2373 case MSR_VM_HSAVE_PA: 2374 case MSR_K8_INT_PENDING_MSG: 2375 case MSR_AMD64_NB_CFG: 2376 case MSR_FAM10H_MMIO_CONF_BASE: 2377 case MSR_AMD64_BU_CFG2: 2378 case MSR_IA32_PERF_CTL: 2379 msr_info->data = 0; 2380 break; 2381 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2382 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2383 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2384 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2385 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2386 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2387 msr_info->data = 0; 2388 break; 2389 case MSR_IA32_UCODE_REV: 2390 msr_info->data = 0x100000000ULL; 2391 break; 2392 case MSR_MTRRcap: 2393 case 0x200 ... 0x2ff: 2394 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2395 case 0xcd: /* fsb frequency */ 2396 msr_info->data = 3; 2397 break; 2398 /* 2399 * MSR_EBC_FREQUENCY_ID 2400 * Conservative value valid for even the basic CPU models. 2401 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2402 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2403 * and 266MHz for model 3, or 4. Set Core Clock 2404 * Frequency to System Bus Frequency Ratio to 1 (bits 2405 * 31:24) even though these are only valid for CPU 2406 * models > 2, however guests may end up dividing or 2407 * multiplying by zero otherwise. 2408 */ 2409 case MSR_EBC_FREQUENCY_ID: 2410 msr_info->data = 1 << 24; 2411 break; 2412 case MSR_IA32_APICBASE: 2413 msr_info->data = kvm_get_apic_base(vcpu); 2414 break; 2415 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2416 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2417 break; 2418 case MSR_IA32_TSCDEADLINE: 2419 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2420 break; 2421 case MSR_IA32_TSC_ADJUST: 2422 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2423 break; 2424 case MSR_IA32_MISC_ENABLE: 2425 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2426 break; 2427 case MSR_IA32_SMBASE: 2428 if (!msr_info->host_initiated) 2429 return 1; 2430 msr_info->data = vcpu->arch.smbase; 2431 break; 2432 case MSR_IA32_PERF_STATUS: 2433 /* TSC increment by tick */ 2434 msr_info->data = 1000ULL; 2435 /* CPU multiplier */ 2436 msr_info->data |= (((uint64_t)4ULL) << 40); 2437 break; 2438 case MSR_EFER: 2439 msr_info->data = vcpu->arch.efer; 2440 break; 2441 case MSR_KVM_WALL_CLOCK: 2442 case MSR_KVM_WALL_CLOCK_NEW: 2443 msr_info->data = vcpu->kvm->arch.wall_clock; 2444 break; 2445 case MSR_KVM_SYSTEM_TIME: 2446 case MSR_KVM_SYSTEM_TIME_NEW: 2447 msr_info->data = vcpu->arch.time; 2448 break; 2449 case MSR_KVM_ASYNC_PF_EN: 2450 msr_info->data = vcpu->arch.apf.msr_val; 2451 break; 2452 case MSR_KVM_STEAL_TIME: 2453 msr_info->data = vcpu->arch.st.msr_val; 2454 break; 2455 case MSR_KVM_PV_EOI_EN: 2456 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2457 break; 2458 case MSR_IA32_P5_MC_ADDR: 2459 case MSR_IA32_P5_MC_TYPE: 2460 case MSR_IA32_MCG_CAP: 2461 case MSR_IA32_MCG_CTL: 2462 case MSR_IA32_MCG_STATUS: 2463 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2464 return get_msr_mce(vcpu, msr_info->index, &msr_info->data); 2465 case MSR_K7_CLK_CTL: 2466 /* 2467 * Provide expected ramp-up count for K7. All other 2468 * are set to zero, indicating minimum divisors for 2469 * every field. 2470 * 2471 * This prevents guest kernels on AMD host with CPU 2472 * type 6, model 8 and higher from exploding due to 2473 * the rdmsr failing. 2474 */ 2475 msr_info->data = 0x20000000; 2476 break; 2477 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2478 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2479 case HV_X64_MSR_CRASH_CTL: 2480 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2481 return kvm_hv_get_msr_common(vcpu, 2482 msr_info->index, &msr_info->data); 2483 break; 2484 case MSR_IA32_BBL_CR_CTL3: 2485 /* This legacy MSR exists but isn't fully documented in current 2486 * silicon. It is however accessed by winxp in very narrow 2487 * scenarios where it sets bit #19, itself documented as 2488 * a "reserved" bit. Best effort attempt to source coherent 2489 * read data here should the balance of the register be 2490 * interpreted by the guest: 2491 * 2492 * L2 cache control register 3: 64GB range, 256KB size, 2493 * enabled, latency 0x1, configured 2494 */ 2495 msr_info->data = 0xbe702111; 2496 break; 2497 case MSR_AMD64_OSVW_ID_LENGTH: 2498 if (!guest_cpuid_has_osvw(vcpu)) 2499 return 1; 2500 msr_info->data = vcpu->arch.osvw.length; 2501 break; 2502 case MSR_AMD64_OSVW_STATUS: 2503 if (!guest_cpuid_has_osvw(vcpu)) 2504 return 1; 2505 msr_info->data = vcpu->arch.osvw.status; 2506 break; 2507 default: 2508 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2509 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2510 if (!ignore_msrs) { 2511 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", 2512 msr_info->index); 2513 return 1; 2514 } else { 2515 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index); 2516 msr_info->data = 0; 2517 } 2518 break; 2519 } 2520 return 0; 2521 } 2522 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2523 2524 /* 2525 * Read or write a bunch of msrs. All parameters are kernel addresses. 2526 * 2527 * @return number of msrs set successfully. 2528 */ 2529 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2530 struct kvm_msr_entry *entries, 2531 int (*do_msr)(struct kvm_vcpu *vcpu, 2532 unsigned index, u64 *data)) 2533 { 2534 int i, idx; 2535 2536 idx = srcu_read_lock(&vcpu->kvm->srcu); 2537 for (i = 0; i < msrs->nmsrs; ++i) 2538 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2539 break; 2540 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2541 2542 return i; 2543 } 2544 2545 /* 2546 * Read or write a bunch of msrs. Parameters are user addresses. 2547 * 2548 * @return number of msrs set successfully. 2549 */ 2550 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2551 int (*do_msr)(struct kvm_vcpu *vcpu, 2552 unsigned index, u64 *data), 2553 int writeback) 2554 { 2555 struct kvm_msrs msrs; 2556 struct kvm_msr_entry *entries; 2557 int r, n; 2558 unsigned size; 2559 2560 r = -EFAULT; 2561 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2562 goto out; 2563 2564 r = -E2BIG; 2565 if (msrs.nmsrs >= MAX_IO_MSRS) 2566 goto out; 2567 2568 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2569 entries = memdup_user(user_msrs->entries, size); 2570 if (IS_ERR(entries)) { 2571 r = PTR_ERR(entries); 2572 goto out; 2573 } 2574 2575 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2576 if (r < 0) 2577 goto out_free; 2578 2579 r = -EFAULT; 2580 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2581 goto out_free; 2582 2583 r = n; 2584 2585 out_free: 2586 kfree(entries); 2587 out: 2588 return r; 2589 } 2590 2591 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2592 { 2593 int r; 2594 2595 switch (ext) { 2596 case KVM_CAP_IRQCHIP: 2597 case KVM_CAP_HLT: 2598 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2599 case KVM_CAP_SET_TSS_ADDR: 2600 case KVM_CAP_EXT_CPUID: 2601 case KVM_CAP_EXT_EMUL_CPUID: 2602 case KVM_CAP_CLOCKSOURCE: 2603 case KVM_CAP_PIT: 2604 case KVM_CAP_NOP_IO_DELAY: 2605 case KVM_CAP_MP_STATE: 2606 case KVM_CAP_SYNC_MMU: 2607 case KVM_CAP_USER_NMI: 2608 case KVM_CAP_REINJECT_CONTROL: 2609 case KVM_CAP_IRQ_INJECT_STATUS: 2610 case KVM_CAP_IOEVENTFD: 2611 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2612 case KVM_CAP_PIT2: 2613 case KVM_CAP_PIT_STATE2: 2614 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2615 case KVM_CAP_XEN_HVM: 2616 case KVM_CAP_VCPU_EVENTS: 2617 case KVM_CAP_HYPERV: 2618 case KVM_CAP_HYPERV_VAPIC: 2619 case KVM_CAP_HYPERV_SPIN: 2620 case KVM_CAP_HYPERV_SYNIC: 2621 case KVM_CAP_PCI_SEGMENT: 2622 case KVM_CAP_DEBUGREGS: 2623 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2624 case KVM_CAP_XSAVE: 2625 case KVM_CAP_ASYNC_PF: 2626 case KVM_CAP_GET_TSC_KHZ: 2627 case KVM_CAP_KVMCLOCK_CTRL: 2628 case KVM_CAP_READONLY_MEM: 2629 case KVM_CAP_HYPERV_TIME: 2630 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2631 case KVM_CAP_TSC_DEADLINE_TIMER: 2632 case KVM_CAP_ENABLE_CAP_VM: 2633 case KVM_CAP_DISABLE_QUIRKS: 2634 case KVM_CAP_SET_BOOT_CPU_ID: 2635 case KVM_CAP_SPLIT_IRQCHIP: 2636 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2637 case KVM_CAP_ASSIGN_DEV_IRQ: 2638 case KVM_CAP_PCI_2_3: 2639 #endif 2640 r = 1; 2641 break; 2642 case KVM_CAP_ADJUST_CLOCK: 2643 r = KVM_CLOCK_TSC_STABLE; 2644 break; 2645 case KVM_CAP_X86_SMM: 2646 /* SMBASE is usually relocated above 1M on modern chipsets, 2647 * and SMM handlers might indeed rely on 4G segment limits, 2648 * so do not report SMM to be available if real mode is 2649 * emulated via vm86 mode. Still, do not go to great lengths 2650 * to avoid userspace's usage of the feature, because it is a 2651 * fringe case that is not enabled except via specific settings 2652 * of the module parameters. 2653 */ 2654 r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); 2655 break; 2656 case KVM_CAP_COALESCED_MMIO: 2657 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 2658 break; 2659 case KVM_CAP_VAPIC: 2660 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2661 break; 2662 case KVM_CAP_NR_VCPUS: 2663 r = KVM_SOFT_MAX_VCPUS; 2664 break; 2665 case KVM_CAP_MAX_VCPUS: 2666 r = KVM_MAX_VCPUS; 2667 break; 2668 case KVM_CAP_NR_MEMSLOTS: 2669 r = KVM_USER_MEM_SLOTS; 2670 break; 2671 case KVM_CAP_PV_MMU: /* obsolete */ 2672 r = 0; 2673 break; 2674 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2675 case KVM_CAP_IOMMU: 2676 r = iommu_present(&pci_bus_type); 2677 break; 2678 #endif 2679 case KVM_CAP_MCE: 2680 r = KVM_MAX_MCE_BANKS; 2681 break; 2682 case KVM_CAP_XCRS: 2683 r = boot_cpu_has(X86_FEATURE_XSAVE); 2684 break; 2685 case KVM_CAP_TSC_CONTROL: 2686 r = kvm_has_tsc_control; 2687 break; 2688 case KVM_CAP_X2APIC_API: 2689 r = KVM_X2APIC_API_VALID_FLAGS; 2690 break; 2691 default: 2692 r = 0; 2693 break; 2694 } 2695 return r; 2696 2697 } 2698 2699 long kvm_arch_dev_ioctl(struct file *filp, 2700 unsigned int ioctl, unsigned long arg) 2701 { 2702 void __user *argp = (void __user *)arg; 2703 long r; 2704 2705 switch (ioctl) { 2706 case KVM_GET_MSR_INDEX_LIST: { 2707 struct kvm_msr_list __user *user_msr_list = argp; 2708 struct kvm_msr_list msr_list; 2709 unsigned n; 2710 2711 r = -EFAULT; 2712 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2713 goto out; 2714 n = msr_list.nmsrs; 2715 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 2716 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2717 goto out; 2718 r = -E2BIG; 2719 if (n < msr_list.nmsrs) 2720 goto out; 2721 r = -EFAULT; 2722 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2723 num_msrs_to_save * sizeof(u32))) 2724 goto out; 2725 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2726 &emulated_msrs, 2727 num_emulated_msrs * sizeof(u32))) 2728 goto out; 2729 r = 0; 2730 break; 2731 } 2732 case KVM_GET_SUPPORTED_CPUID: 2733 case KVM_GET_EMULATED_CPUID: { 2734 struct kvm_cpuid2 __user *cpuid_arg = argp; 2735 struct kvm_cpuid2 cpuid; 2736 2737 r = -EFAULT; 2738 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2739 goto out; 2740 2741 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2742 ioctl); 2743 if (r) 2744 goto out; 2745 2746 r = -EFAULT; 2747 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2748 goto out; 2749 r = 0; 2750 break; 2751 } 2752 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2753 r = -EFAULT; 2754 if (copy_to_user(argp, &kvm_mce_cap_supported, 2755 sizeof(kvm_mce_cap_supported))) 2756 goto out; 2757 r = 0; 2758 break; 2759 } 2760 default: 2761 r = -EINVAL; 2762 } 2763 out: 2764 return r; 2765 } 2766 2767 static void wbinvd_ipi(void *garbage) 2768 { 2769 wbinvd(); 2770 } 2771 2772 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2773 { 2774 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2775 } 2776 2777 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu) 2778 { 2779 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests); 2780 } 2781 2782 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2783 { 2784 /* Address WBINVD may be executed by guest */ 2785 if (need_emulate_wbinvd(vcpu)) { 2786 if (kvm_x86_ops->has_wbinvd_exit()) 2787 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2788 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2789 smp_call_function_single(vcpu->cpu, 2790 wbinvd_ipi, NULL, 1); 2791 } 2792 2793 kvm_x86_ops->vcpu_load(vcpu, cpu); 2794 2795 /* Apply any externally detected TSC adjustments (due to suspend) */ 2796 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2797 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2798 vcpu->arch.tsc_offset_adjustment = 0; 2799 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2800 } 2801 2802 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2803 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2804 rdtsc() - vcpu->arch.last_host_tsc; 2805 if (tsc_delta < 0) 2806 mark_tsc_unstable("KVM discovered backwards TSC"); 2807 2808 if (check_tsc_unstable()) { 2809 u64 offset = kvm_compute_tsc_offset(vcpu, 2810 vcpu->arch.last_guest_tsc); 2811 kvm_vcpu_write_tsc_offset(vcpu, offset); 2812 vcpu->arch.tsc_catchup = 1; 2813 } 2814 if (kvm_lapic_hv_timer_in_use(vcpu) && 2815 kvm_x86_ops->set_hv_timer(vcpu, 2816 kvm_get_lapic_target_expiration_tsc(vcpu))) 2817 kvm_lapic_switch_to_sw_timer(vcpu); 2818 /* 2819 * On a host with synchronized TSC, there is no need to update 2820 * kvmclock on vcpu->cpu migration 2821 */ 2822 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2823 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2824 if (vcpu->cpu != cpu) 2825 kvm_migrate_timers(vcpu); 2826 vcpu->cpu = cpu; 2827 } 2828 2829 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2830 } 2831 2832 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 2833 { 2834 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2835 return; 2836 2837 vcpu->arch.st.steal.preempted = 1; 2838 2839 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime, 2840 &vcpu->arch.st.steal.preempted, 2841 offsetof(struct kvm_steal_time, preempted), 2842 sizeof(vcpu->arch.st.steal.preempted)); 2843 } 2844 2845 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2846 { 2847 int idx; 2848 /* 2849 * Disable page faults because we're in atomic context here. 2850 * kvm_write_guest_offset_cached() would call might_fault() 2851 * that relies on pagefault_disable() to tell if there's a 2852 * bug. NOTE: the write to guest memory may not go through if 2853 * during postcopy live migration or if there's heavy guest 2854 * paging. 2855 */ 2856 pagefault_disable(); 2857 /* 2858 * kvm_memslots() will be called by 2859 * kvm_write_guest_offset_cached() so take the srcu lock. 2860 */ 2861 idx = srcu_read_lock(&vcpu->kvm->srcu); 2862 kvm_steal_time_set_preempted(vcpu); 2863 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2864 pagefault_enable(); 2865 kvm_x86_ops->vcpu_put(vcpu); 2866 kvm_put_guest_fpu(vcpu); 2867 vcpu->arch.last_host_tsc = rdtsc(); 2868 } 2869 2870 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2871 struct kvm_lapic_state *s) 2872 { 2873 if (vcpu->arch.apicv_active) 2874 kvm_x86_ops->sync_pir_to_irr(vcpu); 2875 2876 return kvm_apic_get_state(vcpu, s); 2877 } 2878 2879 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2880 struct kvm_lapic_state *s) 2881 { 2882 int r; 2883 2884 r = kvm_apic_set_state(vcpu, s); 2885 if (r) 2886 return r; 2887 update_cr8_intercept(vcpu); 2888 2889 return 0; 2890 } 2891 2892 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 2893 { 2894 return (!lapic_in_kernel(vcpu) || 2895 kvm_apic_accept_pic_intr(vcpu)); 2896 } 2897 2898 /* 2899 * if userspace requested an interrupt window, check that the 2900 * interrupt window is open. 2901 * 2902 * No need to exit to userspace if we already have an interrupt queued. 2903 */ 2904 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 2905 { 2906 return kvm_arch_interrupt_allowed(vcpu) && 2907 !kvm_cpu_has_interrupt(vcpu) && 2908 !kvm_event_needs_reinjection(vcpu) && 2909 kvm_cpu_accept_dm_intr(vcpu); 2910 } 2911 2912 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 2913 struct kvm_interrupt *irq) 2914 { 2915 if (irq->irq >= KVM_NR_INTERRUPTS) 2916 return -EINVAL; 2917 2918 if (!irqchip_in_kernel(vcpu->kvm)) { 2919 kvm_queue_interrupt(vcpu, irq->irq, false); 2920 kvm_make_request(KVM_REQ_EVENT, vcpu); 2921 return 0; 2922 } 2923 2924 /* 2925 * With in-kernel LAPIC, we only use this to inject EXTINT, so 2926 * fail for in-kernel 8259. 2927 */ 2928 if (pic_in_kernel(vcpu->kvm)) 2929 return -ENXIO; 2930 2931 if (vcpu->arch.pending_external_vector != -1) 2932 return -EEXIST; 2933 2934 vcpu->arch.pending_external_vector = irq->irq; 2935 kvm_make_request(KVM_REQ_EVENT, vcpu); 2936 return 0; 2937 } 2938 2939 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 2940 { 2941 kvm_inject_nmi(vcpu); 2942 2943 return 0; 2944 } 2945 2946 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 2947 { 2948 kvm_make_request(KVM_REQ_SMI, vcpu); 2949 2950 return 0; 2951 } 2952 2953 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 2954 struct kvm_tpr_access_ctl *tac) 2955 { 2956 if (tac->flags) 2957 return -EINVAL; 2958 vcpu->arch.tpr_access_reporting = !!tac->enabled; 2959 return 0; 2960 } 2961 2962 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 2963 u64 mcg_cap) 2964 { 2965 int r; 2966 unsigned bank_num = mcg_cap & 0xff, bank; 2967 2968 r = -EINVAL; 2969 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 2970 goto out; 2971 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 2972 goto out; 2973 r = 0; 2974 vcpu->arch.mcg_cap = mcg_cap; 2975 /* Init IA32_MCG_CTL to all 1s */ 2976 if (mcg_cap & MCG_CTL_P) 2977 vcpu->arch.mcg_ctl = ~(u64)0; 2978 /* Init IA32_MCi_CTL to all 1s */ 2979 for (bank = 0; bank < bank_num; bank++) 2980 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 2981 2982 if (kvm_x86_ops->setup_mce) 2983 kvm_x86_ops->setup_mce(vcpu); 2984 out: 2985 return r; 2986 } 2987 2988 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 2989 struct kvm_x86_mce *mce) 2990 { 2991 u64 mcg_cap = vcpu->arch.mcg_cap; 2992 unsigned bank_num = mcg_cap & 0xff; 2993 u64 *banks = vcpu->arch.mce_banks; 2994 2995 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 2996 return -EINVAL; 2997 /* 2998 * if IA32_MCG_CTL is not all 1s, the uncorrected error 2999 * reporting is disabled 3000 */ 3001 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3002 vcpu->arch.mcg_ctl != ~(u64)0) 3003 return 0; 3004 banks += 4 * mce->bank; 3005 /* 3006 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3007 * reporting is disabled for the bank 3008 */ 3009 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3010 return 0; 3011 if (mce->status & MCI_STATUS_UC) { 3012 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3013 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3014 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3015 return 0; 3016 } 3017 if (banks[1] & MCI_STATUS_VAL) 3018 mce->status |= MCI_STATUS_OVER; 3019 banks[2] = mce->addr; 3020 banks[3] = mce->misc; 3021 vcpu->arch.mcg_status = mce->mcg_status; 3022 banks[1] = mce->status; 3023 kvm_queue_exception(vcpu, MC_VECTOR); 3024 } else if (!(banks[1] & MCI_STATUS_VAL) 3025 || !(banks[1] & MCI_STATUS_UC)) { 3026 if (banks[1] & MCI_STATUS_VAL) 3027 mce->status |= MCI_STATUS_OVER; 3028 banks[2] = mce->addr; 3029 banks[3] = mce->misc; 3030 banks[1] = mce->status; 3031 } else 3032 banks[1] |= MCI_STATUS_OVER; 3033 return 0; 3034 } 3035 3036 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3037 struct kvm_vcpu_events *events) 3038 { 3039 process_nmi(vcpu); 3040 events->exception.injected = 3041 vcpu->arch.exception.pending && 3042 !kvm_exception_is_soft(vcpu->arch.exception.nr); 3043 events->exception.nr = vcpu->arch.exception.nr; 3044 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3045 events->exception.pad = 0; 3046 events->exception.error_code = vcpu->arch.exception.error_code; 3047 3048 events->interrupt.injected = 3049 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 3050 events->interrupt.nr = vcpu->arch.interrupt.nr; 3051 events->interrupt.soft = 0; 3052 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3053 3054 events->nmi.injected = vcpu->arch.nmi_injected; 3055 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3056 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3057 events->nmi.pad = 0; 3058 3059 events->sipi_vector = 0; /* never valid when reporting to user space */ 3060 3061 events->smi.smm = is_smm(vcpu); 3062 events->smi.pending = vcpu->arch.smi_pending; 3063 events->smi.smm_inside_nmi = 3064 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 3065 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 3066 3067 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3068 | KVM_VCPUEVENT_VALID_SHADOW 3069 | KVM_VCPUEVENT_VALID_SMM); 3070 memset(&events->reserved, 0, sizeof(events->reserved)); 3071 } 3072 3073 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags); 3074 3075 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3076 struct kvm_vcpu_events *events) 3077 { 3078 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3079 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3080 | KVM_VCPUEVENT_VALID_SHADOW 3081 | KVM_VCPUEVENT_VALID_SMM)) 3082 return -EINVAL; 3083 3084 if (events->exception.injected && 3085 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 3086 return -EINVAL; 3087 3088 process_nmi(vcpu); 3089 vcpu->arch.exception.pending = events->exception.injected; 3090 vcpu->arch.exception.nr = events->exception.nr; 3091 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3092 vcpu->arch.exception.error_code = events->exception.error_code; 3093 3094 vcpu->arch.interrupt.pending = events->interrupt.injected; 3095 vcpu->arch.interrupt.nr = events->interrupt.nr; 3096 vcpu->arch.interrupt.soft = events->interrupt.soft; 3097 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3098 kvm_x86_ops->set_interrupt_shadow(vcpu, 3099 events->interrupt.shadow); 3100 3101 vcpu->arch.nmi_injected = events->nmi.injected; 3102 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3103 vcpu->arch.nmi_pending = events->nmi.pending; 3104 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3105 3106 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3107 lapic_in_kernel(vcpu)) 3108 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3109 3110 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 3111 u32 hflags = vcpu->arch.hflags; 3112 if (events->smi.smm) 3113 hflags |= HF_SMM_MASK; 3114 else 3115 hflags &= ~HF_SMM_MASK; 3116 kvm_set_hflags(vcpu, hflags); 3117 3118 vcpu->arch.smi_pending = events->smi.pending; 3119 if (events->smi.smm_inside_nmi) 3120 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3121 else 3122 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3123 if (lapic_in_kernel(vcpu)) { 3124 if (events->smi.latched_init) 3125 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3126 else 3127 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3128 } 3129 } 3130 3131 kvm_make_request(KVM_REQ_EVENT, vcpu); 3132 3133 return 0; 3134 } 3135 3136 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3137 struct kvm_debugregs *dbgregs) 3138 { 3139 unsigned long val; 3140 3141 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3142 kvm_get_dr(vcpu, 6, &val); 3143 dbgregs->dr6 = val; 3144 dbgregs->dr7 = vcpu->arch.dr7; 3145 dbgregs->flags = 0; 3146 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3147 } 3148 3149 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3150 struct kvm_debugregs *dbgregs) 3151 { 3152 if (dbgregs->flags) 3153 return -EINVAL; 3154 3155 if (dbgregs->dr6 & ~0xffffffffull) 3156 return -EINVAL; 3157 if (dbgregs->dr7 & ~0xffffffffull) 3158 return -EINVAL; 3159 3160 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3161 kvm_update_dr0123(vcpu); 3162 vcpu->arch.dr6 = dbgregs->dr6; 3163 kvm_update_dr6(vcpu); 3164 vcpu->arch.dr7 = dbgregs->dr7; 3165 kvm_update_dr7(vcpu); 3166 3167 return 0; 3168 } 3169 3170 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3171 3172 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3173 { 3174 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3175 u64 xstate_bv = xsave->header.xfeatures; 3176 u64 valid; 3177 3178 /* 3179 * Copy legacy XSAVE area, to avoid complications with CPUID 3180 * leaves 0 and 1 in the loop below. 3181 */ 3182 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3183 3184 /* Set XSTATE_BV */ 3185 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3186 3187 /* 3188 * Copy each region from the possibly compacted offset to the 3189 * non-compacted offset. 3190 */ 3191 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3192 while (valid) { 3193 u64 feature = valid & -valid; 3194 int index = fls64(feature) - 1; 3195 void *src = get_xsave_addr(xsave, feature); 3196 3197 if (src) { 3198 u32 size, offset, ecx, edx; 3199 cpuid_count(XSTATE_CPUID, index, 3200 &size, &offset, &ecx, &edx); 3201 memcpy(dest + offset, src, size); 3202 } 3203 3204 valid -= feature; 3205 } 3206 } 3207 3208 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3209 { 3210 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3211 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3212 u64 valid; 3213 3214 /* 3215 * Copy legacy XSAVE area, to avoid complications with CPUID 3216 * leaves 0 and 1 in the loop below. 3217 */ 3218 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3219 3220 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3221 xsave->header.xfeatures = xstate_bv; 3222 if (boot_cpu_has(X86_FEATURE_XSAVES)) 3223 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3224 3225 /* 3226 * Copy each region from the non-compacted offset to the 3227 * possibly compacted offset. 3228 */ 3229 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3230 while (valid) { 3231 u64 feature = valid & -valid; 3232 int index = fls64(feature) - 1; 3233 void *dest = get_xsave_addr(xsave, feature); 3234 3235 if (dest) { 3236 u32 size, offset, ecx, edx; 3237 cpuid_count(XSTATE_CPUID, index, 3238 &size, &offset, &ecx, &edx); 3239 memcpy(dest, src + offset, size); 3240 } 3241 3242 valid -= feature; 3243 } 3244 } 3245 3246 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3247 struct kvm_xsave *guest_xsave) 3248 { 3249 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3250 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3251 fill_xsave((u8 *) guest_xsave->region, vcpu); 3252 } else { 3253 memcpy(guest_xsave->region, 3254 &vcpu->arch.guest_fpu.state.fxsave, 3255 sizeof(struct fxregs_state)); 3256 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3257 XFEATURE_MASK_FPSSE; 3258 } 3259 } 3260 3261 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3262 struct kvm_xsave *guest_xsave) 3263 { 3264 u64 xstate_bv = 3265 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3266 3267 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3268 /* 3269 * Here we allow setting states that are not present in 3270 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3271 * with old userspace. 3272 */ 3273 if (xstate_bv & ~kvm_supported_xcr0()) 3274 return -EINVAL; 3275 load_xsave(vcpu, (u8 *)guest_xsave->region); 3276 } else { 3277 if (xstate_bv & ~XFEATURE_MASK_FPSSE) 3278 return -EINVAL; 3279 memcpy(&vcpu->arch.guest_fpu.state.fxsave, 3280 guest_xsave->region, sizeof(struct fxregs_state)); 3281 } 3282 return 0; 3283 } 3284 3285 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3286 struct kvm_xcrs *guest_xcrs) 3287 { 3288 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 3289 guest_xcrs->nr_xcrs = 0; 3290 return; 3291 } 3292 3293 guest_xcrs->nr_xcrs = 1; 3294 guest_xcrs->flags = 0; 3295 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3296 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3297 } 3298 3299 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3300 struct kvm_xcrs *guest_xcrs) 3301 { 3302 int i, r = 0; 3303 3304 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 3305 return -EINVAL; 3306 3307 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3308 return -EINVAL; 3309 3310 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3311 /* Only support XCR0 currently */ 3312 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3313 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3314 guest_xcrs->xcrs[i].value); 3315 break; 3316 } 3317 if (r) 3318 r = -EINVAL; 3319 return r; 3320 } 3321 3322 /* 3323 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3324 * stopped by the hypervisor. This function will be called from the host only. 3325 * EINVAL is returned when the host attempts to set the flag for a guest that 3326 * does not support pv clocks. 3327 */ 3328 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3329 { 3330 if (!vcpu->arch.pv_time_enabled) 3331 return -EINVAL; 3332 vcpu->arch.pvclock_set_guest_stopped_request = true; 3333 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3334 return 0; 3335 } 3336 3337 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 3338 struct kvm_enable_cap *cap) 3339 { 3340 if (cap->flags) 3341 return -EINVAL; 3342 3343 switch (cap->cap) { 3344 case KVM_CAP_HYPERV_SYNIC: 3345 if (!irqchip_in_kernel(vcpu->kvm)) 3346 return -EINVAL; 3347 return kvm_hv_activate_synic(vcpu); 3348 default: 3349 return -EINVAL; 3350 } 3351 } 3352 3353 long kvm_arch_vcpu_ioctl(struct file *filp, 3354 unsigned int ioctl, unsigned long arg) 3355 { 3356 struct kvm_vcpu *vcpu = filp->private_data; 3357 void __user *argp = (void __user *)arg; 3358 int r; 3359 union { 3360 struct kvm_lapic_state *lapic; 3361 struct kvm_xsave *xsave; 3362 struct kvm_xcrs *xcrs; 3363 void *buffer; 3364 } u; 3365 3366 u.buffer = NULL; 3367 switch (ioctl) { 3368 case KVM_GET_LAPIC: { 3369 r = -EINVAL; 3370 if (!lapic_in_kernel(vcpu)) 3371 goto out; 3372 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3373 3374 r = -ENOMEM; 3375 if (!u.lapic) 3376 goto out; 3377 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3378 if (r) 3379 goto out; 3380 r = -EFAULT; 3381 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3382 goto out; 3383 r = 0; 3384 break; 3385 } 3386 case KVM_SET_LAPIC: { 3387 r = -EINVAL; 3388 if (!lapic_in_kernel(vcpu)) 3389 goto out; 3390 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3391 if (IS_ERR(u.lapic)) 3392 return PTR_ERR(u.lapic); 3393 3394 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3395 break; 3396 } 3397 case KVM_INTERRUPT: { 3398 struct kvm_interrupt irq; 3399 3400 r = -EFAULT; 3401 if (copy_from_user(&irq, argp, sizeof irq)) 3402 goto out; 3403 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3404 break; 3405 } 3406 case KVM_NMI: { 3407 r = kvm_vcpu_ioctl_nmi(vcpu); 3408 break; 3409 } 3410 case KVM_SMI: { 3411 r = kvm_vcpu_ioctl_smi(vcpu); 3412 break; 3413 } 3414 case KVM_SET_CPUID: { 3415 struct kvm_cpuid __user *cpuid_arg = argp; 3416 struct kvm_cpuid cpuid; 3417 3418 r = -EFAULT; 3419 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3420 goto out; 3421 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3422 break; 3423 } 3424 case KVM_SET_CPUID2: { 3425 struct kvm_cpuid2 __user *cpuid_arg = argp; 3426 struct kvm_cpuid2 cpuid; 3427 3428 r = -EFAULT; 3429 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3430 goto out; 3431 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3432 cpuid_arg->entries); 3433 break; 3434 } 3435 case KVM_GET_CPUID2: { 3436 struct kvm_cpuid2 __user *cpuid_arg = argp; 3437 struct kvm_cpuid2 cpuid; 3438 3439 r = -EFAULT; 3440 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3441 goto out; 3442 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3443 cpuid_arg->entries); 3444 if (r) 3445 goto out; 3446 r = -EFAULT; 3447 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3448 goto out; 3449 r = 0; 3450 break; 3451 } 3452 case KVM_GET_MSRS: 3453 r = msr_io(vcpu, argp, do_get_msr, 1); 3454 break; 3455 case KVM_SET_MSRS: 3456 r = msr_io(vcpu, argp, do_set_msr, 0); 3457 break; 3458 case KVM_TPR_ACCESS_REPORTING: { 3459 struct kvm_tpr_access_ctl tac; 3460 3461 r = -EFAULT; 3462 if (copy_from_user(&tac, argp, sizeof tac)) 3463 goto out; 3464 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3465 if (r) 3466 goto out; 3467 r = -EFAULT; 3468 if (copy_to_user(argp, &tac, sizeof tac)) 3469 goto out; 3470 r = 0; 3471 break; 3472 }; 3473 case KVM_SET_VAPIC_ADDR: { 3474 struct kvm_vapic_addr va; 3475 int idx; 3476 3477 r = -EINVAL; 3478 if (!lapic_in_kernel(vcpu)) 3479 goto out; 3480 r = -EFAULT; 3481 if (copy_from_user(&va, argp, sizeof va)) 3482 goto out; 3483 idx = srcu_read_lock(&vcpu->kvm->srcu); 3484 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3485 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3486 break; 3487 } 3488 case KVM_X86_SETUP_MCE: { 3489 u64 mcg_cap; 3490 3491 r = -EFAULT; 3492 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3493 goto out; 3494 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3495 break; 3496 } 3497 case KVM_X86_SET_MCE: { 3498 struct kvm_x86_mce mce; 3499 3500 r = -EFAULT; 3501 if (copy_from_user(&mce, argp, sizeof mce)) 3502 goto out; 3503 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3504 break; 3505 } 3506 case KVM_GET_VCPU_EVENTS: { 3507 struct kvm_vcpu_events events; 3508 3509 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3510 3511 r = -EFAULT; 3512 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3513 break; 3514 r = 0; 3515 break; 3516 } 3517 case KVM_SET_VCPU_EVENTS: { 3518 struct kvm_vcpu_events events; 3519 3520 r = -EFAULT; 3521 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3522 break; 3523 3524 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3525 break; 3526 } 3527 case KVM_GET_DEBUGREGS: { 3528 struct kvm_debugregs dbgregs; 3529 3530 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3531 3532 r = -EFAULT; 3533 if (copy_to_user(argp, &dbgregs, 3534 sizeof(struct kvm_debugregs))) 3535 break; 3536 r = 0; 3537 break; 3538 } 3539 case KVM_SET_DEBUGREGS: { 3540 struct kvm_debugregs dbgregs; 3541 3542 r = -EFAULT; 3543 if (copy_from_user(&dbgregs, argp, 3544 sizeof(struct kvm_debugregs))) 3545 break; 3546 3547 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3548 break; 3549 } 3550 case KVM_GET_XSAVE: { 3551 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3552 r = -ENOMEM; 3553 if (!u.xsave) 3554 break; 3555 3556 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3557 3558 r = -EFAULT; 3559 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3560 break; 3561 r = 0; 3562 break; 3563 } 3564 case KVM_SET_XSAVE: { 3565 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3566 if (IS_ERR(u.xsave)) 3567 return PTR_ERR(u.xsave); 3568 3569 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3570 break; 3571 } 3572 case KVM_GET_XCRS: { 3573 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3574 r = -ENOMEM; 3575 if (!u.xcrs) 3576 break; 3577 3578 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3579 3580 r = -EFAULT; 3581 if (copy_to_user(argp, u.xcrs, 3582 sizeof(struct kvm_xcrs))) 3583 break; 3584 r = 0; 3585 break; 3586 } 3587 case KVM_SET_XCRS: { 3588 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3589 if (IS_ERR(u.xcrs)) 3590 return PTR_ERR(u.xcrs); 3591 3592 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3593 break; 3594 } 3595 case KVM_SET_TSC_KHZ: { 3596 u32 user_tsc_khz; 3597 3598 r = -EINVAL; 3599 user_tsc_khz = (u32)arg; 3600 3601 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3602 goto out; 3603 3604 if (user_tsc_khz == 0) 3605 user_tsc_khz = tsc_khz; 3606 3607 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 3608 r = 0; 3609 3610 goto out; 3611 } 3612 case KVM_GET_TSC_KHZ: { 3613 r = vcpu->arch.virtual_tsc_khz; 3614 goto out; 3615 } 3616 case KVM_KVMCLOCK_CTRL: { 3617 r = kvm_set_guest_paused(vcpu); 3618 goto out; 3619 } 3620 case KVM_ENABLE_CAP: { 3621 struct kvm_enable_cap cap; 3622 3623 r = -EFAULT; 3624 if (copy_from_user(&cap, argp, sizeof(cap))) 3625 goto out; 3626 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 3627 break; 3628 } 3629 default: 3630 r = -EINVAL; 3631 } 3632 out: 3633 kfree(u.buffer); 3634 return r; 3635 } 3636 3637 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3638 { 3639 return VM_FAULT_SIGBUS; 3640 } 3641 3642 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3643 { 3644 int ret; 3645 3646 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3647 return -EINVAL; 3648 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3649 return ret; 3650 } 3651 3652 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3653 u64 ident_addr) 3654 { 3655 kvm->arch.ept_identity_map_addr = ident_addr; 3656 return 0; 3657 } 3658 3659 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3660 u32 kvm_nr_mmu_pages) 3661 { 3662 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3663 return -EINVAL; 3664 3665 mutex_lock(&kvm->slots_lock); 3666 3667 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3668 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3669 3670 mutex_unlock(&kvm->slots_lock); 3671 return 0; 3672 } 3673 3674 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3675 { 3676 return kvm->arch.n_max_mmu_pages; 3677 } 3678 3679 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3680 { 3681 int r; 3682 3683 r = 0; 3684 switch (chip->chip_id) { 3685 case KVM_IRQCHIP_PIC_MASTER: 3686 memcpy(&chip->chip.pic, 3687 &pic_irqchip(kvm)->pics[0], 3688 sizeof(struct kvm_pic_state)); 3689 break; 3690 case KVM_IRQCHIP_PIC_SLAVE: 3691 memcpy(&chip->chip.pic, 3692 &pic_irqchip(kvm)->pics[1], 3693 sizeof(struct kvm_pic_state)); 3694 break; 3695 case KVM_IRQCHIP_IOAPIC: 3696 r = kvm_get_ioapic(kvm, &chip->chip.ioapic); 3697 break; 3698 default: 3699 r = -EINVAL; 3700 break; 3701 } 3702 return r; 3703 } 3704 3705 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3706 { 3707 int r; 3708 3709 r = 0; 3710 switch (chip->chip_id) { 3711 case KVM_IRQCHIP_PIC_MASTER: 3712 spin_lock(&pic_irqchip(kvm)->lock); 3713 memcpy(&pic_irqchip(kvm)->pics[0], 3714 &chip->chip.pic, 3715 sizeof(struct kvm_pic_state)); 3716 spin_unlock(&pic_irqchip(kvm)->lock); 3717 break; 3718 case KVM_IRQCHIP_PIC_SLAVE: 3719 spin_lock(&pic_irqchip(kvm)->lock); 3720 memcpy(&pic_irqchip(kvm)->pics[1], 3721 &chip->chip.pic, 3722 sizeof(struct kvm_pic_state)); 3723 spin_unlock(&pic_irqchip(kvm)->lock); 3724 break; 3725 case KVM_IRQCHIP_IOAPIC: 3726 r = kvm_set_ioapic(kvm, &chip->chip.ioapic); 3727 break; 3728 default: 3729 r = -EINVAL; 3730 break; 3731 } 3732 kvm_pic_update_irq(pic_irqchip(kvm)); 3733 return r; 3734 } 3735 3736 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3737 { 3738 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 3739 3740 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 3741 3742 mutex_lock(&kps->lock); 3743 memcpy(ps, &kps->channels, sizeof(*ps)); 3744 mutex_unlock(&kps->lock); 3745 return 0; 3746 } 3747 3748 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3749 { 3750 int i; 3751 struct kvm_pit *pit = kvm->arch.vpit; 3752 3753 mutex_lock(&pit->pit_state.lock); 3754 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 3755 for (i = 0; i < 3; i++) 3756 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 3757 mutex_unlock(&pit->pit_state.lock); 3758 return 0; 3759 } 3760 3761 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3762 { 3763 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3764 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3765 sizeof(ps->channels)); 3766 ps->flags = kvm->arch.vpit->pit_state.flags; 3767 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3768 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3769 return 0; 3770 } 3771 3772 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3773 { 3774 int start = 0; 3775 int i; 3776 u32 prev_legacy, cur_legacy; 3777 struct kvm_pit *pit = kvm->arch.vpit; 3778 3779 mutex_lock(&pit->pit_state.lock); 3780 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3781 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3782 if (!prev_legacy && cur_legacy) 3783 start = 1; 3784 memcpy(&pit->pit_state.channels, &ps->channels, 3785 sizeof(pit->pit_state.channels)); 3786 pit->pit_state.flags = ps->flags; 3787 for (i = 0; i < 3; i++) 3788 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 3789 start && i == 0); 3790 mutex_unlock(&pit->pit_state.lock); 3791 return 0; 3792 } 3793 3794 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3795 struct kvm_reinject_control *control) 3796 { 3797 struct kvm_pit *pit = kvm->arch.vpit; 3798 3799 if (!pit) 3800 return -ENXIO; 3801 3802 /* pit->pit_state.lock was overloaded to prevent userspace from getting 3803 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 3804 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 3805 */ 3806 mutex_lock(&pit->pit_state.lock); 3807 kvm_pit_set_reinject(pit, control->pit_reinject); 3808 mutex_unlock(&pit->pit_state.lock); 3809 3810 return 0; 3811 } 3812 3813 /** 3814 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3815 * @kvm: kvm instance 3816 * @log: slot id and address to which we copy the log 3817 * 3818 * Steps 1-4 below provide general overview of dirty page logging. See 3819 * kvm_get_dirty_log_protect() function description for additional details. 3820 * 3821 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 3822 * always flush the TLB (step 4) even if previous step failed and the dirty 3823 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 3824 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 3825 * writes will be marked dirty for next log read. 3826 * 3827 * 1. Take a snapshot of the bit and clear it if needed. 3828 * 2. Write protect the corresponding page. 3829 * 3. Copy the snapshot to the userspace. 3830 * 4. Flush TLB's if needed. 3831 */ 3832 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3833 { 3834 bool is_dirty = false; 3835 int r; 3836 3837 mutex_lock(&kvm->slots_lock); 3838 3839 /* 3840 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 3841 */ 3842 if (kvm_x86_ops->flush_log_dirty) 3843 kvm_x86_ops->flush_log_dirty(kvm); 3844 3845 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 3846 3847 /* 3848 * All the TLBs can be flushed out of mmu lock, see the comments in 3849 * kvm_mmu_slot_remove_write_access(). 3850 */ 3851 lockdep_assert_held(&kvm->slots_lock); 3852 if (is_dirty) 3853 kvm_flush_remote_tlbs(kvm); 3854 3855 mutex_unlock(&kvm->slots_lock); 3856 return r; 3857 } 3858 3859 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3860 bool line_status) 3861 { 3862 if (!irqchip_in_kernel(kvm)) 3863 return -ENXIO; 3864 3865 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3866 irq_event->irq, irq_event->level, 3867 line_status); 3868 return 0; 3869 } 3870 3871 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 3872 struct kvm_enable_cap *cap) 3873 { 3874 int r; 3875 3876 if (cap->flags) 3877 return -EINVAL; 3878 3879 switch (cap->cap) { 3880 case KVM_CAP_DISABLE_QUIRKS: 3881 kvm->arch.disabled_quirks = cap->args[0]; 3882 r = 0; 3883 break; 3884 case KVM_CAP_SPLIT_IRQCHIP: { 3885 mutex_lock(&kvm->lock); 3886 r = -EINVAL; 3887 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 3888 goto split_irqchip_unlock; 3889 r = -EEXIST; 3890 if (irqchip_in_kernel(kvm)) 3891 goto split_irqchip_unlock; 3892 if (kvm->created_vcpus) 3893 goto split_irqchip_unlock; 3894 r = kvm_setup_empty_irq_routing(kvm); 3895 if (r) 3896 goto split_irqchip_unlock; 3897 /* Pairs with irqchip_in_kernel. */ 3898 smp_wmb(); 3899 kvm->arch.irqchip_split = true; 3900 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 3901 r = 0; 3902 split_irqchip_unlock: 3903 mutex_unlock(&kvm->lock); 3904 break; 3905 } 3906 case KVM_CAP_X2APIC_API: 3907 r = -EINVAL; 3908 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 3909 break; 3910 3911 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 3912 kvm->arch.x2apic_format = true; 3913 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 3914 kvm->arch.x2apic_broadcast_quirk_disabled = true; 3915 3916 r = 0; 3917 break; 3918 default: 3919 r = -EINVAL; 3920 break; 3921 } 3922 return r; 3923 } 3924 3925 long kvm_arch_vm_ioctl(struct file *filp, 3926 unsigned int ioctl, unsigned long arg) 3927 { 3928 struct kvm *kvm = filp->private_data; 3929 void __user *argp = (void __user *)arg; 3930 int r = -ENOTTY; 3931 /* 3932 * This union makes it completely explicit to gcc-3.x 3933 * that these two variables' stack usage should be 3934 * combined, not added together. 3935 */ 3936 union { 3937 struct kvm_pit_state ps; 3938 struct kvm_pit_state2 ps2; 3939 struct kvm_pit_config pit_config; 3940 } u; 3941 3942 switch (ioctl) { 3943 case KVM_SET_TSS_ADDR: 3944 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 3945 break; 3946 case KVM_SET_IDENTITY_MAP_ADDR: { 3947 u64 ident_addr; 3948 3949 r = -EFAULT; 3950 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 3951 goto out; 3952 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 3953 break; 3954 } 3955 case KVM_SET_NR_MMU_PAGES: 3956 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 3957 break; 3958 case KVM_GET_NR_MMU_PAGES: 3959 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 3960 break; 3961 case KVM_CREATE_IRQCHIP: { 3962 struct kvm_pic *vpic; 3963 3964 mutex_lock(&kvm->lock); 3965 r = -EEXIST; 3966 if (kvm->arch.vpic) 3967 goto create_irqchip_unlock; 3968 r = -EINVAL; 3969 if (kvm->created_vcpus) 3970 goto create_irqchip_unlock; 3971 r = -ENOMEM; 3972 vpic = kvm_create_pic(kvm); 3973 if (vpic) { 3974 r = kvm_ioapic_init(kvm); 3975 if (r) { 3976 mutex_lock(&kvm->slots_lock); 3977 kvm_destroy_pic(vpic); 3978 mutex_unlock(&kvm->slots_lock); 3979 goto create_irqchip_unlock; 3980 } 3981 } else 3982 goto create_irqchip_unlock; 3983 r = kvm_setup_default_irq_routing(kvm); 3984 if (r) { 3985 mutex_lock(&kvm->slots_lock); 3986 mutex_lock(&kvm->irq_lock); 3987 kvm_ioapic_destroy(kvm); 3988 kvm_destroy_pic(vpic); 3989 mutex_unlock(&kvm->irq_lock); 3990 mutex_unlock(&kvm->slots_lock); 3991 goto create_irqchip_unlock; 3992 } 3993 /* Write kvm->irq_routing before kvm->arch.vpic. */ 3994 smp_wmb(); 3995 kvm->arch.vpic = vpic; 3996 create_irqchip_unlock: 3997 mutex_unlock(&kvm->lock); 3998 break; 3999 } 4000 case KVM_CREATE_PIT: 4001 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 4002 goto create_pit; 4003 case KVM_CREATE_PIT2: 4004 r = -EFAULT; 4005 if (copy_from_user(&u.pit_config, argp, 4006 sizeof(struct kvm_pit_config))) 4007 goto out; 4008 create_pit: 4009 mutex_lock(&kvm->lock); 4010 r = -EEXIST; 4011 if (kvm->arch.vpit) 4012 goto create_pit_unlock; 4013 r = -ENOMEM; 4014 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 4015 if (kvm->arch.vpit) 4016 r = 0; 4017 create_pit_unlock: 4018 mutex_unlock(&kvm->lock); 4019 break; 4020 case KVM_GET_IRQCHIP: { 4021 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4022 struct kvm_irqchip *chip; 4023 4024 chip = memdup_user(argp, sizeof(*chip)); 4025 if (IS_ERR(chip)) { 4026 r = PTR_ERR(chip); 4027 goto out; 4028 } 4029 4030 r = -ENXIO; 4031 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) 4032 goto get_irqchip_out; 4033 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 4034 if (r) 4035 goto get_irqchip_out; 4036 r = -EFAULT; 4037 if (copy_to_user(argp, chip, sizeof *chip)) 4038 goto get_irqchip_out; 4039 r = 0; 4040 get_irqchip_out: 4041 kfree(chip); 4042 break; 4043 } 4044 case KVM_SET_IRQCHIP: { 4045 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4046 struct kvm_irqchip *chip; 4047 4048 chip = memdup_user(argp, sizeof(*chip)); 4049 if (IS_ERR(chip)) { 4050 r = PTR_ERR(chip); 4051 goto out; 4052 } 4053 4054 r = -ENXIO; 4055 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) 4056 goto set_irqchip_out; 4057 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 4058 if (r) 4059 goto set_irqchip_out; 4060 r = 0; 4061 set_irqchip_out: 4062 kfree(chip); 4063 break; 4064 } 4065 case KVM_GET_PIT: { 4066 r = -EFAULT; 4067 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 4068 goto out; 4069 r = -ENXIO; 4070 if (!kvm->arch.vpit) 4071 goto out; 4072 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 4073 if (r) 4074 goto out; 4075 r = -EFAULT; 4076 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 4077 goto out; 4078 r = 0; 4079 break; 4080 } 4081 case KVM_SET_PIT: { 4082 r = -EFAULT; 4083 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 4084 goto out; 4085 r = -ENXIO; 4086 if (!kvm->arch.vpit) 4087 goto out; 4088 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 4089 break; 4090 } 4091 case KVM_GET_PIT2: { 4092 r = -ENXIO; 4093 if (!kvm->arch.vpit) 4094 goto out; 4095 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 4096 if (r) 4097 goto out; 4098 r = -EFAULT; 4099 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 4100 goto out; 4101 r = 0; 4102 break; 4103 } 4104 case KVM_SET_PIT2: { 4105 r = -EFAULT; 4106 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 4107 goto out; 4108 r = -ENXIO; 4109 if (!kvm->arch.vpit) 4110 goto out; 4111 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 4112 break; 4113 } 4114 case KVM_REINJECT_CONTROL: { 4115 struct kvm_reinject_control control; 4116 r = -EFAULT; 4117 if (copy_from_user(&control, argp, sizeof(control))) 4118 goto out; 4119 r = kvm_vm_ioctl_reinject(kvm, &control); 4120 break; 4121 } 4122 case KVM_SET_BOOT_CPU_ID: 4123 r = 0; 4124 mutex_lock(&kvm->lock); 4125 if (kvm->created_vcpus) 4126 r = -EBUSY; 4127 else 4128 kvm->arch.bsp_vcpu_id = arg; 4129 mutex_unlock(&kvm->lock); 4130 break; 4131 case KVM_XEN_HVM_CONFIG: { 4132 r = -EFAULT; 4133 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 4134 sizeof(struct kvm_xen_hvm_config))) 4135 goto out; 4136 r = -EINVAL; 4137 if (kvm->arch.xen_hvm_config.flags) 4138 goto out; 4139 r = 0; 4140 break; 4141 } 4142 case KVM_SET_CLOCK: { 4143 struct kvm_clock_data user_ns; 4144 u64 now_ns; 4145 4146 r = -EFAULT; 4147 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4148 goto out; 4149 4150 r = -EINVAL; 4151 if (user_ns.flags) 4152 goto out; 4153 4154 r = 0; 4155 local_irq_disable(); 4156 now_ns = __get_kvmclock_ns(kvm); 4157 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 4158 local_irq_enable(); 4159 kvm_gen_update_masterclock(kvm); 4160 break; 4161 } 4162 case KVM_GET_CLOCK: { 4163 struct kvm_clock_data user_ns; 4164 u64 now_ns; 4165 4166 local_irq_disable(); 4167 now_ns = __get_kvmclock_ns(kvm); 4168 user_ns.clock = now_ns; 4169 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 4170 local_irq_enable(); 4171 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4172 4173 r = -EFAULT; 4174 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4175 goto out; 4176 r = 0; 4177 break; 4178 } 4179 case KVM_ENABLE_CAP: { 4180 struct kvm_enable_cap cap; 4181 4182 r = -EFAULT; 4183 if (copy_from_user(&cap, argp, sizeof(cap))) 4184 goto out; 4185 r = kvm_vm_ioctl_enable_cap(kvm, &cap); 4186 break; 4187 } 4188 default: 4189 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); 4190 } 4191 out: 4192 return r; 4193 } 4194 4195 static void kvm_init_msr_list(void) 4196 { 4197 u32 dummy[2]; 4198 unsigned i, j; 4199 4200 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4201 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4202 continue; 4203 4204 /* 4205 * Even MSRs that are valid in the host may not be exposed 4206 * to the guests in some cases. 4207 */ 4208 switch (msrs_to_save[i]) { 4209 case MSR_IA32_BNDCFGS: 4210 if (!kvm_x86_ops->mpx_supported()) 4211 continue; 4212 break; 4213 case MSR_TSC_AUX: 4214 if (!kvm_x86_ops->rdtscp_supported()) 4215 continue; 4216 break; 4217 default: 4218 break; 4219 } 4220 4221 if (j < i) 4222 msrs_to_save[j] = msrs_to_save[i]; 4223 j++; 4224 } 4225 num_msrs_to_save = j; 4226 4227 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4228 switch (emulated_msrs[i]) { 4229 case MSR_IA32_SMBASE: 4230 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) 4231 continue; 4232 break; 4233 default: 4234 break; 4235 } 4236 4237 if (j < i) 4238 emulated_msrs[j] = emulated_msrs[i]; 4239 j++; 4240 } 4241 num_emulated_msrs = j; 4242 } 4243 4244 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4245 const void *v) 4246 { 4247 int handled = 0; 4248 int n; 4249 4250 do { 4251 n = min(len, 8); 4252 if (!(lapic_in_kernel(vcpu) && 4253 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4254 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4255 break; 4256 handled += n; 4257 addr += n; 4258 len -= n; 4259 v += n; 4260 } while (len); 4261 4262 return handled; 4263 } 4264 4265 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4266 { 4267 int handled = 0; 4268 int n; 4269 4270 do { 4271 n = min(len, 8); 4272 if (!(lapic_in_kernel(vcpu) && 4273 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4274 addr, n, v)) 4275 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4276 break; 4277 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 4278 handled += n; 4279 addr += n; 4280 len -= n; 4281 v += n; 4282 } while (len); 4283 4284 return handled; 4285 } 4286 4287 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4288 struct kvm_segment *var, int seg) 4289 { 4290 kvm_x86_ops->set_segment(vcpu, var, seg); 4291 } 4292 4293 void kvm_get_segment(struct kvm_vcpu *vcpu, 4294 struct kvm_segment *var, int seg) 4295 { 4296 kvm_x86_ops->get_segment(vcpu, var, seg); 4297 } 4298 4299 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4300 struct x86_exception *exception) 4301 { 4302 gpa_t t_gpa; 4303 4304 BUG_ON(!mmu_is_nested(vcpu)); 4305 4306 /* NPT walks are always user-walks */ 4307 access |= PFERR_USER_MASK; 4308 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4309 4310 return t_gpa; 4311 } 4312 4313 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4314 struct x86_exception *exception) 4315 { 4316 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4317 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4318 } 4319 4320 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4321 struct x86_exception *exception) 4322 { 4323 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4324 access |= PFERR_FETCH_MASK; 4325 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4326 } 4327 4328 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4329 struct x86_exception *exception) 4330 { 4331 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4332 access |= PFERR_WRITE_MASK; 4333 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4334 } 4335 4336 /* uses this to access any guest's mapped memory without checking CPL */ 4337 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4338 struct x86_exception *exception) 4339 { 4340 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4341 } 4342 4343 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4344 struct kvm_vcpu *vcpu, u32 access, 4345 struct x86_exception *exception) 4346 { 4347 void *data = val; 4348 int r = X86EMUL_CONTINUE; 4349 4350 while (bytes) { 4351 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4352 exception); 4353 unsigned offset = addr & (PAGE_SIZE-1); 4354 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4355 int ret; 4356 4357 if (gpa == UNMAPPED_GVA) 4358 return X86EMUL_PROPAGATE_FAULT; 4359 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 4360 offset, toread); 4361 if (ret < 0) { 4362 r = X86EMUL_IO_NEEDED; 4363 goto out; 4364 } 4365 4366 bytes -= toread; 4367 data += toread; 4368 addr += toread; 4369 } 4370 out: 4371 return r; 4372 } 4373 4374 /* used for instruction fetching */ 4375 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4376 gva_t addr, void *val, unsigned int bytes, 4377 struct x86_exception *exception) 4378 { 4379 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4380 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4381 unsigned offset; 4382 int ret; 4383 4384 /* Inline kvm_read_guest_virt_helper for speed. */ 4385 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4386 exception); 4387 if (unlikely(gpa == UNMAPPED_GVA)) 4388 return X86EMUL_PROPAGATE_FAULT; 4389 4390 offset = addr & (PAGE_SIZE-1); 4391 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4392 bytes = (unsigned)PAGE_SIZE - offset; 4393 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 4394 offset, bytes); 4395 if (unlikely(ret < 0)) 4396 return X86EMUL_IO_NEEDED; 4397 4398 return X86EMUL_CONTINUE; 4399 } 4400 4401 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4402 gva_t addr, void *val, unsigned int bytes, 4403 struct x86_exception *exception) 4404 { 4405 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4406 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4407 4408 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4409 exception); 4410 } 4411 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4412 4413 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4414 gva_t addr, void *val, unsigned int bytes, 4415 struct x86_exception *exception) 4416 { 4417 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4418 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4419 } 4420 4421 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 4422 unsigned long addr, void *val, unsigned int bytes) 4423 { 4424 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4425 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 4426 4427 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 4428 } 4429 4430 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4431 gva_t addr, void *val, 4432 unsigned int bytes, 4433 struct x86_exception *exception) 4434 { 4435 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4436 void *data = val; 4437 int r = X86EMUL_CONTINUE; 4438 4439 while (bytes) { 4440 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4441 PFERR_WRITE_MASK, 4442 exception); 4443 unsigned offset = addr & (PAGE_SIZE-1); 4444 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4445 int ret; 4446 4447 if (gpa == UNMAPPED_GVA) 4448 return X86EMUL_PROPAGATE_FAULT; 4449 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 4450 if (ret < 0) { 4451 r = X86EMUL_IO_NEEDED; 4452 goto out; 4453 } 4454 4455 bytes -= towrite; 4456 data += towrite; 4457 addr += towrite; 4458 } 4459 out: 4460 return r; 4461 } 4462 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4463 4464 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4465 gpa_t *gpa, struct x86_exception *exception, 4466 bool write) 4467 { 4468 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4469 | (write ? PFERR_WRITE_MASK : 0); 4470 4471 /* 4472 * currently PKRU is only applied to ept enabled guest so 4473 * there is no pkey in EPT page table for L1 guest or EPT 4474 * shadow page table for L2 guest. 4475 */ 4476 if (vcpu_match_mmio_gva(vcpu, gva) 4477 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4478 vcpu->arch.access, 0, access)) { 4479 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4480 (gva & (PAGE_SIZE - 1)); 4481 trace_vcpu_match_mmio(gva, *gpa, write, false); 4482 return 1; 4483 } 4484 4485 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4486 4487 if (*gpa == UNMAPPED_GVA) 4488 return -1; 4489 4490 /* For APIC access vmexit */ 4491 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4492 return 1; 4493 4494 if (vcpu_match_mmio_gpa(vcpu, *gpa)) { 4495 trace_vcpu_match_mmio(gva, *gpa, write, true); 4496 return 1; 4497 } 4498 4499 return 0; 4500 } 4501 4502 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4503 const void *val, int bytes) 4504 { 4505 int ret; 4506 4507 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 4508 if (ret < 0) 4509 return 0; 4510 kvm_page_track_write(vcpu, gpa, val, bytes); 4511 return 1; 4512 } 4513 4514 struct read_write_emulator_ops { 4515 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4516 int bytes); 4517 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4518 void *val, int bytes); 4519 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4520 int bytes, void *val); 4521 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4522 void *val, int bytes); 4523 bool write; 4524 }; 4525 4526 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4527 { 4528 if (vcpu->mmio_read_completed) { 4529 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4530 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4531 vcpu->mmio_read_completed = 0; 4532 return 1; 4533 } 4534 4535 return 0; 4536 } 4537 4538 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4539 void *val, int bytes) 4540 { 4541 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 4542 } 4543 4544 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4545 void *val, int bytes) 4546 { 4547 return emulator_write_phys(vcpu, gpa, val, bytes); 4548 } 4549 4550 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4551 { 4552 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4553 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4554 } 4555 4556 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4557 void *val, int bytes) 4558 { 4559 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4560 return X86EMUL_IO_NEEDED; 4561 } 4562 4563 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4564 void *val, int bytes) 4565 { 4566 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4567 4568 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4569 return X86EMUL_CONTINUE; 4570 } 4571 4572 static const struct read_write_emulator_ops read_emultor = { 4573 .read_write_prepare = read_prepare, 4574 .read_write_emulate = read_emulate, 4575 .read_write_mmio = vcpu_mmio_read, 4576 .read_write_exit_mmio = read_exit_mmio, 4577 }; 4578 4579 static const struct read_write_emulator_ops write_emultor = { 4580 .read_write_emulate = write_emulate, 4581 .read_write_mmio = write_mmio, 4582 .read_write_exit_mmio = write_exit_mmio, 4583 .write = true, 4584 }; 4585 4586 static int emulator_read_write_onepage(unsigned long addr, void *val, 4587 unsigned int bytes, 4588 struct x86_exception *exception, 4589 struct kvm_vcpu *vcpu, 4590 const struct read_write_emulator_ops *ops) 4591 { 4592 gpa_t gpa; 4593 int handled, ret; 4594 bool write = ops->write; 4595 struct kvm_mmio_fragment *frag; 4596 4597 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4598 4599 if (ret < 0) 4600 return X86EMUL_PROPAGATE_FAULT; 4601 4602 /* For APIC access vmexit */ 4603 if (ret) 4604 goto mmio; 4605 4606 if (ops->read_write_emulate(vcpu, gpa, val, bytes)) 4607 return X86EMUL_CONTINUE; 4608 4609 mmio: 4610 /* 4611 * Is this MMIO handled locally? 4612 */ 4613 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4614 if (handled == bytes) 4615 return X86EMUL_CONTINUE; 4616 4617 gpa += handled; 4618 bytes -= handled; 4619 val += handled; 4620 4621 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4622 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4623 frag->gpa = gpa; 4624 frag->data = val; 4625 frag->len = bytes; 4626 return X86EMUL_CONTINUE; 4627 } 4628 4629 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 4630 unsigned long addr, 4631 void *val, unsigned int bytes, 4632 struct x86_exception *exception, 4633 const struct read_write_emulator_ops *ops) 4634 { 4635 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4636 gpa_t gpa; 4637 int rc; 4638 4639 if (ops->read_write_prepare && 4640 ops->read_write_prepare(vcpu, val, bytes)) 4641 return X86EMUL_CONTINUE; 4642 4643 vcpu->mmio_nr_fragments = 0; 4644 4645 /* Crossing a page boundary? */ 4646 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4647 int now; 4648 4649 now = -addr & ~PAGE_MASK; 4650 rc = emulator_read_write_onepage(addr, val, now, exception, 4651 vcpu, ops); 4652 4653 if (rc != X86EMUL_CONTINUE) 4654 return rc; 4655 addr += now; 4656 if (ctxt->mode != X86EMUL_MODE_PROT64) 4657 addr = (u32)addr; 4658 val += now; 4659 bytes -= now; 4660 } 4661 4662 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4663 vcpu, ops); 4664 if (rc != X86EMUL_CONTINUE) 4665 return rc; 4666 4667 if (!vcpu->mmio_nr_fragments) 4668 return rc; 4669 4670 gpa = vcpu->mmio_fragments[0].gpa; 4671 4672 vcpu->mmio_needed = 1; 4673 vcpu->mmio_cur_fragment = 0; 4674 4675 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4676 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4677 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4678 vcpu->run->mmio.phys_addr = gpa; 4679 4680 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4681 } 4682 4683 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4684 unsigned long addr, 4685 void *val, 4686 unsigned int bytes, 4687 struct x86_exception *exception) 4688 { 4689 return emulator_read_write(ctxt, addr, val, bytes, 4690 exception, &read_emultor); 4691 } 4692 4693 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4694 unsigned long addr, 4695 const void *val, 4696 unsigned int bytes, 4697 struct x86_exception *exception) 4698 { 4699 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4700 exception, &write_emultor); 4701 } 4702 4703 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4704 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4705 4706 #ifdef CONFIG_X86_64 4707 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4708 #else 4709 # define CMPXCHG64(ptr, old, new) \ 4710 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4711 #endif 4712 4713 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4714 unsigned long addr, 4715 const void *old, 4716 const void *new, 4717 unsigned int bytes, 4718 struct x86_exception *exception) 4719 { 4720 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4721 gpa_t gpa; 4722 struct page *page; 4723 char *kaddr; 4724 bool exchanged; 4725 4726 /* guests cmpxchg8b have to be emulated atomically */ 4727 if (bytes > 8 || (bytes & (bytes - 1))) 4728 goto emul_write; 4729 4730 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4731 4732 if (gpa == UNMAPPED_GVA || 4733 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4734 goto emul_write; 4735 4736 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4737 goto emul_write; 4738 4739 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 4740 if (is_error_page(page)) 4741 goto emul_write; 4742 4743 kaddr = kmap_atomic(page); 4744 kaddr += offset_in_page(gpa); 4745 switch (bytes) { 4746 case 1: 4747 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4748 break; 4749 case 2: 4750 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4751 break; 4752 case 4: 4753 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4754 break; 4755 case 8: 4756 exchanged = CMPXCHG64(kaddr, old, new); 4757 break; 4758 default: 4759 BUG(); 4760 } 4761 kunmap_atomic(kaddr); 4762 kvm_release_page_dirty(page); 4763 4764 if (!exchanged) 4765 return X86EMUL_CMPXCHG_FAILED; 4766 4767 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 4768 kvm_page_track_write(vcpu, gpa, new, bytes); 4769 4770 return X86EMUL_CONTINUE; 4771 4772 emul_write: 4773 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4774 4775 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4776 } 4777 4778 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4779 { 4780 /* TODO: String I/O for in kernel device */ 4781 int r; 4782 4783 if (vcpu->arch.pio.in) 4784 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 4785 vcpu->arch.pio.size, pd); 4786 else 4787 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 4788 vcpu->arch.pio.port, vcpu->arch.pio.size, 4789 pd); 4790 return r; 4791 } 4792 4793 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4794 unsigned short port, void *val, 4795 unsigned int count, bool in) 4796 { 4797 vcpu->arch.pio.port = port; 4798 vcpu->arch.pio.in = in; 4799 vcpu->arch.pio.count = count; 4800 vcpu->arch.pio.size = size; 4801 4802 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4803 vcpu->arch.pio.count = 0; 4804 return 1; 4805 } 4806 4807 vcpu->run->exit_reason = KVM_EXIT_IO; 4808 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4809 vcpu->run->io.size = size; 4810 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4811 vcpu->run->io.count = count; 4812 vcpu->run->io.port = port; 4813 4814 return 0; 4815 } 4816 4817 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4818 int size, unsigned short port, void *val, 4819 unsigned int count) 4820 { 4821 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4822 int ret; 4823 4824 if (vcpu->arch.pio.count) 4825 goto data_avail; 4826 4827 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4828 if (ret) { 4829 data_avail: 4830 memcpy(val, vcpu->arch.pio_data, size * count); 4831 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 4832 vcpu->arch.pio.count = 0; 4833 return 1; 4834 } 4835 4836 return 0; 4837 } 4838 4839 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4840 int size, unsigned short port, 4841 const void *val, unsigned int count) 4842 { 4843 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4844 4845 memcpy(vcpu->arch.pio_data, val, size * count); 4846 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 4847 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4848 } 4849 4850 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4851 { 4852 return kvm_x86_ops->get_segment_base(vcpu, seg); 4853 } 4854 4855 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4856 { 4857 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4858 } 4859 4860 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 4861 { 4862 if (!need_emulate_wbinvd(vcpu)) 4863 return X86EMUL_CONTINUE; 4864 4865 if (kvm_x86_ops->has_wbinvd_exit()) { 4866 int cpu = get_cpu(); 4867 4868 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4869 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 4870 wbinvd_ipi, NULL, 1); 4871 put_cpu(); 4872 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 4873 } else 4874 wbinvd(); 4875 return X86EMUL_CONTINUE; 4876 } 4877 4878 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 4879 { 4880 kvm_emulate_wbinvd_noskip(vcpu); 4881 return kvm_skip_emulated_instruction(vcpu); 4882 } 4883 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 4884 4885 4886 4887 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 4888 { 4889 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 4890 } 4891 4892 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 4893 unsigned long *dest) 4894 { 4895 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 4896 } 4897 4898 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 4899 unsigned long value) 4900 { 4901 4902 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 4903 } 4904 4905 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 4906 { 4907 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 4908 } 4909 4910 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 4911 { 4912 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4913 unsigned long value; 4914 4915 switch (cr) { 4916 case 0: 4917 value = kvm_read_cr0(vcpu); 4918 break; 4919 case 2: 4920 value = vcpu->arch.cr2; 4921 break; 4922 case 3: 4923 value = kvm_read_cr3(vcpu); 4924 break; 4925 case 4: 4926 value = kvm_read_cr4(vcpu); 4927 break; 4928 case 8: 4929 value = kvm_get_cr8(vcpu); 4930 break; 4931 default: 4932 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4933 return 0; 4934 } 4935 4936 return value; 4937 } 4938 4939 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 4940 { 4941 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4942 int res = 0; 4943 4944 switch (cr) { 4945 case 0: 4946 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 4947 break; 4948 case 2: 4949 vcpu->arch.cr2 = val; 4950 break; 4951 case 3: 4952 res = kvm_set_cr3(vcpu, val); 4953 break; 4954 case 4: 4955 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 4956 break; 4957 case 8: 4958 res = kvm_set_cr8(vcpu, val); 4959 break; 4960 default: 4961 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4962 res = -1; 4963 } 4964 4965 return res; 4966 } 4967 4968 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 4969 { 4970 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 4971 } 4972 4973 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4974 { 4975 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 4976 } 4977 4978 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4979 { 4980 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 4981 } 4982 4983 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4984 { 4985 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 4986 } 4987 4988 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4989 { 4990 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 4991 } 4992 4993 static unsigned long emulator_get_cached_segment_base( 4994 struct x86_emulate_ctxt *ctxt, int seg) 4995 { 4996 return get_segment_base(emul_to_vcpu(ctxt), seg); 4997 } 4998 4999 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 5000 struct desc_struct *desc, u32 *base3, 5001 int seg) 5002 { 5003 struct kvm_segment var; 5004 5005 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 5006 *selector = var.selector; 5007 5008 if (var.unusable) { 5009 memset(desc, 0, sizeof(*desc)); 5010 return false; 5011 } 5012 5013 if (var.g) 5014 var.limit >>= 12; 5015 set_desc_limit(desc, var.limit); 5016 set_desc_base(desc, (unsigned long)var.base); 5017 #ifdef CONFIG_X86_64 5018 if (base3) 5019 *base3 = var.base >> 32; 5020 #endif 5021 desc->type = var.type; 5022 desc->s = var.s; 5023 desc->dpl = var.dpl; 5024 desc->p = var.present; 5025 desc->avl = var.avl; 5026 desc->l = var.l; 5027 desc->d = var.db; 5028 desc->g = var.g; 5029 5030 return true; 5031 } 5032 5033 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 5034 struct desc_struct *desc, u32 base3, 5035 int seg) 5036 { 5037 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5038 struct kvm_segment var; 5039 5040 var.selector = selector; 5041 var.base = get_desc_base(desc); 5042 #ifdef CONFIG_X86_64 5043 var.base |= ((u64)base3) << 32; 5044 #endif 5045 var.limit = get_desc_limit(desc); 5046 if (desc->g) 5047 var.limit = (var.limit << 12) | 0xfff; 5048 var.type = desc->type; 5049 var.dpl = desc->dpl; 5050 var.db = desc->d; 5051 var.s = desc->s; 5052 var.l = desc->l; 5053 var.g = desc->g; 5054 var.avl = desc->avl; 5055 var.present = desc->p; 5056 var.unusable = !var.present; 5057 var.padding = 0; 5058 5059 kvm_set_segment(vcpu, &var, seg); 5060 return; 5061 } 5062 5063 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 5064 u32 msr_index, u64 *pdata) 5065 { 5066 struct msr_data msr; 5067 int r; 5068 5069 msr.index = msr_index; 5070 msr.host_initiated = false; 5071 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 5072 if (r) 5073 return r; 5074 5075 *pdata = msr.data; 5076 return 0; 5077 } 5078 5079 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 5080 u32 msr_index, u64 data) 5081 { 5082 struct msr_data msr; 5083 5084 msr.data = data; 5085 msr.index = msr_index; 5086 msr.host_initiated = false; 5087 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 5088 } 5089 5090 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 5091 { 5092 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5093 5094 return vcpu->arch.smbase; 5095 } 5096 5097 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 5098 { 5099 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5100 5101 vcpu->arch.smbase = smbase; 5102 } 5103 5104 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 5105 u32 pmc) 5106 { 5107 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 5108 } 5109 5110 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 5111 u32 pmc, u64 *pdata) 5112 { 5113 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 5114 } 5115 5116 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 5117 { 5118 emul_to_vcpu(ctxt)->arch.halt_request = 1; 5119 } 5120 5121 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) 5122 { 5123 preempt_disable(); 5124 kvm_load_guest_fpu(emul_to_vcpu(ctxt)); 5125 } 5126 5127 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) 5128 { 5129 preempt_enable(); 5130 } 5131 5132 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 5133 struct x86_instruction_info *info, 5134 enum x86_intercept_stage stage) 5135 { 5136 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 5137 } 5138 5139 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 5140 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) 5141 { 5142 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); 5143 } 5144 5145 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 5146 { 5147 return kvm_register_read(emul_to_vcpu(ctxt), reg); 5148 } 5149 5150 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 5151 { 5152 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 5153 } 5154 5155 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5156 { 5157 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5158 } 5159 5160 static const struct x86_emulate_ops emulate_ops = { 5161 .read_gpr = emulator_read_gpr, 5162 .write_gpr = emulator_write_gpr, 5163 .read_std = kvm_read_guest_virt_system, 5164 .write_std = kvm_write_guest_virt_system, 5165 .read_phys = kvm_read_guest_phys_system, 5166 .fetch = kvm_fetch_guest_virt, 5167 .read_emulated = emulator_read_emulated, 5168 .write_emulated = emulator_write_emulated, 5169 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5170 .invlpg = emulator_invlpg, 5171 .pio_in_emulated = emulator_pio_in_emulated, 5172 .pio_out_emulated = emulator_pio_out_emulated, 5173 .get_segment = emulator_get_segment, 5174 .set_segment = emulator_set_segment, 5175 .get_cached_segment_base = emulator_get_cached_segment_base, 5176 .get_gdt = emulator_get_gdt, 5177 .get_idt = emulator_get_idt, 5178 .set_gdt = emulator_set_gdt, 5179 .set_idt = emulator_set_idt, 5180 .get_cr = emulator_get_cr, 5181 .set_cr = emulator_set_cr, 5182 .cpl = emulator_get_cpl, 5183 .get_dr = emulator_get_dr, 5184 .set_dr = emulator_set_dr, 5185 .get_smbase = emulator_get_smbase, 5186 .set_smbase = emulator_set_smbase, 5187 .set_msr = emulator_set_msr, 5188 .get_msr = emulator_get_msr, 5189 .check_pmc = emulator_check_pmc, 5190 .read_pmc = emulator_read_pmc, 5191 .halt = emulator_halt, 5192 .wbinvd = emulator_wbinvd, 5193 .fix_hypercall = emulator_fix_hypercall, 5194 .get_fpu = emulator_get_fpu, 5195 .put_fpu = emulator_put_fpu, 5196 .intercept = emulator_intercept, 5197 .get_cpuid = emulator_get_cpuid, 5198 .set_nmi_mask = emulator_set_nmi_mask, 5199 }; 5200 5201 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5202 { 5203 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5204 /* 5205 * an sti; sti; sequence only disable interrupts for the first 5206 * instruction. So, if the last instruction, be it emulated or 5207 * not, left the system with the INT_STI flag enabled, it 5208 * means that the last instruction is an sti. We should not 5209 * leave the flag on in this case. The same goes for mov ss 5210 */ 5211 if (int_shadow & mask) 5212 mask = 0; 5213 if (unlikely(int_shadow || mask)) { 5214 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5215 if (!mask) 5216 kvm_make_request(KVM_REQ_EVENT, vcpu); 5217 } 5218 } 5219 5220 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5221 { 5222 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5223 if (ctxt->exception.vector == PF_VECTOR) 5224 return kvm_propagate_fault(vcpu, &ctxt->exception); 5225 5226 if (ctxt->exception.error_code_valid) 5227 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5228 ctxt->exception.error_code); 5229 else 5230 kvm_queue_exception(vcpu, ctxt->exception.vector); 5231 return false; 5232 } 5233 5234 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5235 { 5236 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5237 int cs_db, cs_l; 5238 5239 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5240 5241 ctxt->eflags = kvm_get_rflags(vcpu); 5242 ctxt->eip = kvm_rip_read(vcpu); 5243 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5244 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5245 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5246 cs_db ? X86EMUL_MODE_PROT32 : 5247 X86EMUL_MODE_PROT16; 5248 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 5249 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 5250 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 5251 ctxt->emul_flags = vcpu->arch.hflags; 5252 5253 init_decode_cache(ctxt); 5254 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5255 } 5256 5257 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5258 { 5259 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5260 int ret; 5261 5262 init_emulate_ctxt(vcpu); 5263 5264 ctxt->op_bytes = 2; 5265 ctxt->ad_bytes = 2; 5266 ctxt->_eip = ctxt->eip + inc_eip; 5267 ret = emulate_int_real(ctxt, irq); 5268 5269 if (ret != X86EMUL_CONTINUE) 5270 return EMULATE_FAIL; 5271 5272 ctxt->eip = ctxt->_eip; 5273 kvm_rip_write(vcpu, ctxt->eip); 5274 kvm_set_rflags(vcpu, ctxt->eflags); 5275 5276 if (irq == NMI_VECTOR) 5277 vcpu->arch.nmi_pending = 0; 5278 else 5279 vcpu->arch.interrupt.pending = false; 5280 5281 return EMULATE_DONE; 5282 } 5283 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5284 5285 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 5286 { 5287 int r = EMULATE_DONE; 5288 5289 ++vcpu->stat.insn_emulation_fail; 5290 trace_kvm_emulate_insn_failed(vcpu); 5291 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5292 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5293 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5294 vcpu->run->internal.ndata = 0; 5295 r = EMULATE_FAIL; 5296 } 5297 kvm_queue_exception(vcpu, UD_VECTOR); 5298 5299 return r; 5300 } 5301 5302 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5303 bool write_fault_to_shadow_pgtable, 5304 int emulation_type) 5305 { 5306 gpa_t gpa = cr2; 5307 kvm_pfn_t pfn; 5308 5309 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5310 return false; 5311 5312 if (!vcpu->arch.mmu.direct_map) { 5313 /* 5314 * Write permission should be allowed since only 5315 * write access need to be emulated. 5316 */ 5317 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5318 5319 /* 5320 * If the mapping is invalid in guest, let cpu retry 5321 * it to generate fault. 5322 */ 5323 if (gpa == UNMAPPED_GVA) 5324 return true; 5325 } 5326 5327 /* 5328 * Do not retry the unhandleable instruction if it faults on the 5329 * readonly host memory, otherwise it will goto a infinite loop: 5330 * retry instruction -> write #PF -> emulation fail -> retry 5331 * instruction -> ... 5332 */ 5333 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5334 5335 /* 5336 * If the instruction failed on the error pfn, it can not be fixed, 5337 * report the error to userspace. 5338 */ 5339 if (is_error_noslot_pfn(pfn)) 5340 return false; 5341 5342 kvm_release_pfn_clean(pfn); 5343 5344 /* The instructions are well-emulated on direct mmu. */ 5345 if (vcpu->arch.mmu.direct_map) { 5346 unsigned int indirect_shadow_pages; 5347 5348 spin_lock(&vcpu->kvm->mmu_lock); 5349 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5350 spin_unlock(&vcpu->kvm->mmu_lock); 5351 5352 if (indirect_shadow_pages) 5353 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5354 5355 return true; 5356 } 5357 5358 /* 5359 * if emulation was due to access to shadowed page table 5360 * and it failed try to unshadow page and re-enter the 5361 * guest to let CPU execute the instruction. 5362 */ 5363 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5364 5365 /* 5366 * If the access faults on its page table, it can not 5367 * be fixed by unprotecting shadow page and it should 5368 * be reported to userspace. 5369 */ 5370 return !write_fault_to_shadow_pgtable; 5371 } 5372 5373 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5374 unsigned long cr2, int emulation_type) 5375 { 5376 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5377 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5378 5379 last_retry_eip = vcpu->arch.last_retry_eip; 5380 last_retry_addr = vcpu->arch.last_retry_addr; 5381 5382 /* 5383 * If the emulation is caused by #PF and it is non-page_table 5384 * writing instruction, it means the VM-EXIT is caused by shadow 5385 * page protected, we can zap the shadow page and retry this 5386 * instruction directly. 5387 * 5388 * Note: if the guest uses a non-page-table modifying instruction 5389 * on the PDE that points to the instruction, then we will unmap 5390 * the instruction and go to an infinite loop. So, we cache the 5391 * last retried eip and the last fault address, if we meet the eip 5392 * and the address again, we can break out of the potential infinite 5393 * loop. 5394 */ 5395 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5396 5397 if (!(emulation_type & EMULTYPE_RETRY)) 5398 return false; 5399 5400 if (x86_page_table_writing_insn(ctxt)) 5401 return false; 5402 5403 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5404 return false; 5405 5406 vcpu->arch.last_retry_eip = ctxt->eip; 5407 vcpu->arch.last_retry_addr = cr2; 5408 5409 if (!vcpu->arch.mmu.direct_map) 5410 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5411 5412 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5413 5414 return true; 5415 } 5416 5417 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5418 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5419 5420 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 5421 { 5422 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 5423 /* This is a good place to trace that we are exiting SMM. */ 5424 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 5425 5426 /* Process a latched INIT or SMI, if any. */ 5427 kvm_make_request(KVM_REQ_EVENT, vcpu); 5428 } 5429 5430 kvm_mmu_reset_context(vcpu); 5431 } 5432 5433 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) 5434 { 5435 unsigned changed = vcpu->arch.hflags ^ emul_flags; 5436 5437 vcpu->arch.hflags = emul_flags; 5438 5439 if (changed & HF_SMM_MASK) 5440 kvm_smm_changed(vcpu); 5441 } 5442 5443 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5444 unsigned long *db) 5445 { 5446 u32 dr6 = 0; 5447 int i; 5448 u32 enable, rwlen; 5449 5450 enable = dr7; 5451 rwlen = dr7 >> 16; 5452 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5453 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5454 dr6 |= (1 << i); 5455 return dr6; 5456 } 5457 5458 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) 5459 { 5460 struct kvm_run *kvm_run = vcpu->run; 5461 5462 /* 5463 * rflags is the old, "raw" value of the flags. The new value has 5464 * not been saved yet. 5465 * 5466 * This is correct even for TF set by the guest, because "the 5467 * processor will not generate this exception after the instruction 5468 * that sets the TF flag". 5469 */ 5470 if (unlikely(rflags & X86_EFLAGS_TF)) { 5471 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5472 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | 5473 DR6_RTM; 5474 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5475 kvm_run->debug.arch.exception = DB_VECTOR; 5476 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5477 *r = EMULATE_USER_EXIT; 5478 } else { 5479 /* 5480 * "Certain debug exceptions may clear bit 0-3. The 5481 * remaining contents of the DR6 register are never 5482 * cleared by the processor". 5483 */ 5484 vcpu->arch.dr6 &= ~15; 5485 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5486 kvm_queue_exception(vcpu, DB_VECTOR); 5487 } 5488 } 5489 } 5490 5491 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 5492 { 5493 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5494 int r = EMULATE_DONE; 5495 5496 kvm_x86_ops->skip_emulated_instruction(vcpu); 5497 kvm_vcpu_check_singlestep(vcpu, rflags, &r); 5498 return r == EMULATE_DONE; 5499 } 5500 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 5501 5502 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5503 { 5504 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5505 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5506 struct kvm_run *kvm_run = vcpu->run; 5507 unsigned long eip = kvm_get_linear_rip(vcpu); 5508 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5509 vcpu->arch.guest_debug_dr7, 5510 vcpu->arch.eff_db); 5511 5512 if (dr6 != 0) { 5513 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5514 kvm_run->debug.arch.pc = eip; 5515 kvm_run->debug.arch.exception = DB_VECTOR; 5516 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5517 *r = EMULATE_USER_EXIT; 5518 return true; 5519 } 5520 } 5521 5522 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5523 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5524 unsigned long eip = kvm_get_linear_rip(vcpu); 5525 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5526 vcpu->arch.dr7, 5527 vcpu->arch.db); 5528 5529 if (dr6 != 0) { 5530 vcpu->arch.dr6 &= ~15; 5531 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5532 kvm_queue_exception(vcpu, DB_VECTOR); 5533 *r = EMULATE_DONE; 5534 return true; 5535 } 5536 } 5537 5538 return false; 5539 } 5540 5541 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5542 unsigned long cr2, 5543 int emulation_type, 5544 void *insn, 5545 int insn_len) 5546 { 5547 int r; 5548 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5549 bool writeback = true; 5550 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5551 5552 /* 5553 * Clear write_fault_to_shadow_pgtable here to ensure it is 5554 * never reused. 5555 */ 5556 vcpu->arch.write_fault_to_shadow_pgtable = false; 5557 kvm_clear_exception_queue(vcpu); 5558 5559 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5560 init_emulate_ctxt(vcpu); 5561 5562 /* 5563 * We will reenter on the same instruction since 5564 * we do not set complete_userspace_io. This does not 5565 * handle watchpoints yet, those would be handled in 5566 * the emulate_ops. 5567 */ 5568 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5569 return r; 5570 5571 ctxt->interruptibility = 0; 5572 ctxt->have_exception = false; 5573 ctxt->exception.vector = -1; 5574 ctxt->perm_ok = false; 5575 5576 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5577 5578 r = x86_decode_insn(ctxt, insn, insn_len); 5579 5580 trace_kvm_emulate_insn_start(vcpu); 5581 ++vcpu->stat.insn_emulation; 5582 if (r != EMULATION_OK) { 5583 if (emulation_type & EMULTYPE_TRAP_UD) 5584 return EMULATE_FAIL; 5585 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5586 emulation_type)) 5587 return EMULATE_DONE; 5588 if (emulation_type & EMULTYPE_SKIP) 5589 return EMULATE_FAIL; 5590 return handle_emulation_failure(vcpu); 5591 } 5592 } 5593 5594 if (emulation_type & EMULTYPE_SKIP) { 5595 kvm_rip_write(vcpu, ctxt->_eip); 5596 if (ctxt->eflags & X86_EFLAGS_RF) 5597 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5598 return EMULATE_DONE; 5599 } 5600 5601 if (retry_instruction(ctxt, cr2, emulation_type)) 5602 return EMULATE_DONE; 5603 5604 /* this is needed for vmware backdoor interface to work since it 5605 changes registers values during IO operation */ 5606 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5607 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5608 emulator_invalidate_register_cache(ctxt); 5609 } 5610 5611 restart: 5612 r = x86_emulate_insn(ctxt); 5613 5614 if (r == EMULATION_INTERCEPTED) 5615 return EMULATE_DONE; 5616 5617 if (r == EMULATION_FAILED) { 5618 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5619 emulation_type)) 5620 return EMULATE_DONE; 5621 5622 return handle_emulation_failure(vcpu); 5623 } 5624 5625 if (ctxt->have_exception) { 5626 r = EMULATE_DONE; 5627 if (inject_emulated_exception(vcpu)) 5628 return r; 5629 } else if (vcpu->arch.pio.count) { 5630 if (!vcpu->arch.pio.in) { 5631 /* FIXME: return into emulator if single-stepping. */ 5632 vcpu->arch.pio.count = 0; 5633 } else { 5634 writeback = false; 5635 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5636 } 5637 r = EMULATE_USER_EXIT; 5638 } else if (vcpu->mmio_needed) { 5639 if (!vcpu->mmio_is_write) 5640 writeback = false; 5641 r = EMULATE_USER_EXIT; 5642 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5643 } else if (r == EMULATION_RESTART) 5644 goto restart; 5645 else 5646 r = EMULATE_DONE; 5647 5648 if (writeback) { 5649 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5650 toggle_interruptibility(vcpu, ctxt->interruptibility); 5651 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5652 if (vcpu->arch.hflags != ctxt->emul_flags) 5653 kvm_set_hflags(vcpu, ctxt->emul_flags); 5654 kvm_rip_write(vcpu, ctxt->eip); 5655 if (r == EMULATE_DONE) 5656 kvm_vcpu_check_singlestep(vcpu, rflags, &r); 5657 if (!ctxt->have_exception || 5658 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 5659 __kvm_set_rflags(vcpu, ctxt->eflags); 5660 5661 /* 5662 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5663 * do nothing, and it will be requested again as soon as 5664 * the shadow expires. But we still need to check here, 5665 * because POPF has no interrupt shadow. 5666 */ 5667 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5668 kvm_make_request(KVM_REQ_EVENT, vcpu); 5669 } else 5670 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5671 5672 return r; 5673 } 5674 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5675 5676 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5677 { 5678 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5679 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5680 size, port, &val, 1); 5681 /* do not return to emulator after return from userspace */ 5682 vcpu->arch.pio.count = 0; 5683 return ret; 5684 } 5685 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5686 5687 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 5688 { 5689 unsigned long val; 5690 5691 /* We should only ever be called with arch.pio.count equal to 1 */ 5692 BUG_ON(vcpu->arch.pio.count != 1); 5693 5694 /* For size less than 4 we merge, else we zero extend */ 5695 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) 5696 : 0; 5697 5698 /* 5699 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform 5700 * the copy and tracing 5701 */ 5702 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, 5703 vcpu->arch.pio.port, &val, 1); 5704 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 5705 5706 return 1; 5707 } 5708 5709 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port) 5710 { 5711 unsigned long val; 5712 int ret; 5713 5714 /* For size less than 4 we merge, else we zero extend */ 5715 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0; 5716 5717 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, 5718 &val, 1); 5719 if (ret) { 5720 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 5721 return ret; 5722 } 5723 5724 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 5725 5726 return 0; 5727 } 5728 EXPORT_SYMBOL_GPL(kvm_fast_pio_in); 5729 5730 static int kvmclock_cpu_down_prep(unsigned int cpu) 5731 { 5732 __this_cpu_write(cpu_tsc_khz, 0); 5733 return 0; 5734 } 5735 5736 static void tsc_khz_changed(void *data) 5737 { 5738 struct cpufreq_freqs *freq = data; 5739 unsigned long khz = 0; 5740 5741 if (data) 5742 khz = freq->new; 5743 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5744 khz = cpufreq_quick_get(raw_smp_processor_id()); 5745 if (!khz) 5746 khz = tsc_khz; 5747 __this_cpu_write(cpu_tsc_khz, khz); 5748 } 5749 5750 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5751 void *data) 5752 { 5753 struct cpufreq_freqs *freq = data; 5754 struct kvm *kvm; 5755 struct kvm_vcpu *vcpu; 5756 int i, send_ipi = 0; 5757 5758 /* 5759 * We allow guests to temporarily run on slowing clocks, 5760 * provided we notify them after, or to run on accelerating 5761 * clocks, provided we notify them before. Thus time never 5762 * goes backwards. 5763 * 5764 * However, we have a problem. We can't atomically update 5765 * the frequency of a given CPU from this function; it is 5766 * merely a notifier, which can be called from any CPU. 5767 * Changing the TSC frequency at arbitrary points in time 5768 * requires a recomputation of local variables related to 5769 * the TSC for each VCPU. We must flag these local variables 5770 * to be updated and be sure the update takes place with the 5771 * new frequency before any guests proceed. 5772 * 5773 * Unfortunately, the combination of hotplug CPU and frequency 5774 * change creates an intractable locking scenario; the order 5775 * of when these callouts happen is undefined with respect to 5776 * CPU hotplug, and they can race with each other. As such, 5777 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5778 * undefined; you can actually have a CPU frequency change take 5779 * place in between the computation of X and the setting of the 5780 * variable. To protect against this problem, all updates of 5781 * the per_cpu tsc_khz variable are done in an interrupt 5782 * protected IPI, and all callers wishing to update the value 5783 * must wait for a synchronous IPI to complete (which is trivial 5784 * if the caller is on the CPU already). This establishes the 5785 * necessary total order on variable updates. 5786 * 5787 * Note that because a guest time update may take place 5788 * anytime after the setting of the VCPU's request bit, the 5789 * correct TSC value must be set before the request. However, 5790 * to ensure the update actually makes it to any guest which 5791 * starts running in hardware virtualization between the set 5792 * and the acquisition of the spinlock, we must also ping the 5793 * CPU after setting the request bit. 5794 * 5795 */ 5796 5797 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5798 return 0; 5799 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5800 return 0; 5801 5802 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5803 5804 spin_lock(&kvm_lock); 5805 list_for_each_entry(kvm, &vm_list, vm_list) { 5806 kvm_for_each_vcpu(i, vcpu, kvm) { 5807 if (vcpu->cpu != freq->cpu) 5808 continue; 5809 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5810 if (vcpu->cpu != smp_processor_id()) 5811 send_ipi = 1; 5812 } 5813 } 5814 spin_unlock(&kvm_lock); 5815 5816 if (freq->old < freq->new && send_ipi) { 5817 /* 5818 * We upscale the frequency. Must make the guest 5819 * doesn't see old kvmclock values while running with 5820 * the new frequency, otherwise we risk the guest sees 5821 * time go backwards. 5822 * 5823 * In case we update the frequency for another cpu 5824 * (which might be in guest context) send an interrupt 5825 * to kick the cpu out of guest context. Next time 5826 * guest context is entered kvmclock will be updated, 5827 * so the guest will not see stale values. 5828 */ 5829 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5830 } 5831 return 0; 5832 } 5833 5834 static struct notifier_block kvmclock_cpufreq_notifier_block = { 5835 .notifier_call = kvmclock_cpufreq_notifier 5836 }; 5837 5838 static int kvmclock_cpu_online(unsigned int cpu) 5839 { 5840 tsc_khz_changed(NULL); 5841 return 0; 5842 } 5843 5844 static void kvm_timer_init(void) 5845 { 5846 max_tsc_khz = tsc_khz; 5847 5848 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5849 #ifdef CONFIG_CPU_FREQ 5850 struct cpufreq_policy policy; 5851 int cpu; 5852 5853 memset(&policy, 0, sizeof(policy)); 5854 cpu = get_cpu(); 5855 cpufreq_get_policy(&policy, cpu); 5856 if (policy.cpuinfo.max_freq) 5857 max_tsc_khz = policy.cpuinfo.max_freq; 5858 put_cpu(); 5859 #endif 5860 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 5861 CPUFREQ_TRANSITION_NOTIFIER); 5862 } 5863 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 5864 5865 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 5866 kvmclock_cpu_online, kvmclock_cpu_down_prep); 5867 } 5868 5869 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 5870 5871 int kvm_is_in_guest(void) 5872 { 5873 return __this_cpu_read(current_vcpu) != NULL; 5874 } 5875 5876 static int kvm_is_user_mode(void) 5877 { 5878 int user_mode = 3; 5879 5880 if (__this_cpu_read(current_vcpu)) 5881 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 5882 5883 return user_mode != 0; 5884 } 5885 5886 static unsigned long kvm_get_guest_ip(void) 5887 { 5888 unsigned long ip = 0; 5889 5890 if (__this_cpu_read(current_vcpu)) 5891 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 5892 5893 return ip; 5894 } 5895 5896 static struct perf_guest_info_callbacks kvm_guest_cbs = { 5897 .is_in_guest = kvm_is_in_guest, 5898 .is_user_mode = kvm_is_user_mode, 5899 .get_guest_ip = kvm_get_guest_ip, 5900 }; 5901 5902 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 5903 { 5904 __this_cpu_write(current_vcpu, vcpu); 5905 } 5906 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 5907 5908 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 5909 { 5910 __this_cpu_write(current_vcpu, NULL); 5911 } 5912 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 5913 5914 static void kvm_set_mmio_spte_mask(void) 5915 { 5916 u64 mask; 5917 int maxphyaddr = boot_cpu_data.x86_phys_bits; 5918 5919 /* 5920 * Set the reserved bits and the present bit of an paging-structure 5921 * entry to generate page fault with PFER.RSV = 1. 5922 */ 5923 /* Mask the reserved physical address bits. */ 5924 mask = rsvd_bits(maxphyaddr, 51); 5925 5926 /* Bit 62 is always reserved for 32bit host. */ 5927 mask |= 0x3ull << 62; 5928 5929 /* Set the present bit. */ 5930 mask |= 1ull; 5931 5932 #ifdef CONFIG_X86_64 5933 /* 5934 * If reserved bit is not supported, clear the present bit to disable 5935 * mmio page fault. 5936 */ 5937 if (maxphyaddr == 52) 5938 mask &= ~1ull; 5939 #endif 5940 5941 kvm_mmu_set_mmio_spte_mask(mask); 5942 } 5943 5944 #ifdef CONFIG_X86_64 5945 static void pvclock_gtod_update_fn(struct work_struct *work) 5946 { 5947 struct kvm *kvm; 5948 5949 struct kvm_vcpu *vcpu; 5950 int i; 5951 5952 spin_lock(&kvm_lock); 5953 list_for_each_entry(kvm, &vm_list, vm_list) 5954 kvm_for_each_vcpu(i, vcpu, kvm) 5955 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 5956 atomic_set(&kvm_guest_has_master_clock, 0); 5957 spin_unlock(&kvm_lock); 5958 } 5959 5960 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 5961 5962 /* 5963 * Notification about pvclock gtod data update. 5964 */ 5965 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 5966 void *priv) 5967 { 5968 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 5969 struct timekeeper *tk = priv; 5970 5971 update_pvclock_gtod(tk); 5972 5973 /* disable master clock if host does not trust, or does not 5974 * use, TSC clocksource 5975 */ 5976 if (gtod->clock.vclock_mode != VCLOCK_TSC && 5977 atomic_read(&kvm_guest_has_master_clock) != 0) 5978 queue_work(system_long_wq, &pvclock_gtod_work); 5979 5980 return 0; 5981 } 5982 5983 static struct notifier_block pvclock_gtod_notifier = { 5984 .notifier_call = pvclock_gtod_notify, 5985 }; 5986 #endif 5987 5988 int kvm_arch_init(void *opaque) 5989 { 5990 int r; 5991 struct kvm_x86_ops *ops = opaque; 5992 5993 if (kvm_x86_ops) { 5994 printk(KERN_ERR "kvm: already loaded the other module\n"); 5995 r = -EEXIST; 5996 goto out; 5997 } 5998 5999 if (!ops->cpu_has_kvm_support()) { 6000 printk(KERN_ERR "kvm: no hardware support\n"); 6001 r = -EOPNOTSUPP; 6002 goto out; 6003 } 6004 if (ops->disabled_by_bios()) { 6005 printk(KERN_ERR "kvm: disabled by bios\n"); 6006 r = -EOPNOTSUPP; 6007 goto out; 6008 } 6009 6010 r = -ENOMEM; 6011 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 6012 if (!shared_msrs) { 6013 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 6014 goto out; 6015 } 6016 6017 r = kvm_mmu_module_init(); 6018 if (r) 6019 goto out_free_percpu; 6020 6021 kvm_set_mmio_spte_mask(); 6022 6023 kvm_x86_ops = ops; 6024 6025 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 6026 PT_DIRTY_MASK, PT64_NX_MASK, 0, 6027 PT_PRESENT_MASK); 6028 kvm_timer_init(); 6029 6030 perf_register_guest_info_callbacks(&kvm_guest_cbs); 6031 6032 if (boot_cpu_has(X86_FEATURE_XSAVE)) 6033 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 6034 6035 kvm_lapic_init(); 6036 #ifdef CONFIG_X86_64 6037 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 6038 #endif 6039 6040 return 0; 6041 6042 out_free_percpu: 6043 free_percpu(shared_msrs); 6044 out: 6045 return r; 6046 } 6047 6048 void kvm_arch_exit(void) 6049 { 6050 kvm_lapic_exit(); 6051 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 6052 6053 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 6054 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 6055 CPUFREQ_TRANSITION_NOTIFIER); 6056 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 6057 #ifdef CONFIG_X86_64 6058 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 6059 #endif 6060 kvm_x86_ops = NULL; 6061 kvm_mmu_module_exit(); 6062 free_percpu(shared_msrs); 6063 } 6064 6065 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 6066 { 6067 ++vcpu->stat.halt_exits; 6068 if (lapic_in_kernel(vcpu)) { 6069 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 6070 return 1; 6071 } else { 6072 vcpu->run->exit_reason = KVM_EXIT_HLT; 6073 return 0; 6074 } 6075 } 6076 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 6077 6078 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 6079 { 6080 int ret = kvm_skip_emulated_instruction(vcpu); 6081 /* 6082 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 6083 * KVM_EXIT_DEBUG here. 6084 */ 6085 return kvm_vcpu_halt(vcpu) && ret; 6086 } 6087 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 6088 6089 /* 6090 * kvm_pv_kick_cpu_op: Kick a vcpu. 6091 * 6092 * @apicid - apicid of vcpu to be kicked. 6093 */ 6094 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 6095 { 6096 struct kvm_lapic_irq lapic_irq; 6097 6098 lapic_irq.shorthand = 0; 6099 lapic_irq.dest_mode = 0; 6100 lapic_irq.dest_id = apicid; 6101 lapic_irq.msi_redir_hint = false; 6102 6103 lapic_irq.delivery_mode = APIC_DM_REMRD; 6104 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 6105 } 6106 6107 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) 6108 { 6109 vcpu->arch.apicv_active = false; 6110 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); 6111 } 6112 6113 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 6114 { 6115 unsigned long nr, a0, a1, a2, a3, ret; 6116 int op_64_bit, r; 6117 6118 r = kvm_skip_emulated_instruction(vcpu); 6119 6120 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 6121 return kvm_hv_hypercall(vcpu); 6122 6123 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 6124 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 6125 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 6126 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 6127 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 6128 6129 trace_kvm_hypercall(nr, a0, a1, a2, a3); 6130 6131 op_64_bit = is_64_bit_mode(vcpu); 6132 if (!op_64_bit) { 6133 nr &= 0xFFFFFFFF; 6134 a0 &= 0xFFFFFFFF; 6135 a1 &= 0xFFFFFFFF; 6136 a2 &= 0xFFFFFFFF; 6137 a3 &= 0xFFFFFFFF; 6138 } 6139 6140 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 6141 ret = -KVM_EPERM; 6142 goto out; 6143 } 6144 6145 switch (nr) { 6146 case KVM_HC_VAPIC_POLL_IRQ: 6147 ret = 0; 6148 break; 6149 case KVM_HC_KICK_CPU: 6150 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 6151 ret = 0; 6152 break; 6153 default: 6154 ret = -KVM_ENOSYS; 6155 break; 6156 } 6157 out: 6158 if (!op_64_bit) 6159 ret = (u32)ret; 6160 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 6161 ++vcpu->stat.hypercalls; 6162 return r; 6163 } 6164 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 6165 6166 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 6167 { 6168 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6169 char instruction[3]; 6170 unsigned long rip = kvm_rip_read(vcpu); 6171 6172 kvm_x86_ops->patch_hypercall(vcpu, instruction); 6173 6174 return emulator_write_emulated(ctxt, rip, instruction, 3, 6175 &ctxt->exception); 6176 } 6177 6178 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 6179 { 6180 return vcpu->run->request_interrupt_window && 6181 likely(!pic_in_kernel(vcpu->kvm)); 6182 } 6183 6184 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 6185 { 6186 struct kvm_run *kvm_run = vcpu->run; 6187 6188 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 6189 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 6190 kvm_run->cr8 = kvm_get_cr8(vcpu); 6191 kvm_run->apic_base = kvm_get_apic_base(vcpu); 6192 kvm_run->ready_for_interrupt_injection = 6193 pic_in_kernel(vcpu->kvm) || 6194 kvm_vcpu_ready_for_interrupt_injection(vcpu); 6195 } 6196 6197 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 6198 { 6199 int max_irr, tpr; 6200 6201 if (!kvm_x86_ops->update_cr8_intercept) 6202 return; 6203 6204 if (!lapic_in_kernel(vcpu)) 6205 return; 6206 6207 if (vcpu->arch.apicv_active) 6208 return; 6209 6210 if (!vcpu->arch.apic->vapic_addr) 6211 max_irr = kvm_lapic_find_highest_irr(vcpu); 6212 else 6213 max_irr = -1; 6214 6215 if (max_irr != -1) 6216 max_irr >>= 4; 6217 6218 tpr = kvm_lapic_get_cr8(vcpu); 6219 6220 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 6221 } 6222 6223 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 6224 { 6225 int r; 6226 6227 /* try to reinject previous events if any */ 6228 if (vcpu->arch.exception.pending) { 6229 trace_kvm_inj_exception(vcpu->arch.exception.nr, 6230 vcpu->arch.exception.has_error_code, 6231 vcpu->arch.exception.error_code); 6232 6233 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 6234 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 6235 X86_EFLAGS_RF); 6236 6237 if (vcpu->arch.exception.nr == DB_VECTOR && 6238 (vcpu->arch.dr7 & DR7_GD)) { 6239 vcpu->arch.dr7 &= ~DR7_GD; 6240 kvm_update_dr7(vcpu); 6241 } 6242 6243 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, 6244 vcpu->arch.exception.has_error_code, 6245 vcpu->arch.exception.error_code, 6246 vcpu->arch.exception.reinject); 6247 return 0; 6248 } 6249 6250 if (vcpu->arch.nmi_injected) { 6251 kvm_x86_ops->set_nmi(vcpu); 6252 return 0; 6253 } 6254 6255 if (vcpu->arch.interrupt.pending) { 6256 kvm_x86_ops->set_irq(vcpu); 6257 return 0; 6258 } 6259 6260 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6261 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6262 if (r != 0) 6263 return r; 6264 } 6265 6266 /* try to inject new event if pending */ 6267 if (vcpu->arch.smi_pending && !is_smm(vcpu)) { 6268 vcpu->arch.smi_pending = false; 6269 enter_smm(vcpu); 6270 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { 6271 --vcpu->arch.nmi_pending; 6272 vcpu->arch.nmi_injected = true; 6273 kvm_x86_ops->set_nmi(vcpu); 6274 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6275 /* 6276 * Because interrupts can be injected asynchronously, we are 6277 * calling check_nested_events again here to avoid a race condition. 6278 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6279 * proposal and current concerns. Perhaps we should be setting 6280 * KVM_REQ_EVENT only on certain events and not unconditionally? 6281 */ 6282 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6283 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6284 if (r != 0) 6285 return r; 6286 } 6287 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6288 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6289 false); 6290 kvm_x86_ops->set_irq(vcpu); 6291 } 6292 } 6293 6294 return 0; 6295 } 6296 6297 static void process_nmi(struct kvm_vcpu *vcpu) 6298 { 6299 unsigned limit = 2; 6300 6301 /* 6302 * x86 is limited to one NMI running, and one NMI pending after it. 6303 * If an NMI is already in progress, limit further NMIs to just one. 6304 * Otherwise, allow two (and we'll inject the first one immediately). 6305 */ 6306 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6307 limit = 1; 6308 6309 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6310 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6311 kvm_make_request(KVM_REQ_EVENT, vcpu); 6312 } 6313 6314 #define put_smstate(type, buf, offset, val) \ 6315 *(type *)((buf) + (offset) - 0x7e00) = val 6316 6317 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 6318 { 6319 u32 flags = 0; 6320 flags |= seg->g << 23; 6321 flags |= seg->db << 22; 6322 flags |= seg->l << 21; 6323 flags |= seg->avl << 20; 6324 flags |= seg->present << 15; 6325 flags |= seg->dpl << 13; 6326 flags |= seg->s << 12; 6327 flags |= seg->type << 8; 6328 return flags; 6329 } 6330 6331 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 6332 { 6333 struct kvm_segment seg; 6334 int offset; 6335 6336 kvm_get_segment(vcpu, &seg, n); 6337 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 6338 6339 if (n < 3) 6340 offset = 0x7f84 + n * 12; 6341 else 6342 offset = 0x7f2c + (n - 3) * 12; 6343 6344 put_smstate(u32, buf, offset + 8, seg.base); 6345 put_smstate(u32, buf, offset + 4, seg.limit); 6346 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 6347 } 6348 6349 #ifdef CONFIG_X86_64 6350 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 6351 { 6352 struct kvm_segment seg; 6353 int offset; 6354 u16 flags; 6355 6356 kvm_get_segment(vcpu, &seg, n); 6357 offset = 0x7e00 + n * 16; 6358 6359 flags = enter_smm_get_segment_flags(&seg) >> 8; 6360 put_smstate(u16, buf, offset, seg.selector); 6361 put_smstate(u16, buf, offset + 2, flags); 6362 put_smstate(u32, buf, offset + 4, seg.limit); 6363 put_smstate(u64, buf, offset + 8, seg.base); 6364 } 6365 #endif 6366 6367 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 6368 { 6369 struct desc_ptr dt; 6370 struct kvm_segment seg; 6371 unsigned long val; 6372 int i; 6373 6374 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 6375 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 6376 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 6377 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 6378 6379 for (i = 0; i < 8; i++) 6380 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 6381 6382 kvm_get_dr(vcpu, 6, &val); 6383 put_smstate(u32, buf, 0x7fcc, (u32)val); 6384 kvm_get_dr(vcpu, 7, &val); 6385 put_smstate(u32, buf, 0x7fc8, (u32)val); 6386 6387 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6388 put_smstate(u32, buf, 0x7fc4, seg.selector); 6389 put_smstate(u32, buf, 0x7f64, seg.base); 6390 put_smstate(u32, buf, 0x7f60, seg.limit); 6391 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 6392 6393 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6394 put_smstate(u32, buf, 0x7fc0, seg.selector); 6395 put_smstate(u32, buf, 0x7f80, seg.base); 6396 put_smstate(u32, buf, 0x7f7c, seg.limit); 6397 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 6398 6399 kvm_x86_ops->get_gdt(vcpu, &dt); 6400 put_smstate(u32, buf, 0x7f74, dt.address); 6401 put_smstate(u32, buf, 0x7f70, dt.size); 6402 6403 kvm_x86_ops->get_idt(vcpu, &dt); 6404 put_smstate(u32, buf, 0x7f58, dt.address); 6405 put_smstate(u32, buf, 0x7f54, dt.size); 6406 6407 for (i = 0; i < 6; i++) 6408 enter_smm_save_seg_32(vcpu, buf, i); 6409 6410 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 6411 6412 /* revision id */ 6413 put_smstate(u32, buf, 0x7efc, 0x00020000); 6414 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 6415 } 6416 6417 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 6418 { 6419 #ifdef CONFIG_X86_64 6420 struct desc_ptr dt; 6421 struct kvm_segment seg; 6422 unsigned long val; 6423 int i; 6424 6425 for (i = 0; i < 16; i++) 6426 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 6427 6428 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 6429 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 6430 6431 kvm_get_dr(vcpu, 6, &val); 6432 put_smstate(u64, buf, 0x7f68, val); 6433 kvm_get_dr(vcpu, 7, &val); 6434 put_smstate(u64, buf, 0x7f60, val); 6435 6436 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 6437 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 6438 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 6439 6440 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 6441 6442 /* revision id */ 6443 put_smstate(u32, buf, 0x7efc, 0x00020064); 6444 6445 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 6446 6447 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6448 put_smstate(u16, buf, 0x7e90, seg.selector); 6449 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 6450 put_smstate(u32, buf, 0x7e94, seg.limit); 6451 put_smstate(u64, buf, 0x7e98, seg.base); 6452 6453 kvm_x86_ops->get_idt(vcpu, &dt); 6454 put_smstate(u32, buf, 0x7e84, dt.size); 6455 put_smstate(u64, buf, 0x7e88, dt.address); 6456 6457 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6458 put_smstate(u16, buf, 0x7e70, seg.selector); 6459 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 6460 put_smstate(u32, buf, 0x7e74, seg.limit); 6461 put_smstate(u64, buf, 0x7e78, seg.base); 6462 6463 kvm_x86_ops->get_gdt(vcpu, &dt); 6464 put_smstate(u32, buf, 0x7e64, dt.size); 6465 put_smstate(u64, buf, 0x7e68, dt.address); 6466 6467 for (i = 0; i < 6; i++) 6468 enter_smm_save_seg_64(vcpu, buf, i); 6469 #else 6470 WARN_ON_ONCE(1); 6471 #endif 6472 } 6473 6474 static void enter_smm(struct kvm_vcpu *vcpu) 6475 { 6476 struct kvm_segment cs, ds; 6477 struct desc_ptr dt; 6478 char buf[512]; 6479 u32 cr0; 6480 6481 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 6482 vcpu->arch.hflags |= HF_SMM_MASK; 6483 memset(buf, 0, 512); 6484 if (guest_cpuid_has_longmode(vcpu)) 6485 enter_smm_save_state_64(vcpu, buf); 6486 else 6487 enter_smm_save_state_32(vcpu, buf); 6488 6489 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 6490 6491 if (kvm_x86_ops->get_nmi_mask(vcpu)) 6492 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 6493 else 6494 kvm_x86_ops->set_nmi_mask(vcpu, true); 6495 6496 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 6497 kvm_rip_write(vcpu, 0x8000); 6498 6499 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 6500 kvm_x86_ops->set_cr0(vcpu, cr0); 6501 vcpu->arch.cr0 = cr0; 6502 6503 kvm_x86_ops->set_cr4(vcpu, 0); 6504 6505 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 6506 dt.address = dt.size = 0; 6507 kvm_x86_ops->set_idt(vcpu, &dt); 6508 6509 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 6510 6511 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 6512 cs.base = vcpu->arch.smbase; 6513 6514 ds.selector = 0; 6515 ds.base = 0; 6516 6517 cs.limit = ds.limit = 0xffffffff; 6518 cs.type = ds.type = 0x3; 6519 cs.dpl = ds.dpl = 0; 6520 cs.db = ds.db = 0; 6521 cs.s = ds.s = 1; 6522 cs.l = ds.l = 0; 6523 cs.g = ds.g = 1; 6524 cs.avl = ds.avl = 0; 6525 cs.present = ds.present = 1; 6526 cs.unusable = ds.unusable = 0; 6527 cs.padding = ds.padding = 0; 6528 6529 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 6530 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 6531 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 6532 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 6533 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 6534 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 6535 6536 if (guest_cpuid_has_longmode(vcpu)) 6537 kvm_x86_ops->set_efer(vcpu, 0); 6538 6539 kvm_update_cpuid(vcpu); 6540 kvm_mmu_reset_context(vcpu); 6541 } 6542 6543 static void process_smi(struct kvm_vcpu *vcpu) 6544 { 6545 vcpu->arch.smi_pending = true; 6546 kvm_make_request(KVM_REQ_EVENT, vcpu); 6547 } 6548 6549 void kvm_make_scan_ioapic_request(struct kvm *kvm) 6550 { 6551 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 6552 } 6553 6554 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 6555 { 6556 u64 eoi_exit_bitmap[4]; 6557 6558 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 6559 return; 6560 6561 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 6562 6563 if (irqchip_split(vcpu->kvm)) 6564 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 6565 else { 6566 if (vcpu->arch.apicv_active) 6567 kvm_x86_ops->sync_pir_to_irr(vcpu); 6568 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 6569 } 6570 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 6571 vcpu_to_synic(vcpu)->vec_bitmap, 256); 6572 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 6573 } 6574 6575 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) 6576 { 6577 ++vcpu->stat.tlb_flush; 6578 kvm_x86_ops->tlb_flush(vcpu); 6579 } 6580 6581 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 6582 { 6583 struct page *page = NULL; 6584 6585 if (!lapic_in_kernel(vcpu)) 6586 return; 6587 6588 if (!kvm_x86_ops->set_apic_access_page_addr) 6589 return; 6590 6591 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6592 if (is_error_page(page)) 6593 return; 6594 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 6595 6596 /* 6597 * Do not pin apic access page in memory, the MMU notifier 6598 * will call us again if it is migrated or swapped out. 6599 */ 6600 put_page(page); 6601 } 6602 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 6603 6604 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 6605 unsigned long address) 6606 { 6607 /* 6608 * The physical address of apic access page is stored in the VMCS. 6609 * Update it when it becomes invalid. 6610 */ 6611 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) 6612 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 6613 } 6614 6615 /* 6616 * Returns 1 to let vcpu_run() continue the guest execution loop without 6617 * exiting to the userspace. Otherwise, the value will be returned to the 6618 * userspace. 6619 */ 6620 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 6621 { 6622 int r; 6623 bool req_int_win = 6624 dm_request_for_irq_injection(vcpu) && 6625 kvm_cpu_accept_dm_intr(vcpu); 6626 6627 bool req_immediate_exit = false; 6628 6629 if (vcpu->requests) { 6630 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6631 kvm_mmu_unload(vcpu); 6632 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6633 __kvm_migrate_timers(vcpu); 6634 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6635 kvm_gen_update_masterclock(vcpu->kvm); 6636 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6637 kvm_gen_kvmclock_update(vcpu); 6638 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6639 r = kvm_guest_time_update(vcpu); 6640 if (unlikely(r)) 6641 goto out; 6642 } 6643 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6644 kvm_mmu_sync_roots(vcpu); 6645 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6646 kvm_vcpu_flush_tlb(vcpu); 6647 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6648 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6649 r = 0; 6650 goto out; 6651 } 6652 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6653 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6654 r = 0; 6655 goto out; 6656 } 6657 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { 6658 vcpu->fpu_active = 0; 6659 kvm_x86_ops->fpu_deactivate(vcpu); 6660 } 6661 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 6662 /* Page is swapped out. Do synthetic halt */ 6663 vcpu->arch.apf.halted = true; 6664 r = 1; 6665 goto out; 6666 } 6667 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 6668 record_steal_time(vcpu); 6669 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 6670 process_smi(vcpu); 6671 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 6672 process_nmi(vcpu); 6673 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 6674 kvm_pmu_handle_event(vcpu); 6675 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 6676 kvm_pmu_deliver_pmi(vcpu); 6677 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 6678 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 6679 if (test_bit(vcpu->arch.pending_ioapic_eoi, 6680 vcpu->arch.ioapic_handled_vectors)) { 6681 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 6682 vcpu->run->eoi.vector = 6683 vcpu->arch.pending_ioapic_eoi; 6684 r = 0; 6685 goto out; 6686 } 6687 } 6688 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 6689 vcpu_scan_ioapic(vcpu); 6690 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 6691 kvm_vcpu_reload_apic_access_page(vcpu); 6692 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 6693 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6694 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 6695 r = 0; 6696 goto out; 6697 } 6698 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 6699 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6700 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 6701 r = 0; 6702 goto out; 6703 } 6704 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 6705 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 6706 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 6707 r = 0; 6708 goto out; 6709 } 6710 6711 /* 6712 * KVM_REQ_HV_STIMER has to be processed after 6713 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 6714 * depend on the guest clock being up-to-date 6715 */ 6716 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 6717 kvm_hv_process_stimers(vcpu); 6718 } 6719 6720 /* 6721 * KVM_REQ_EVENT is not set when posted interrupts are set by 6722 * VT-d hardware, so we have to update RVI unconditionally. 6723 */ 6724 if (kvm_lapic_enabled(vcpu)) { 6725 /* 6726 * Update architecture specific hints for APIC 6727 * virtual interrupt delivery. 6728 */ 6729 if (vcpu->arch.apicv_active) 6730 kvm_x86_ops->hwapic_irr_update(vcpu, 6731 kvm_lapic_find_highest_irr(vcpu)); 6732 } 6733 6734 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 6735 kvm_apic_accept_events(vcpu); 6736 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 6737 r = 1; 6738 goto out; 6739 } 6740 6741 if (inject_pending_event(vcpu, req_int_win) != 0) 6742 req_immediate_exit = true; 6743 else { 6744 /* Enable NMI/IRQ window open exits if needed. 6745 * 6746 * SMIs have two cases: 1) they can be nested, and 6747 * then there is nothing to do here because RSM will 6748 * cause a vmexit anyway; 2) or the SMI can be pending 6749 * because inject_pending_event has completed the 6750 * injection of an IRQ or NMI from the previous vmexit, 6751 * and then we request an immediate exit to inject the SMI. 6752 */ 6753 if (vcpu->arch.smi_pending && !is_smm(vcpu)) 6754 req_immediate_exit = true; 6755 if (vcpu->arch.nmi_pending) 6756 kvm_x86_ops->enable_nmi_window(vcpu); 6757 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6758 kvm_x86_ops->enable_irq_window(vcpu); 6759 } 6760 6761 if (kvm_lapic_enabled(vcpu)) { 6762 update_cr8_intercept(vcpu); 6763 kvm_lapic_sync_to_vapic(vcpu); 6764 } 6765 } 6766 6767 r = kvm_mmu_reload(vcpu); 6768 if (unlikely(r)) { 6769 goto cancel_injection; 6770 } 6771 6772 preempt_disable(); 6773 6774 kvm_x86_ops->prepare_guest_switch(vcpu); 6775 if (vcpu->fpu_active) 6776 kvm_load_guest_fpu(vcpu); 6777 vcpu->mode = IN_GUEST_MODE; 6778 6779 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6780 6781 /* 6782 * We should set ->mode before check ->requests, 6783 * Please see the comment in kvm_make_all_cpus_request. 6784 * This also orders the write to mode from any reads 6785 * to the page tables done while the VCPU is running. 6786 * Please see the comment in kvm_flush_remote_tlbs. 6787 */ 6788 smp_mb__after_srcu_read_unlock(); 6789 6790 local_irq_disable(); 6791 6792 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests 6793 || need_resched() || signal_pending(current)) { 6794 vcpu->mode = OUTSIDE_GUEST_MODE; 6795 smp_wmb(); 6796 local_irq_enable(); 6797 preempt_enable(); 6798 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6799 r = 1; 6800 goto cancel_injection; 6801 } 6802 6803 kvm_load_guest_xcr0(vcpu); 6804 6805 if (req_immediate_exit) { 6806 kvm_make_request(KVM_REQ_EVENT, vcpu); 6807 smp_send_reschedule(vcpu->cpu); 6808 } 6809 6810 trace_kvm_entry(vcpu->vcpu_id); 6811 wait_lapic_expire(vcpu); 6812 guest_enter_irqoff(); 6813 6814 if (unlikely(vcpu->arch.switch_db_regs)) { 6815 set_debugreg(0, 7); 6816 set_debugreg(vcpu->arch.eff_db[0], 0); 6817 set_debugreg(vcpu->arch.eff_db[1], 1); 6818 set_debugreg(vcpu->arch.eff_db[2], 2); 6819 set_debugreg(vcpu->arch.eff_db[3], 3); 6820 set_debugreg(vcpu->arch.dr6, 6); 6821 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6822 } 6823 6824 kvm_x86_ops->run(vcpu); 6825 6826 /* 6827 * Do this here before restoring debug registers on the host. And 6828 * since we do this before handling the vmexit, a DR access vmexit 6829 * can (a) read the correct value of the debug registers, (b) set 6830 * KVM_DEBUGREG_WONT_EXIT again. 6831 */ 6832 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 6833 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 6834 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 6835 kvm_update_dr0123(vcpu); 6836 kvm_update_dr6(vcpu); 6837 kvm_update_dr7(vcpu); 6838 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6839 } 6840 6841 /* 6842 * If the guest has used debug registers, at least dr7 6843 * will be disabled while returning to the host. 6844 * If we don't have active breakpoints in the host, we don't 6845 * care about the messed up debug address registers. But if 6846 * we have some of them active, restore the old state. 6847 */ 6848 if (hw_breakpoint_active()) 6849 hw_breakpoint_restore(); 6850 6851 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 6852 6853 vcpu->mode = OUTSIDE_GUEST_MODE; 6854 smp_wmb(); 6855 6856 kvm_put_guest_xcr0(vcpu); 6857 6858 kvm_x86_ops->handle_external_intr(vcpu); 6859 6860 ++vcpu->stat.exits; 6861 6862 guest_exit_irqoff(); 6863 6864 local_irq_enable(); 6865 preempt_enable(); 6866 6867 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6868 6869 /* 6870 * Profile KVM exit RIPs: 6871 */ 6872 if (unlikely(prof_on == KVM_PROFILING)) { 6873 unsigned long rip = kvm_rip_read(vcpu); 6874 profile_hit(KVM_PROFILING, (void *)rip); 6875 } 6876 6877 if (unlikely(vcpu->arch.tsc_always_catchup)) 6878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6879 6880 if (vcpu->arch.apic_attention) 6881 kvm_lapic_sync_from_vapic(vcpu); 6882 6883 r = kvm_x86_ops->handle_exit(vcpu); 6884 return r; 6885 6886 cancel_injection: 6887 kvm_x86_ops->cancel_injection(vcpu); 6888 if (unlikely(vcpu->arch.apic_attention)) 6889 kvm_lapic_sync_from_vapic(vcpu); 6890 out: 6891 return r; 6892 } 6893 6894 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 6895 { 6896 if (!kvm_arch_vcpu_runnable(vcpu) && 6897 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 6898 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6899 kvm_vcpu_block(vcpu); 6900 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6901 6902 if (kvm_x86_ops->post_block) 6903 kvm_x86_ops->post_block(vcpu); 6904 6905 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 6906 return 1; 6907 } 6908 6909 kvm_apic_accept_events(vcpu); 6910 switch(vcpu->arch.mp_state) { 6911 case KVM_MP_STATE_HALTED: 6912 vcpu->arch.pv.pv_unhalted = false; 6913 vcpu->arch.mp_state = 6914 KVM_MP_STATE_RUNNABLE; 6915 case KVM_MP_STATE_RUNNABLE: 6916 vcpu->arch.apf.halted = false; 6917 break; 6918 case KVM_MP_STATE_INIT_RECEIVED: 6919 break; 6920 default: 6921 return -EINTR; 6922 break; 6923 } 6924 return 1; 6925 } 6926 6927 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 6928 { 6929 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 6930 !vcpu->arch.apf.halted); 6931 } 6932 6933 static int vcpu_run(struct kvm_vcpu *vcpu) 6934 { 6935 int r; 6936 struct kvm *kvm = vcpu->kvm; 6937 6938 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6939 6940 for (;;) { 6941 if (kvm_vcpu_running(vcpu)) { 6942 r = vcpu_enter_guest(vcpu); 6943 } else { 6944 r = vcpu_block(kvm, vcpu); 6945 } 6946 6947 if (r <= 0) 6948 break; 6949 6950 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); 6951 if (kvm_cpu_has_pending_timer(vcpu)) 6952 kvm_inject_pending_timer_irqs(vcpu); 6953 6954 if (dm_request_for_irq_injection(vcpu) && 6955 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 6956 r = 0; 6957 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 6958 ++vcpu->stat.request_irq_exits; 6959 break; 6960 } 6961 6962 kvm_check_async_pf_completion(vcpu); 6963 6964 if (signal_pending(current)) { 6965 r = -EINTR; 6966 vcpu->run->exit_reason = KVM_EXIT_INTR; 6967 ++vcpu->stat.signal_exits; 6968 break; 6969 } 6970 if (need_resched()) { 6971 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6972 cond_resched(); 6973 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6974 } 6975 } 6976 6977 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6978 6979 return r; 6980 } 6981 6982 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 6983 { 6984 int r; 6985 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6986 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 6987 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6988 if (r != EMULATE_DONE) 6989 return 0; 6990 return 1; 6991 } 6992 6993 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 6994 { 6995 BUG_ON(!vcpu->arch.pio.count); 6996 6997 return complete_emulated_io(vcpu); 6998 } 6999 7000 /* 7001 * Implements the following, as a state machine: 7002 * 7003 * read: 7004 * for each fragment 7005 * for each mmio piece in the fragment 7006 * write gpa, len 7007 * exit 7008 * copy data 7009 * execute insn 7010 * 7011 * write: 7012 * for each fragment 7013 * for each mmio piece in the fragment 7014 * write gpa, len 7015 * copy data 7016 * exit 7017 */ 7018 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 7019 { 7020 struct kvm_run *run = vcpu->run; 7021 struct kvm_mmio_fragment *frag; 7022 unsigned len; 7023 7024 BUG_ON(!vcpu->mmio_needed); 7025 7026 /* Complete previous fragment */ 7027 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 7028 len = min(8u, frag->len); 7029 if (!vcpu->mmio_is_write) 7030 memcpy(frag->data, run->mmio.data, len); 7031 7032 if (frag->len <= 8) { 7033 /* Switch to the next fragment. */ 7034 frag++; 7035 vcpu->mmio_cur_fragment++; 7036 } else { 7037 /* Go forward to the next mmio piece. */ 7038 frag->data += len; 7039 frag->gpa += len; 7040 frag->len -= len; 7041 } 7042 7043 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 7044 vcpu->mmio_needed = 0; 7045 7046 /* FIXME: return into emulator if single-stepping. */ 7047 if (vcpu->mmio_is_write) 7048 return 1; 7049 vcpu->mmio_read_completed = 1; 7050 return complete_emulated_io(vcpu); 7051 } 7052 7053 run->exit_reason = KVM_EXIT_MMIO; 7054 run->mmio.phys_addr = frag->gpa; 7055 if (vcpu->mmio_is_write) 7056 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 7057 run->mmio.len = min(8u, frag->len); 7058 run->mmio.is_write = vcpu->mmio_is_write; 7059 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 7060 return 0; 7061 } 7062 7063 7064 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 7065 { 7066 struct fpu *fpu = ¤t->thread.fpu; 7067 int r; 7068 sigset_t sigsaved; 7069 7070 fpu__activate_curr(fpu); 7071 7072 if (vcpu->sigset_active) 7073 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 7074 7075 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 7076 kvm_vcpu_block(vcpu); 7077 kvm_apic_accept_events(vcpu); 7078 clear_bit(KVM_REQ_UNHALT, &vcpu->requests); 7079 r = -EAGAIN; 7080 goto out; 7081 } 7082 7083 /* re-sync apic's tpr */ 7084 if (!lapic_in_kernel(vcpu)) { 7085 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 7086 r = -EINVAL; 7087 goto out; 7088 } 7089 } 7090 7091 if (unlikely(vcpu->arch.complete_userspace_io)) { 7092 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 7093 vcpu->arch.complete_userspace_io = NULL; 7094 r = cui(vcpu); 7095 if (r <= 0) 7096 goto out; 7097 } else 7098 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 7099 7100 r = vcpu_run(vcpu); 7101 7102 out: 7103 post_kvm_run_save(vcpu); 7104 if (vcpu->sigset_active) 7105 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 7106 7107 return r; 7108 } 7109 7110 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7111 { 7112 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 7113 /* 7114 * We are here if userspace calls get_regs() in the middle of 7115 * instruction emulation. Registers state needs to be copied 7116 * back from emulation context to vcpu. Userspace shouldn't do 7117 * that usually, but some bad designed PV devices (vmware 7118 * backdoor interface) need this to work 7119 */ 7120 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 7121 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7122 } 7123 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 7124 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 7125 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 7126 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 7127 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 7128 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 7129 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 7130 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 7131 #ifdef CONFIG_X86_64 7132 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 7133 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 7134 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 7135 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 7136 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 7137 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 7138 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 7139 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 7140 #endif 7141 7142 regs->rip = kvm_rip_read(vcpu); 7143 regs->rflags = kvm_get_rflags(vcpu); 7144 7145 return 0; 7146 } 7147 7148 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7149 { 7150 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 7151 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7152 7153 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 7154 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 7155 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 7156 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 7157 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 7158 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 7159 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 7160 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 7161 #ifdef CONFIG_X86_64 7162 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 7163 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 7164 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 7165 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 7166 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 7167 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 7168 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 7169 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 7170 #endif 7171 7172 kvm_rip_write(vcpu, regs->rip); 7173 kvm_set_rflags(vcpu, regs->rflags); 7174 7175 vcpu->arch.exception.pending = false; 7176 7177 kvm_make_request(KVM_REQ_EVENT, vcpu); 7178 7179 return 0; 7180 } 7181 7182 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 7183 { 7184 struct kvm_segment cs; 7185 7186 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7187 *db = cs.db; 7188 *l = cs.l; 7189 } 7190 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 7191 7192 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 7193 struct kvm_sregs *sregs) 7194 { 7195 struct desc_ptr dt; 7196 7197 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7198 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7199 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7200 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7201 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7202 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7203 7204 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7205 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7206 7207 kvm_x86_ops->get_idt(vcpu, &dt); 7208 sregs->idt.limit = dt.size; 7209 sregs->idt.base = dt.address; 7210 kvm_x86_ops->get_gdt(vcpu, &dt); 7211 sregs->gdt.limit = dt.size; 7212 sregs->gdt.base = dt.address; 7213 7214 sregs->cr0 = kvm_read_cr0(vcpu); 7215 sregs->cr2 = vcpu->arch.cr2; 7216 sregs->cr3 = kvm_read_cr3(vcpu); 7217 sregs->cr4 = kvm_read_cr4(vcpu); 7218 sregs->cr8 = kvm_get_cr8(vcpu); 7219 sregs->efer = vcpu->arch.efer; 7220 sregs->apic_base = kvm_get_apic_base(vcpu); 7221 7222 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 7223 7224 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 7225 set_bit(vcpu->arch.interrupt.nr, 7226 (unsigned long *)sregs->interrupt_bitmap); 7227 7228 return 0; 7229 } 7230 7231 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 7232 struct kvm_mp_state *mp_state) 7233 { 7234 kvm_apic_accept_events(vcpu); 7235 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 7236 vcpu->arch.pv.pv_unhalted) 7237 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 7238 else 7239 mp_state->mp_state = vcpu->arch.mp_state; 7240 7241 return 0; 7242 } 7243 7244 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 7245 struct kvm_mp_state *mp_state) 7246 { 7247 if (!lapic_in_kernel(vcpu) && 7248 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 7249 return -EINVAL; 7250 7251 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 7252 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 7253 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 7254 } else 7255 vcpu->arch.mp_state = mp_state->mp_state; 7256 kvm_make_request(KVM_REQ_EVENT, vcpu); 7257 return 0; 7258 } 7259 7260 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 7261 int reason, bool has_error_code, u32 error_code) 7262 { 7263 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7264 int ret; 7265 7266 init_emulate_ctxt(vcpu); 7267 7268 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 7269 has_error_code, error_code); 7270 7271 if (ret) 7272 return EMULATE_FAIL; 7273 7274 kvm_rip_write(vcpu, ctxt->eip); 7275 kvm_set_rflags(vcpu, ctxt->eflags); 7276 kvm_make_request(KVM_REQ_EVENT, vcpu); 7277 return EMULATE_DONE; 7278 } 7279 EXPORT_SYMBOL_GPL(kvm_task_switch); 7280 7281 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 7282 struct kvm_sregs *sregs) 7283 { 7284 struct msr_data apic_base_msr; 7285 int mmu_reset_needed = 0; 7286 int pending_vec, max_bits, idx; 7287 struct desc_ptr dt; 7288 7289 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) 7290 return -EINVAL; 7291 7292 dt.size = sregs->idt.limit; 7293 dt.address = sregs->idt.base; 7294 kvm_x86_ops->set_idt(vcpu, &dt); 7295 dt.size = sregs->gdt.limit; 7296 dt.address = sregs->gdt.base; 7297 kvm_x86_ops->set_gdt(vcpu, &dt); 7298 7299 vcpu->arch.cr2 = sregs->cr2; 7300 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 7301 vcpu->arch.cr3 = sregs->cr3; 7302 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 7303 7304 kvm_set_cr8(vcpu, sregs->cr8); 7305 7306 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 7307 kvm_x86_ops->set_efer(vcpu, sregs->efer); 7308 apic_base_msr.data = sregs->apic_base; 7309 apic_base_msr.host_initiated = true; 7310 kvm_set_apic_base(vcpu, &apic_base_msr); 7311 7312 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 7313 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 7314 vcpu->arch.cr0 = sregs->cr0; 7315 7316 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 7317 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 7318 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 7319 kvm_update_cpuid(vcpu); 7320 7321 idx = srcu_read_lock(&vcpu->kvm->srcu); 7322 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 7323 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 7324 mmu_reset_needed = 1; 7325 } 7326 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7327 7328 if (mmu_reset_needed) 7329 kvm_mmu_reset_context(vcpu); 7330 7331 max_bits = KVM_NR_INTERRUPTS; 7332 pending_vec = find_first_bit( 7333 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 7334 if (pending_vec < max_bits) { 7335 kvm_queue_interrupt(vcpu, pending_vec, false); 7336 pr_debug("Set back pending irq %d\n", pending_vec); 7337 } 7338 7339 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7340 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7341 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7342 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7343 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7344 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7345 7346 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7347 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7348 7349 update_cr8_intercept(vcpu); 7350 7351 /* Older userspace won't unhalt the vcpu on reset. */ 7352 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 7353 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 7354 !is_protmode(vcpu)) 7355 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7356 7357 kvm_make_request(KVM_REQ_EVENT, vcpu); 7358 7359 return 0; 7360 } 7361 7362 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 7363 struct kvm_guest_debug *dbg) 7364 { 7365 unsigned long rflags; 7366 int i, r; 7367 7368 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 7369 r = -EBUSY; 7370 if (vcpu->arch.exception.pending) 7371 goto out; 7372 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 7373 kvm_queue_exception(vcpu, DB_VECTOR); 7374 else 7375 kvm_queue_exception(vcpu, BP_VECTOR); 7376 } 7377 7378 /* 7379 * Read rflags as long as potentially injected trace flags are still 7380 * filtered out. 7381 */ 7382 rflags = kvm_get_rflags(vcpu); 7383 7384 vcpu->guest_debug = dbg->control; 7385 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 7386 vcpu->guest_debug = 0; 7387 7388 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 7389 for (i = 0; i < KVM_NR_DB_REGS; ++i) 7390 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 7391 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 7392 } else { 7393 for (i = 0; i < KVM_NR_DB_REGS; i++) 7394 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 7395 } 7396 kvm_update_dr7(vcpu); 7397 7398 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7399 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 7400 get_segment_base(vcpu, VCPU_SREG_CS); 7401 7402 /* 7403 * Trigger an rflags update that will inject or remove the trace 7404 * flags. 7405 */ 7406 kvm_set_rflags(vcpu, rflags); 7407 7408 kvm_x86_ops->update_bp_intercept(vcpu); 7409 7410 r = 0; 7411 7412 out: 7413 7414 return r; 7415 } 7416 7417 /* 7418 * Translate a guest virtual address to a guest physical address. 7419 */ 7420 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 7421 struct kvm_translation *tr) 7422 { 7423 unsigned long vaddr = tr->linear_address; 7424 gpa_t gpa; 7425 int idx; 7426 7427 idx = srcu_read_lock(&vcpu->kvm->srcu); 7428 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 7429 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7430 tr->physical_address = gpa; 7431 tr->valid = gpa != UNMAPPED_GVA; 7432 tr->writeable = 1; 7433 tr->usermode = 0; 7434 7435 return 0; 7436 } 7437 7438 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7439 { 7440 struct fxregs_state *fxsave = 7441 &vcpu->arch.guest_fpu.state.fxsave; 7442 7443 memcpy(fpu->fpr, fxsave->st_space, 128); 7444 fpu->fcw = fxsave->cwd; 7445 fpu->fsw = fxsave->swd; 7446 fpu->ftwx = fxsave->twd; 7447 fpu->last_opcode = fxsave->fop; 7448 fpu->last_ip = fxsave->rip; 7449 fpu->last_dp = fxsave->rdp; 7450 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 7451 7452 return 0; 7453 } 7454 7455 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7456 { 7457 struct fxregs_state *fxsave = 7458 &vcpu->arch.guest_fpu.state.fxsave; 7459 7460 memcpy(fxsave->st_space, fpu->fpr, 128); 7461 fxsave->cwd = fpu->fcw; 7462 fxsave->swd = fpu->fsw; 7463 fxsave->twd = fpu->ftwx; 7464 fxsave->fop = fpu->last_opcode; 7465 fxsave->rip = fpu->last_ip; 7466 fxsave->rdp = fpu->last_dp; 7467 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 7468 7469 return 0; 7470 } 7471 7472 static void fx_init(struct kvm_vcpu *vcpu) 7473 { 7474 fpstate_init(&vcpu->arch.guest_fpu.state); 7475 if (boot_cpu_has(X86_FEATURE_XSAVES)) 7476 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = 7477 host_xcr0 | XSTATE_COMPACTION_ENABLED; 7478 7479 /* 7480 * Ensure guest xcr0 is valid for loading 7481 */ 7482 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 7483 7484 vcpu->arch.cr0 |= X86_CR0_ET; 7485 } 7486 7487 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 7488 { 7489 if (vcpu->guest_fpu_loaded) 7490 return; 7491 7492 /* 7493 * Restore all possible states in the guest, 7494 * and assume host would use all available bits. 7495 * Guest xcr0 would be loaded later. 7496 */ 7497 vcpu->guest_fpu_loaded = 1; 7498 __kernel_fpu_begin(); 7499 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state); 7500 trace_kvm_fpu(1); 7501 } 7502 7503 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 7504 { 7505 if (!vcpu->guest_fpu_loaded) 7506 return; 7507 7508 vcpu->guest_fpu_loaded = 0; 7509 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); 7510 __kernel_fpu_end(); 7511 ++vcpu->stat.fpu_reload; 7512 trace_kvm_fpu(0); 7513 } 7514 7515 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 7516 { 7517 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask; 7518 7519 kvmclock_reset(vcpu); 7520 7521 kvm_x86_ops->vcpu_free(vcpu); 7522 free_cpumask_var(wbinvd_dirty_mask); 7523 } 7524 7525 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 7526 unsigned int id) 7527 { 7528 struct kvm_vcpu *vcpu; 7529 7530 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 7531 printk_once(KERN_WARNING 7532 "kvm: SMP vm created on host with unstable TSC; " 7533 "guest TSC will not be reliable\n"); 7534 7535 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 7536 7537 return vcpu; 7538 } 7539 7540 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 7541 { 7542 int r; 7543 7544 kvm_vcpu_mtrr_init(vcpu); 7545 r = vcpu_load(vcpu); 7546 if (r) 7547 return r; 7548 kvm_vcpu_reset(vcpu, false); 7549 kvm_mmu_setup(vcpu); 7550 vcpu_put(vcpu); 7551 return r; 7552 } 7553 7554 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 7555 { 7556 struct msr_data msr; 7557 struct kvm *kvm = vcpu->kvm; 7558 7559 if (vcpu_load(vcpu)) 7560 return; 7561 msr.data = 0x0; 7562 msr.index = MSR_IA32_TSC; 7563 msr.host_initiated = true; 7564 kvm_write_tsc(vcpu, &msr); 7565 vcpu_put(vcpu); 7566 7567 if (!kvmclock_periodic_sync) 7568 return; 7569 7570 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 7571 KVMCLOCK_SYNC_PERIOD); 7572 } 7573 7574 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 7575 { 7576 int r; 7577 vcpu->arch.apf.msr_val = 0; 7578 7579 r = vcpu_load(vcpu); 7580 BUG_ON(r); 7581 kvm_mmu_unload(vcpu); 7582 vcpu_put(vcpu); 7583 7584 kvm_x86_ops->vcpu_free(vcpu); 7585 } 7586 7587 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 7588 { 7589 vcpu->arch.hflags = 0; 7590 7591 vcpu->arch.smi_pending = 0; 7592 atomic_set(&vcpu->arch.nmi_queued, 0); 7593 vcpu->arch.nmi_pending = 0; 7594 vcpu->arch.nmi_injected = false; 7595 kvm_clear_interrupt_queue(vcpu); 7596 kvm_clear_exception_queue(vcpu); 7597 7598 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 7599 kvm_update_dr0123(vcpu); 7600 vcpu->arch.dr6 = DR6_INIT; 7601 kvm_update_dr6(vcpu); 7602 vcpu->arch.dr7 = DR7_FIXED_1; 7603 kvm_update_dr7(vcpu); 7604 7605 vcpu->arch.cr2 = 0; 7606 7607 kvm_make_request(KVM_REQ_EVENT, vcpu); 7608 vcpu->arch.apf.msr_val = 0; 7609 vcpu->arch.st.msr_val = 0; 7610 7611 kvmclock_reset(vcpu); 7612 7613 kvm_clear_async_pf_completion_queue(vcpu); 7614 kvm_async_pf_hash_reset(vcpu); 7615 vcpu->arch.apf.halted = false; 7616 7617 if (!init_event) { 7618 kvm_pmu_reset(vcpu); 7619 vcpu->arch.smbase = 0x30000; 7620 } 7621 7622 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 7623 vcpu->arch.regs_avail = ~0; 7624 vcpu->arch.regs_dirty = ~0; 7625 7626 kvm_x86_ops->vcpu_reset(vcpu, init_event); 7627 } 7628 7629 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 7630 { 7631 struct kvm_segment cs; 7632 7633 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7634 cs.selector = vector << 8; 7635 cs.base = vector << 12; 7636 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7637 kvm_rip_write(vcpu, 0); 7638 } 7639 7640 int kvm_arch_hardware_enable(void) 7641 { 7642 struct kvm *kvm; 7643 struct kvm_vcpu *vcpu; 7644 int i; 7645 int ret; 7646 u64 local_tsc; 7647 u64 max_tsc = 0; 7648 bool stable, backwards_tsc = false; 7649 7650 kvm_shared_msr_cpu_online(); 7651 ret = kvm_x86_ops->hardware_enable(); 7652 if (ret != 0) 7653 return ret; 7654 7655 local_tsc = rdtsc(); 7656 stable = !check_tsc_unstable(); 7657 list_for_each_entry(kvm, &vm_list, vm_list) { 7658 kvm_for_each_vcpu(i, vcpu, kvm) { 7659 if (!stable && vcpu->cpu == smp_processor_id()) 7660 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7661 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 7662 backwards_tsc = true; 7663 if (vcpu->arch.last_host_tsc > max_tsc) 7664 max_tsc = vcpu->arch.last_host_tsc; 7665 } 7666 } 7667 } 7668 7669 /* 7670 * Sometimes, even reliable TSCs go backwards. This happens on 7671 * platforms that reset TSC during suspend or hibernate actions, but 7672 * maintain synchronization. We must compensate. Fortunately, we can 7673 * detect that condition here, which happens early in CPU bringup, 7674 * before any KVM threads can be running. Unfortunately, we can't 7675 * bring the TSCs fully up to date with real time, as we aren't yet far 7676 * enough into CPU bringup that we know how much real time has actually 7677 * elapsed; our helper function, ktime_get_boot_ns() will be using boot 7678 * variables that haven't been updated yet. 7679 * 7680 * So we simply find the maximum observed TSC above, then record the 7681 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 7682 * the adjustment will be applied. Note that we accumulate 7683 * adjustments, in case multiple suspend cycles happen before some VCPU 7684 * gets a chance to run again. In the event that no KVM threads get a 7685 * chance to run, we will miss the entire elapsed period, as we'll have 7686 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 7687 * loose cycle time. This isn't too big a deal, since the loss will be 7688 * uniform across all VCPUs (not to mention the scenario is extremely 7689 * unlikely). It is possible that a second hibernate recovery happens 7690 * much faster than a first, causing the observed TSC here to be 7691 * smaller; this would require additional padding adjustment, which is 7692 * why we set last_host_tsc to the local tsc observed here. 7693 * 7694 * N.B. - this code below runs only on platforms with reliable TSC, 7695 * as that is the only way backwards_tsc is set above. Also note 7696 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 7697 * have the same delta_cyc adjustment applied if backwards_tsc 7698 * is detected. Note further, this adjustment is only done once, 7699 * as we reset last_host_tsc on all VCPUs to stop this from being 7700 * called multiple times (one for each physical CPU bringup). 7701 * 7702 * Platforms with unreliable TSCs don't have to deal with this, they 7703 * will be compensated by the logic in vcpu_load, which sets the TSC to 7704 * catchup mode. This will catchup all VCPUs to real time, but cannot 7705 * guarantee that they stay in perfect synchronization. 7706 */ 7707 if (backwards_tsc) { 7708 u64 delta_cyc = max_tsc - local_tsc; 7709 backwards_tsc_observed = true; 7710 list_for_each_entry(kvm, &vm_list, vm_list) { 7711 kvm_for_each_vcpu(i, vcpu, kvm) { 7712 vcpu->arch.tsc_offset_adjustment += delta_cyc; 7713 vcpu->arch.last_host_tsc = local_tsc; 7714 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7715 } 7716 7717 /* 7718 * We have to disable TSC offset matching.. if you were 7719 * booting a VM while issuing an S4 host suspend.... 7720 * you may have some problem. Solving this issue is 7721 * left as an exercise to the reader. 7722 */ 7723 kvm->arch.last_tsc_nsec = 0; 7724 kvm->arch.last_tsc_write = 0; 7725 } 7726 7727 } 7728 return 0; 7729 } 7730 7731 void kvm_arch_hardware_disable(void) 7732 { 7733 kvm_x86_ops->hardware_disable(); 7734 drop_user_return_notifiers(); 7735 } 7736 7737 int kvm_arch_hardware_setup(void) 7738 { 7739 int r; 7740 7741 r = kvm_x86_ops->hardware_setup(); 7742 if (r != 0) 7743 return r; 7744 7745 if (kvm_has_tsc_control) { 7746 /* 7747 * Make sure the user can only configure tsc_khz values that 7748 * fit into a signed integer. 7749 * A min value is not calculated needed because it will always 7750 * be 1 on all machines. 7751 */ 7752 u64 max = min(0x7fffffffULL, 7753 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 7754 kvm_max_guest_tsc_khz = max; 7755 7756 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 7757 } 7758 7759 kvm_init_msr_list(); 7760 return 0; 7761 } 7762 7763 void kvm_arch_hardware_unsetup(void) 7764 { 7765 kvm_x86_ops->hardware_unsetup(); 7766 } 7767 7768 void kvm_arch_check_processor_compat(void *rtn) 7769 { 7770 kvm_x86_ops->check_processor_compatibility(rtn); 7771 } 7772 7773 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 7774 { 7775 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 7776 } 7777 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 7778 7779 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 7780 { 7781 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 7782 } 7783 7784 struct static_key kvm_no_apic_vcpu __read_mostly; 7785 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 7786 7787 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 7788 { 7789 struct page *page; 7790 struct kvm *kvm; 7791 int r; 7792 7793 BUG_ON(vcpu->kvm == NULL); 7794 kvm = vcpu->kvm; 7795 7796 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(); 7797 vcpu->arch.pv.pv_unhalted = false; 7798 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 7799 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 7800 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7801 else 7802 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 7803 7804 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 7805 if (!page) { 7806 r = -ENOMEM; 7807 goto fail; 7808 } 7809 vcpu->arch.pio_data = page_address(page); 7810 7811 kvm_set_tsc_khz(vcpu, max_tsc_khz); 7812 7813 r = kvm_mmu_create(vcpu); 7814 if (r < 0) 7815 goto fail_free_pio_data; 7816 7817 if (irqchip_in_kernel(kvm)) { 7818 r = kvm_create_lapic(vcpu); 7819 if (r < 0) 7820 goto fail_mmu_destroy; 7821 } else 7822 static_key_slow_inc(&kvm_no_apic_vcpu); 7823 7824 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 7825 GFP_KERNEL); 7826 if (!vcpu->arch.mce_banks) { 7827 r = -ENOMEM; 7828 goto fail_free_lapic; 7829 } 7830 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 7831 7832 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 7833 r = -ENOMEM; 7834 goto fail_free_mce_banks; 7835 } 7836 7837 fx_init(vcpu); 7838 7839 vcpu->arch.ia32_tsc_adjust_msr = 0x0; 7840 vcpu->arch.pv_time_enabled = false; 7841 7842 vcpu->arch.guest_supported_xcr0 = 0; 7843 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 7844 7845 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 7846 7847 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 7848 7849 kvm_async_pf_hash_reset(vcpu); 7850 kvm_pmu_init(vcpu); 7851 7852 vcpu->arch.pending_external_vector = -1; 7853 7854 kvm_hv_vcpu_init(vcpu); 7855 7856 return 0; 7857 7858 fail_free_mce_banks: 7859 kfree(vcpu->arch.mce_banks); 7860 fail_free_lapic: 7861 kvm_free_lapic(vcpu); 7862 fail_mmu_destroy: 7863 kvm_mmu_destroy(vcpu); 7864 fail_free_pio_data: 7865 free_page((unsigned long)vcpu->arch.pio_data); 7866 fail: 7867 return r; 7868 } 7869 7870 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 7871 { 7872 int idx; 7873 7874 kvm_hv_vcpu_uninit(vcpu); 7875 kvm_pmu_destroy(vcpu); 7876 kfree(vcpu->arch.mce_banks); 7877 kvm_free_lapic(vcpu); 7878 idx = srcu_read_lock(&vcpu->kvm->srcu); 7879 kvm_mmu_destroy(vcpu); 7880 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7881 free_page((unsigned long)vcpu->arch.pio_data); 7882 if (!lapic_in_kernel(vcpu)) 7883 static_key_slow_dec(&kvm_no_apic_vcpu); 7884 } 7885 7886 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 7887 { 7888 kvm_x86_ops->sched_in(vcpu, cpu); 7889 } 7890 7891 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 7892 { 7893 if (type) 7894 return -EINVAL; 7895 7896 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 7897 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 7898 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 7899 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 7900 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 7901 7902 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 7903 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 7904 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 7905 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 7906 &kvm->arch.irq_sources_bitmap); 7907 7908 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 7909 mutex_init(&kvm->arch.apic_map_lock); 7910 mutex_init(&kvm->arch.hyperv.hv_lock); 7911 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 7912 7913 kvm->arch.kvmclock_offset = -ktime_get_boot_ns(); 7914 pvclock_update_vm_gtod_copy(kvm); 7915 7916 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 7917 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 7918 7919 kvm_page_track_init(kvm); 7920 kvm_mmu_init_vm(kvm); 7921 7922 if (kvm_x86_ops->vm_init) 7923 return kvm_x86_ops->vm_init(kvm); 7924 7925 return 0; 7926 } 7927 7928 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 7929 { 7930 int r; 7931 r = vcpu_load(vcpu); 7932 BUG_ON(r); 7933 kvm_mmu_unload(vcpu); 7934 vcpu_put(vcpu); 7935 } 7936 7937 static void kvm_free_vcpus(struct kvm *kvm) 7938 { 7939 unsigned int i; 7940 struct kvm_vcpu *vcpu; 7941 7942 /* 7943 * Unpin any mmu pages first. 7944 */ 7945 kvm_for_each_vcpu(i, vcpu, kvm) { 7946 kvm_clear_async_pf_completion_queue(vcpu); 7947 kvm_unload_vcpu_mmu(vcpu); 7948 } 7949 kvm_for_each_vcpu(i, vcpu, kvm) 7950 kvm_arch_vcpu_free(vcpu); 7951 7952 mutex_lock(&kvm->lock); 7953 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 7954 kvm->vcpus[i] = NULL; 7955 7956 atomic_set(&kvm->online_vcpus, 0); 7957 mutex_unlock(&kvm->lock); 7958 } 7959 7960 void kvm_arch_sync_events(struct kvm *kvm) 7961 { 7962 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 7963 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 7964 kvm_free_all_assigned_devices(kvm); 7965 kvm_free_pit(kvm); 7966 } 7967 7968 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 7969 { 7970 int i, r; 7971 unsigned long hva; 7972 struct kvm_memslots *slots = kvm_memslots(kvm); 7973 struct kvm_memory_slot *slot, old; 7974 7975 /* Called with kvm->slots_lock held. */ 7976 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 7977 return -EINVAL; 7978 7979 slot = id_to_memslot(slots, id); 7980 if (size) { 7981 if (slot->npages) 7982 return -EEXIST; 7983 7984 /* 7985 * MAP_SHARED to prevent internal slot pages from being moved 7986 * by fork()/COW. 7987 */ 7988 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 7989 MAP_SHARED | MAP_ANONYMOUS, 0); 7990 if (IS_ERR((void *)hva)) 7991 return PTR_ERR((void *)hva); 7992 } else { 7993 if (!slot->npages) 7994 return 0; 7995 7996 hva = 0; 7997 } 7998 7999 old = *slot; 8000 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 8001 struct kvm_userspace_memory_region m; 8002 8003 m.slot = id | (i << 16); 8004 m.flags = 0; 8005 m.guest_phys_addr = gpa; 8006 m.userspace_addr = hva; 8007 m.memory_size = size; 8008 r = __kvm_set_memory_region(kvm, &m); 8009 if (r < 0) 8010 return r; 8011 } 8012 8013 if (!size) { 8014 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 8015 WARN_ON(r < 0); 8016 } 8017 8018 return 0; 8019 } 8020 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 8021 8022 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 8023 { 8024 int r; 8025 8026 mutex_lock(&kvm->slots_lock); 8027 r = __x86_set_memory_region(kvm, id, gpa, size); 8028 mutex_unlock(&kvm->slots_lock); 8029 8030 return r; 8031 } 8032 EXPORT_SYMBOL_GPL(x86_set_memory_region); 8033 8034 void kvm_arch_destroy_vm(struct kvm *kvm) 8035 { 8036 if (current->mm == kvm->mm) { 8037 /* 8038 * Free memory regions allocated on behalf of userspace, 8039 * unless the the memory map has changed due to process exit 8040 * or fd copying. 8041 */ 8042 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 8043 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 8044 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 8045 } 8046 if (kvm_x86_ops->vm_destroy) 8047 kvm_x86_ops->vm_destroy(kvm); 8048 kvm_iommu_unmap_guest(kvm); 8049 kfree(kvm->arch.vpic); 8050 kfree(kvm->arch.vioapic); 8051 kvm_free_vcpus(kvm); 8052 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 8053 kvm_mmu_uninit_vm(kvm); 8054 } 8055 8056 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 8057 struct kvm_memory_slot *dont) 8058 { 8059 int i; 8060 8061 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8062 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 8063 kvfree(free->arch.rmap[i]); 8064 free->arch.rmap[i] = NULL; 8065 } 8066 if (i == 0) 8067 continue; 8068 8069 if (!dont || free->arch.lpage_info[i - 1] != 8070 dont->arch.lpage_info[i - 1]) { 8071 kvfree(free->arch.lpage_info[i - 1]); 8072 free->arch.lpage_info[i - 1] = NULL; 8073 } 8074 } 8075 8076 kvm_page_track_free_memslot(free, dont); 8077 } 8078 8079 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 8080 unsigned long npages) 8081 { 8082 int i; 8083 8084 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8085 struct kvm_lpage_info *linfo; 8086 unsigned long ugfn; 8087 int lpages; 8088 int level = i + 1; 8089 8090 lpages = gfn_to_index(slot->base_gfn + npages - 1, 8091 slot->base_gfn, level) + 1; 8092 8093 slot->arch.rmap[i] = 8094 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); 8095 if (!slot->arch.rmap[i]) 8096 goto out_free; 8097 if (i == 0) 8098 continue; 8099 8100 linfo = kvm_kvzalloc(lpages * sizeof(*linfo)); 8101 if (!linfo) 8102 goto out_free; 8103 8104 slot->arch.lpage_info[i - 1] = linfo; 8105 8106 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 8107 linfo[0].disallow_lpage = 1; 8108 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 8109 linfo[lpages - 1].disallow_lpage = 1; 8110 ugfn = slot->userspace_addr >> PAGE_SHIFT; 8111 /* 8112 * If the gfn and userspace address are not aligned wrt each 8113 * other, or if explicitly asked to, disable large page 8114 * support for this slot 8115 */ 8116 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 8117 !kvm_largepages_enabled()) { 8118 unsigned long j; 8119 8120 for (j = 0; j < lpages; ++j) 8121 linfo[j].disallow_lpage = 1; 8122 } 8123 } 8124 8125 if (kvm_page_track_create_memslot(slot, npages)) 8126 goto out_free; 8127 8128 return 0; 8129 8130 out_free: 8131 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8132 kvfree(slot->arch.rmap[i]); 8133 slot->arch.rmap[i] = NULL; 8134 if (i == 0) 8135 continue; 8136 8137 kvfree(slot->arch.lpage_info[i - 1]); 8138 slot->arch.lpage_info[i - 1] = NULL; 8139 } 8140 return -ENOMEM; 8141 } 8142 8143 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) 8144 { 8145 /* 8146 * memslots->generation has been incremented. 8147 * mmio generation may have reached its maximum value. 8148 */ 8149 kvm_mmu_invalidate_mmio_sptes(kvm, slots); 8150 } 8151 8152 int kvm_arch_prepare_memory_region(struct kvm *kvm, 8153 struct kvm_memory_slot *memslot, 8154 const struct kvm_userspace_memory_region *mem, 8155 enum kvm_mr_change change) 8156 { 8157 return 0; 8158 } 8159 8160 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 8161 struct kvm_memory_slot *new) 8162 { 8163 /* Still write protect RO slot */ 8164 if (new->flags & KVM_MEM_READONLY) { 8165 kvm_mmu_slot_remove_write_access(kvm, new); 8166 return; 8167 } 8168 8169 /* 8170 * Call kvm_x86_ops dirty logging hooks when they are valid. 8171 * 8172 * kvm_x86_ops->slot_disable_log_dirty is called when: 8173 * 8174 * - KVM_MR_CREATE with dirty logging is disabled 8175 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 8176 * 8177 * The reason is, in case of PML, we need to set D-bit for any slots 8178 * with dirty logging disabled in order to eliminate unnecessary GPA 8179 * logging in PML buffer (and potential PML buffer full VMEXT). This 8180 * guarantees leaving PML enabled during guest's lifetime won't have 8181 * any additonal overhead from PML when guest is running with dirty 8182 * logging disabled for memory slots. 8183 * 8184 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 8185 * to dirty logging mode. 8186 * 8187 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 8188 * 8189 * In case of write protect: 8190 * 8191 * Write protect all pages for dirty logging. 8192 * 8193 * All the sptes including the large sptes which point to this 8194 * slot are set to readonly. We can not create any new large 8195 * spte on this slot until the end of the logging. 8196 * 8197 * See the comments in fast_page_fault(). 8198 */ 8199 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 8200 if (kvm_x86_ops->slot_enable_log_dirty) 8201 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 8202 else 8203 kvm_mmu_slot_remove_write_access(kvm, new); 8204 } else { 8205 if (kvm_x86_ops->slot_disable_log_dirty) 8206 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 8207 } 8208 } 8209 8210 void kvm_arch_commit_memory_region(struct kvm *kvm, 8211 const struct kvm_userspace_memory_region *mem, 8212 const struct kvm_memory_slot *old, 8213 const struct kvm_memory_slot *new, 8214 enum kvm_mr_change change) 8215 { 8216 int nr_mmu_pages = 0; 8217 8218 if (!kvm->arch.n_requested_mmu_pages) 8219 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 8220 8221 if (nr_mmu_pages) 8222 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 8223 8224 /* 8225 * Dirty logging tracks sptes in 4k granularity, meaning that large 8226 * sptes have to be split. If live migration is successful, the guest 8227 * in the source machine will be destroyed and large sptes will be 8228 * created in the destination. However, if the guest continues to run 8229 * in the source machine (for example if live migration fails), small 8230 * sptes will remain around and cause bad performance. 8231 * 8232 * Scan sptes if dirty logging has been stopped, dropping those 8233 * which can be collapsed into a single large-page spte. Later 8234 * page faults will create the large-page sptes. 8235 */ 8236 if ((change != KVM_MR_DELETE) && 8237 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 8238 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 8239 kvm_mmu_zap_collapsible_sptes(kvm, new); 8240 8241 /* 8242 * Set up write protection and/or dirty logging for the new slot. 8243 * 8244 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 8245 * been zapped so no dirty logging staff is needed for old slot. For 8246 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 8247 * new and it's also covered when dealing with the new slot. 8248 * 8249 * FIXME: const-ify all uses of struct kvm_memory_slot. 8250 */ 8251 if (change != KVM_MR_DELETE) 8252 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 8253 } 8254 8255 void kvm_arch_flush_shadow_all(struct kvm *kvm) 8256 { 8257 kvm_mmu_invalidate_zap_all_pages(kvm); 8258 } 8259 8260 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 8261 struct kvm_memory_slot *slot) 8262 { 8263 kvm_page_track_flush_slot(kvm, slot); 8264 } 8265 8266 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 8267 { 8268 if (!list_empty_careful(&vcpu->async_pf.done)) 8269 return true; 8270 8271 if (kvm_apic_has_events(vcpu)) 8272 return true; 8273 8274 if (vcpu->arch.pv.pv_unhalted) 8275 return true; 8276 8277 if (atomic_read(&vcpu->arch.nmi_queued)) 8278 return true; 8279 8280 if (test_bit(KVM_REQ_SMI, &vcpu->requests)) 8281 return true; 8282 8283 if (kvm_arch_interrupt_allowed(vcpu) && 8284 kvm_cpu_has_interrupt(vcpu)) 8285 return true; 8286 8287 if (kvm_hv_has_stimer_pending(vcpu)) 8288 return true; 8289 8290 return false; 8291 } 8292 8293 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 8294 { 8295 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 8296 kvm_x86_ops->check_nested_events(vcpu, false); 8297 8298 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 8299 } 8300 8301 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 8302 { 8303 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 8304 } 8305 8306 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 8307 { 8308 return kvm_x86_ops->interrupt_allowed(vcpu); 8309 } 8310 8311 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 8312 { 8313 if (is_64_bit_mode(vcpu)) 8314 return kvm_rip_read(vcpu); 8315 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 8316 kvm_rip_read(vcpu)); 8317 } 8318 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 8319 8320 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 8321 { 8322 return kvm_get_linear_rip(vcpu) == linear_rip; 8323 } 8324 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 8325 8326 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 8327 { 8328 unsigned long rflags; 8329 8330 rflags = kvm_x86_ops->get_rflags(vcpu); 8331 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8332 rflags &= ~X86_EFLAGS_TF; 8333 return rflags; 8334 } 8335 EXPORT_SYMBOL_GPL(kvm_get_rflags); 8336 8337 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8338 { 8339 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 8340 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 8341 rflags |= X86_EFLAGS_TF; 8342 kvm_x86_ops->set_rflags(vcpu, rflags); 8343 } 8344 8345 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8346 { 8347 __kvm_set_rflags(vcpu, rflags); 8348 kvm_make_request(KVM_REQ_EVENT, vcpu); 8349 } 8350 EXPORT_SYMBOL_GPL(kvm_set_rflags); 8351 8352 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 8353 { 8354 int r; 8355 8356 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 8357 work->wakeup_all) 8358 return; 8359 8360 r = kvm_mmu_reload(vcpu); 8361 if (unlikely(r)) 8362 return; 8363 8364 if (!vcpu->arch.mmu.direct_map && 8365 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 8366 return; 8367 8368 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 8369 } 8370 8371 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 8372 { 8373 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 8374 } 8375 8376 static inline u32 kvm_async_pf_next_probe(u32 key) 8377 { 8378 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 8379 } 8380 8381 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8382 { 8383 u32 key = kvm_async_pf_hash_fn(gfn); 8384 8385 while (vcpu->arch.apf.gfns[key] != ~0) 8386 key = kvm_async_pf_next_probe(key); 8387 8388 vcpu->arch.apf.gfns[key] = gfn; 8389 } 8390 8391 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 8392 { 8393 int i; 8394 u32 key = kvm_async_pf_hash_fn(gfn); 8395 8396 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 8397 (vcpu->arch.apf.gfns[key] != gfn && 8398 vcpu->arch.apf.gfns[key] != ~0); i++) 8399 key = kvm_async_pf_next_probe(key); 8400 8401 return key; 8402 } 8403 8404 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8405 { 8406 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 8407 } 8408 8409 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8410 { 8411 u32 i, j, k; 8412 8413 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 8414 while (true) { 8415 vcpu->arch.apf.gfns[i] = ~0; 8416 do { 8417 j = kvm_async_pf_next_probe(j); 8418 if (vcpu->arch.apf.gfns[j] == ~0) 8419 return; 8420 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 8421 /* 8422 * k lies cyclically in ]i,j] 8423 * | i.k.j | 8424 * |....j i.k.| or |.k..j i...| 8425 */ 8426 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 8427 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 8428 i = j; 8429 } 8430 } 8431 8432 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 8433 { 8434 8435 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 8436 sizeof(val)); 8437 } 8438 8439 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 8440 struct kvm_async_pf *work) 8441 { 8442 struct x86_exception fault; 8443 8444 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 8445 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 8446 8447 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 8448 (vcpu->arch.apf.send_user_only && 8449 kvm_x86_ops->get_cpl(vcpu) == 0)) 8450 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 8451 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 8452 fault.vector = PF_VECTOR; 8453 fault.error_code_valid = true; 8454 fault.error_code = 0; 8455 fault.nested_page_fault = false; 8456 fault.address = work->arch.token; 8457 kvm_inject_page_fault(vcpu, &fault); 8458 } 8459 } 8460 8461 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 8462 struct kvm_async_pf *work) 8463 { 8464 struct x86_exception fault; 8465 8466 trace_kvm_async_pf_ready(work->arch.token, work->gva); 8467 if (work->wakeup_all) 8468 work->arch.token = ~0; /* broadcast wakeup */ 8469 else 8470 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 8471 8472 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && 8473 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 8474 fault.vector = PF_VECTOR; 8475 fault.error_code_valid = true; 8476 fault.error_code = 0; 8477 fault.nested_page_fault = false; 8478 fault.address = work->arch.token; 8479 kvm_inject_page_fault(vcpu, &fault); 8480 } 8481 vcpu->arch.apf.halted = false; 8482 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8483 } 8484 8485 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 8486 { 8487 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 8488 return true; 8489 else 8490 return !kvm_event_needs_reinjection(vcpu) && 8491 kvm_x86_ops->interrupt_allowed(vcpu); 8492 } 8493 8494 void kvm_arch_start_assignment(struct kvm *kvm) 8495 { 8496 atomic_inc(&kvm->arch.assigned_device_count); 8497 } 8498 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 8499 8500 void kvm_arch_end_assignment(struct kvm *kvm) 8501 { 8502 atomic_dec(&kvm->arch.assigned_device_count); 8503 } 8504 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 8505 8506 bool kvm_arch_has_assigned_device(struct kvm *kvm) 8507 { 8508 return atomic_read(&kvm->arch.assigned_device_count); 8509 } 8510 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 8511 8512 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 8513 { 8514 atomic_inc(&kvm->arch.noncoherent_dma_count); 8515 } 8516 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 8517 8518 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 8519 { 8520 atomic_dec(&kvm->arch.noncoherent_dma_count); 8521 } 8522 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 8523 8524 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 8525 { 8526 return atomic_read(&kvm->arch.noncoherent_dma_count); 8527 } 8528 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 8529 8530 bool kvm_arch_has_irq_bypass(void) 8531 { 8532 return kvm_x86_ops->update_pi_irte != NULL; 8533 } 8534 8535 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 8536 struct irq_bypass_producer *prod) 8537 { 8538 struct kvm_kernel_irqfd *irqfd = 8539 container_of(cons, struct kvm_kernel_irqfd, consumer); 8540 8541 irqfd->producer = prod; 8542 8543 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 8544 prod->irq, irqfd->gsi, 1); 8545 } 8546 8547 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 8548 struct irq_bypass_producer *prod) 8549 { 8550 int ret; 8551 struct kvm_kernel_irqfd *irqfd = 8552 container_of(cons, struct kvm_kernel_irqfd, consumer); 8553 8554 WARN_ON(irqfd->producer != prod); 8555 irqfd->producer = NULL; 8556 8557 /* 8558 * When producer of consumer is unregistered, we change back to 8559 * remapped mode, so we can re-use the current implementation 8560 * when the irq is masked/disabled or the consumer side (KVM 8561 * int this case doesn't want to receive the interrupts. 8562 */ 8563 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 8564 if (ret) 8565 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 8566 " fails: %d\n", irqfd->consumer.token, ret); 8567 } 8568 8569 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 8570 uint32_t guest_irq, bool set) 8571 { 8572 if (!kvm_x86_ops->update_pi_irte) 8573 return -EINVAL; 8574 8575 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 8576 } 8577 8578 bool kvm_vector_hashing_enabled(void) 8579 { 8580 return vector_hashing; 8581 } 8582 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); 8583 8584 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 8585 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 8586 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 8587 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 8588 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 8589 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 8590 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 8591 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 8592 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 8593 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 8594 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 8595 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 8596 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 8597 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 8598 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 8599 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 8600 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 8601 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 8602 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 8603