1 #include <linux/clocksource.h> 2 #include <linux/clockchips.h> 3 #include <linux/interrupt.h> 4 #include <linux/export.h> 5 #include <linux/delay.h> 6 #include <linux/errno.h> 7 #include <linux/i8253.h> 8 #include <linux/slab.h> 9 #include <linux/hpet.h> 10 #include <linux/init.h> 11 #include <linux/cpu.h> 12 #include <linux/pm.h> 13 #include <linux/io.h> 14 15 #include <asm/irqdomain.h> 16 #include <asm/fixmap.h> 17 #include <asm/hpet.h> 18 #include <asm/time.h> 19 20 #define HPET_MASK CLOCKSOURCE_MASK(32) 21 22 /* FSEC = 10^-15 23 NSEC = 10^-9 */ 24 #define FSEC_PER_NSEC 1000000L 25 26 #define HPET_DEV_USED_BIT 2 27 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) 28 #define HPET_DEV_VALID 0x8 29 #define HPET_DEV_FSB_CAP 0x1000 30 #define HPET_DEV_PERI_CAP 0x2000 31 32 #define HPET_MIN_CYCLES 128 33 #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1)) 34 35 /* 36 * HPET address is set in acpi/boot.c, when an ACPI entry exists 37 */ 38 unsigned long hpet_address; 39 u8 hpet_blockid; /* OS timer block num */ 40 u8 hpet_msi_disable; 41 42 #ifdef CONFIG_PCI_MSI 43 static unsigned long hpet_num_timers; 44 #endif 45 static void __iomem *hpet_virt_address; 46 47 struct hpet_dev { 48 struct clock_event_device evt; 49 unsigned int num; 50 int cpu; 51 unsigned int irq; 52 unsigned int flags; 53 char name[10]; 54 }; 55 56 inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev) 57 { 58 return container_of(evtdev, struct hpet_dev, evt); 59 } 60 61 inline unsigned int hpet_readl(unsigned int a) 62 { 63 return readl(hpet_virt_address + a); 64 } 65 66 static inline void hpet_writel(unsigned int d, unsigned int a) 67 { 68 writel(d, hpet_virt_address + a); 69 } 70 71 #ifdef CONFIG_X86_64 72 #include <asm/pgtable.h> 73 #endif 74 75 static inline void hpet_set_mapping(void) 76 { 77 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); 78 } 79 80 static inline void hpet_clear_mapping(void) 81 { 82 iounmap(hpet_virt_address); 83 hpet_virt_address = NULL; 84 } 85 86 /* 87 * HPET command line enable / disable 88 */ 89 int boot_hpet_disable; 90 int hpet_force_user; 91 static int hpet_verbose; 92 93 static int __init hpet_setup(char *str) 94 { 95 while (str) { 96 char *next = strchr(str, ','); 97 98 if (next) 99 *next++ = 0; 100 if (!strncmp("disable", str, 7)) 101 boot_hpet_disable = 1; 102 if (!strncmp("force", str, 5)) 103 hpet_force_user = 1; 104 if (!strncmp("verbose", str, 7)) 105 hpet_verbose = 1; 106 str = next; 107 } 108 return 1; 109 } 110 __setup("hpet=", hpet_setup); 111 112 static int __init disable_hpet(char *str) 113 { 114 boot_hpet_disable = 1; 115 return 1; 116 } 117 __setup("nohpet", disable_hpet); 118 119 static inline int is_hpet_capable(void) 120 { 121 return !boot_hpet_disable && hpet_address; 122 } 123 124 /* 125 * HPET timer interrupt enable / disable 126 */ 127 static int hpet_legacy_int_enabled; 128 129 /** 130 * is_hpet_enabled - check whether the hpet timer interrupt is enabled 131 */ 132 int is_hpet_enabled(void) 133 { 134 return is_hpet_capable() && hpet_legacy_int_enabled; 135 } 136 EXPORT_SYMBOL_GPL(is_hpet_enabled); 137 138 static void _hpet_print_config(const char *function, int line) 139 { 140 u32 i, timers, l, h; 141 printk(KERN_INFO "hpet: %s(%d):\n", function, line); 142 l = hpet_readl(HPET_ID); 143 h = hpet_readl(HPET_PERIOD); 144 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 145 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); 146 l = hpet_readl(HPET_CFG); 147 h = hpet_readl(HPET_STATUS); 148 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); 149 l = hpet_readl(HPET_COUNTER); 150 h = hpet_readl(HPET_COUNTER+4); 151 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); 152 153 for (i = 0; i < timers; i++) { 154 l = hpet_readl(HPET_Tn_CFG(i)); 155 h = hpet_readl(HPET_Tn_CFG(i)+4); 156 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", 157 i, l, h); 158 l = hpet_readl(HPET_Tn_CMP(i)); 159 h = hpet_readl(HPET_Tn_CMP(i)+4); 160 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", 161 i, l, h); 162 l = hpet_readl(HPET_Tn_ROUTE(i)); 163 h = hpet_readl(HPET_Tn_ROUTE(i)+4); 164 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", 165 i, l, h); 166 } 167 } 168 169 #define hpet_print_config() \ 170 do { \ 171 if (hpet_verbose) \ 172 _hpet_print_config(__func__, __LINE__); \ 173 } while (0) 174 175 /* 176 * When the hpet driver (/dev/hpet) is enabled, we need to reserve 177 * timer 0 and timer 1 in case of RTC emulation. 178 */ 179 #ifdef CONFIG_HPET 180 181 static void hpet_reserve_msi_timers(struct hpet_data *hd); 182 183 static void hpet_reserve_platform_timers(unsigned int id) 184 { 185 struct hpet __iomem *hpet = hpet_virt_address; 186 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; 187 unsigned int nrtimers, i; 188 struct hpet_data hd; 189 190 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 191 192 memset(&hd, 0, sizeof(hd)); 193 hd.hd_phys_address = hpet_address; 194 hd.hd_address = hpet; 195 hd.hd_nirqs = nrtimers; 196 hpet_reserve_timer(&hd, 0); 197 198 #ifdef CONFIG_HPET_EMULATE_RTC 199 hpet_reserve_timer(&hd, 1); 200 #endif 201 202 /* 203 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 204 * is wrong for i8259!) not the output IRQ. Many BIOS writers 205 * don't bother configuring *any* comparator interrupts. 206 */ 207 hd.hd_irq[0] = HPET_LEGACY_8254; 208 hd.hd_irq[1] = HPET_LEGACY_RTC; 209 210 for (i = 2; i < nrtimers; timer++, i++) { 211 hd.hd_irq[i] = (readl(&timer->hpet_config) & 212 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; 213 } 214 215 hpet_reserve_msi_timers(&hd); 216 217 hpet_alloc(&hd); 218 219 } 220 #else 221 static void hpet_reserve_platform_timers(unsigned int id) { } 222 #endif 223 224 /* 225 * Common hpet info 226 */ 227 static unsigned long hpet_freq; 228 229 static void hpet_legacy_set_mode(enum clock_event_mode mode, 230 struct clock_event_device *evt); 231 static int hpet_legacy_next_event(unsigned long delta, 232 struct clock_event_device *evt); 233 234 /* 235 * The hpet clock event device 236 */ 237 static struct clock_event_device hpet_clockevent = { 238 .name = "hpet", 239 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 240 .set_mode = hpet_legacy_set_mode, 241 .set_next_event = hpet_legacy_next_event, 242 .irq = 0, 243 .rating = 50, 244 }; 245 246 static void hpet_stop_counter(void) 247 { 248 unsigned long cfg = hpet_readl(HPET_CFG); 249 cfg &= ~HPET_CFG_ENABLE; 250 hpet_writel(cfg, HPET_CFG); 251 } 252 253 static void hpet_reset_counter(void) 254 { 255 hpet_writel(0, HPET_COUNTER); 256 hpet_writel(0, HPET_COUNTER + 4); 257 } 258 259 static void hpet_start_counter(void) 260 { 261 unsigned int cfg = hpet_readl(HPET_CFG); 262 cfg |= HPET_CFG_ENABLE; 263 hpet_writel(cfg, HPET_CFG); 264 } 265 266 static void hpet_restart_counter(void) 267 { 268 hpet_stop_counter(); 269 hpet_reset_counter(); 270 hpet_start_counter(); 271 } 272 273 static void hpet_resume_device(void) 274 { 275 force_hpet_resume(); 276 } 277 278 static void hpet_resume_counter(struct clocksource *cs) 279 { 280 hpet_resume_device(); 281 hpet_restart_counter(); 282 } 283 284 static void hpet_enable_legacy_int(void) 285 { 286 unsigned int cfg = hpet_readl(HPET_CFG); 287 288 cfg |= HPET_CFG_LEGACY; 289 hpet_writel(cfg, HPET_CFG); 290 hpet_legacy_int_enabled = 1; 291 } 292 293 static void hpet_legacy_clockevent_register(void) 294 { 295 /* Start HPET legacy interrupts */ 296 hpet_enable_legacy_int(); 297 298 /* 299 * Start hpet with the boot cpu mask and make it 300 * global after the IO_APIC has been initialized. 301 */ 302 hpet_clockevent.cpumask = cpumask_of(smp_processor_id()); 303 clockevents_config_and_register(&hpet_clockevent, hpet_freq, 304 HPET_MIN_PROG_DELTA, 0x7FFFFFFF); 305 global_clock_event = &hpet_clockevent; 306 printk(KERN_DEBUG "hpet clockevent registered\n"); 307 } 308 309 static void hpet_set_mode(enum clock_event_mode mode, 310 struct clock_event_device *evt, int timer) 311 { 312 unsigned int cfg, cmp, now; 313 uint64_t delta; 314 315 switch (mode) { 316 case CLOCK_EVT_MODE_PERIODIC: 317 hpet_stop_counter(); 318 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; 319 delta >>= evt->shift; 320 now = hpet_readl(HPET_COUNTER); 321 cmp = now + (unsigned int) delta; 322 cfg = hpet_readl(HPET_Tn_CFG(timer)); 323 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | 324 HPET_TN_SETVAL | HPET_TN_32BIT; 325 hpet_writel(cfg, HPET_Tn_CFG(timer)); 326 hpet_writel(cmp, HPET_Tn_CMP(timer)); 327 udelay(1); 328 /* 329 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL 330 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL 331 * bit is automatically cleared after the first write. 332 * (See AMD-8111 HyperTransport I/O Hub Data Sheet, 333 * Publication # 24674) 334 */ 335 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer)); 336 hpet_start_counter(); 337 hpet_print_config(); 338 break; 339 340 case CLOCK_EVT_MODE_ONESHOT: 341 cfg = hpet_readl(HPET_Tn_CFG(timer)); 342 cfg &= ~HPET_TN_PERIODIC; 343 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 344 hpet_writel(cfg, HPET_Tn_CFG(timer)); 345 break; 346 347 case CLOCK_EVT_MODE_UNUSED: 348 case CLOCK_EVT_MODE_SHUTDOWN: 349 cfg = hpet_readl(HPET_Tn_CFG(timer)); 350 cfg &= ~HPET_TN_ENABLE; 351 hpet_writel(cfg, HPET_Tn_CFG(timer)); 352 break; 353 354 case CLOCK_EVT_MODE_RESUME: 355 if (timer == 0) { 356 hpet_enable_legacy_int(); 357 } else { 358 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 359 irq_domain_activate_irq(irq_get_irq_data(hdev->irq)); 360 disable_irq(hdev->irq); 361 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); 362 enable_irq(hdev->irq); 363 } 364 hpet_print_config(); 365 break; 366 } 367 } 368 369 static int hpet_next_event(unsigned long delta, 370 struct clock_event_device *evt, int timer) 371 { 372 u32 cnt; 373 s32 res; 374 375 cnt = hpet_readl(HPET_COUNTER); 376 cnt += (u32) delta; 377 hpet_writel(cnt, HPET_Tn_CMP(timer)); 378 379 /* 380 * HPETs are a complete disaster. The compare register is 381 * based on a equal comparison and neither provides a less 382 * than or equal functionality (which would require to take 383 * the wraparound into account) nor a simple count down event 384 * mode. Further the write to the comparator register is 385 * delayed internally up to two HPET clock cycles in certain 386 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even 387 * longer delays. We worked around that by reading back the 388 * compare register, but that required another workaround for 389 * ICH9,10 chips where the first readout after write can 390 * return the old stale value. We already had a minimum 391 * programming delta of 5us enforced, but a NMI or SMI hitting 392 * between the counter readout and the comparator write can 393 * move us behind that point easily. Now instead of reading 394 * the compare register back several times, we make the ETIME 395 * decision based on the following: Return ETIME if the 396 * counter value after the write is less than HPET_MIN_CYCLES 397 * away from the event or if the counter is already ahead of 398 * the event. The minimum programming delta for the generic 399 * clockevents code is set to 1.5 * HPET_MIN_CYCLES. 400 */ 401 res = (s32)(cnt - hpet_readl(HPET_COUNTER)); 402 403 return res < HPET_MIN_CYCLES ? -ETIME : 0; 404 } 405 406 static void hpet_legacy_set_mode(enum clock_event_mode mode, 407 struct clock_event_device *evt) 408 { 409 hpet_set_mode(mode, evt, 0); 410 } 411 412 static int hpet_legacy_next_event(unsigned long delta, 413 struct clock_event_device *evt) 414 { 415 return hpet_next_event(delta, evt, 0); 416 } 417 418 /* 419 * HPET MSI Support 420 */ 421 #ifdef CONFIG_PCI_MSI 422 423 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); 424 static struct hpet_dev *hpet_devs; 425 static struct irq_domain *hpet_domain; 426 427 void hpet_msi_unmask(struct irq_data *data) 428 { 429 struct hpet_dev *hdev = data->handler_data; 430 unsigned int cfg; 431 432 /* unmask it */ 433 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 434 cfg |= HPET_TN_ENABLE | HPET_TN_FSB; 435 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 436 } 437 438 void hpet_msi_mask(struct irq_data *data) 439 { 440 struct hpet_dev *hdev = data->handler_data; 441 unsigned int cfg; 442 443 /* mask it */ 444 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 445 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB); 446 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 447 } 448 449 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg) 450 { 451 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); 452 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); 453 } 454 455 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg) 456 { 457 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); 458 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); 459 msg->address_hi = 0; 460 } 461 462 static void hpet_msi_set_mode(enum clock_event_mode mode, 463 struct clock_event_device *evt) 464 { 465 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 466 hpet_set_mode(mode, evt, hdev->num); 467 } 468 469 static int hpet_msi_next_event(unsigned long delta, 470 struct clock_event_device *evt) 471 { 472 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 473 return hpet_next_event(delta, evt, hdev->num); 474 } 475 476 static irqreturn_t hpet_interrupt_handler(int irq, void *data) 477 { 478 struct hpet_dev *dev = (struct hpet_dev *)data; 479 struct clock_event_device *hevt = &dev->evt; 480 481 if (!hevt->event_handler) { 482 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", 483 dev->num); 484 return IRQ_HANDLED; 485 } 486 487 hevt->event_handler(hevt); 488 return IRQ_HANDLED; 489 } 490 491 static int hpet_setup_irq(struct hpet_dev *dev) 492 { 493 494 if (request_irq(dev->irq, hpet_interrupt_handler, 495 IRQF_TIMER | IRQF_NOBALANCING, 496 dev->name, dev)) 497 return -1; 498 499 disable_irq(dev->irq); 500 irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); 501 enable_irq(dev->irq); 502 503 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", 504 dev->name, dev->irq); 505 506 return 0; 507 } 508 509 /* This should be called in specific @cpu */ 510 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) 511 { 512 struct clock_event_device *evt = &hdev->evt; 513 514 WARN_ON(cpu != smp_processor_id()); 515 if (!(hdev->flags & HPET_DEV_VALID)) 516 return; 517 518 hdev->cpu = cpu; 519 per_cpu(cpu_hpet_dev, cpu) = hdev; 520 evt->name = hdev->name; 521 hpet_setup_irq(hdev); 522 evt->irq = hdev->irq; 523 524 evt->rating = 110; 525 evt->features = CLOCK_EVT_FEAT_ONESHOT; 526 if (hdev->flags & HPET_DEV_PERI_CAP) 527 evt->features |= CLOCK_EVT_FEAT_PERIODIC; 528 529 evt->set_mode = hpet_msi_set_mode; 530 evt->set_next_event = hpet_msi_next_event; 531 evt->cpumask = cpumask_of(hdev->cpu); 532 533 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA, 534 0x7FFFFFFF); 535 } 536 537 #ifdef CONFIG_HPET 538 /* Reserve at least one timer for userspace (/dev/hpet) */ 539 #define RESERVE_TIMERS 1 540 #else 541 #define RESERVE_TIMERS 0 542 #endif 543 544 static void hpet_msi_capability_lookup(unsigned int start_timer) 545 { 546 unsigned int id; 547 unsigned int num_timers; 548 unsigned int num_timers_used = 0; 549 int i, irq; 550 551 if (hpet_msi_disable) 552 return; 553 554 if (boot_cpu_has(X86_FEATURE_ARAT)) 555 return; 556 id = hpet_readl(HPET_ID); 557 558 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); 559 num_timers++; /* Value read out starts from 0 */ 560 hpet_print_config(); 561 562 hpet_domain = hpet_create_irq_domain(hpet_blockid); 563 if (!hpet_domain) 564 return; 565 566 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); 567 if (!hpet_devs) 568 return; 569 570 hpet_num_timers = num_timers; 571 572 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { 573 struct hpet_dev *hdev = &hpet_devs[num_timers_used]; 574 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); 575 576 /* Only consider HPET timer with MSI support */ 577 if (!(cfg & HPET_TN_FSB_CAP)) 578 continue; 579 580 hdev->flags = 0; 581 if (cfg & HPET_TN_PERIODIC_CAP) 582 hdev->flags |= HPET_DEV_PERI_CAP; 583 sprintf(hdev->name, "hpet%d", i); 584 hdev->num = i; 585 586 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num); 587 if (irq <= 0) 588 continue; 589 590 hdev->irq = irq; 591 hdev->flags |= HPET_DEV_FSB_CAP; 592 hdev->flags |= HPET_DEV_VALID; 593 num_timers_used++; 594 if (num_timers_used == num_possible_cpus()) 595 break; 596 } 597 598 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", 599 num_timers, num_timers_used); 600 } 601 602 #ifdef CONFIG_HPET 603 static void hpet_reserve_msi_timers(struct hpet_data *hd) 604 { 605 int i; 606 607 if (!hpet_devs) 608 return; 609 610 for (i = 0; i < hpet_num_timers; i++) { 611 struct hpet_dev *hdev = &hpet_devs[i]; 612 613 if (!(hdev->flags & HPET_DEV_VALID)) 614 continue; 615 616 hd->hd_irq[hdev->num] = hdev->irq; 617 hpet_reserve_timer(hd, hdev->num); 618 } 619 } 620 #endif 621 622 static struct hpet_dev *hpet_get_unused_timer(void) 623 { 624 int i; 625 626 if (!hpet_devs) 627 return NULL; 628 629 for (i = 0; i < hpet_num_timers; i++) { 630 struct hpet_dev *hdev = &hpet_devs[i]; 631 632 if (!(hdev->flags & HPET_DEV_VALID)) 633 continue; 634 if (test_and_set_bit(HPET_DEV_USED_BIT, 635 (unsigned long *)&hdev->flags)) 636 continue; 637 return hdev; 638 } 639 return NULL; 640 } 641 642 struct hpet_work_struct { 643 struct delayed_work work; 644 struct completion complete; 645 }; 646 647 static void hpet_work(struct work_struct *w) 648 { 649 struct hpet_dev *hdev; 650 int cpu = smp_processor_id(); 651 struct hpet_work_struct *hpet_work; 652 653 hpet_work = container_of(w, struct hpet_work_struct, work.work); 654 655 hdev = hpet_get_unused_timer(); 656 if (hdev) 657 init_one_hpet_msi_clockevent(hdev, cpu); 658 659 complete(&hpet_work->complete); 660 } 661 662 static int hpet_cpuhp_notify(struct notifier_block *n, 663 unsigned long action, void *hcpu) 664 { 665 unsigned long cpu = (unsigned long)hcpu; 666 struct hpet_work_struct work; 667 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); 668 669 switch (action & 0xf) { 670 case CPU_ONLINE: 671 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work); 672 init_completion(&work.complete); 673 /* FIXME: add schedule_work_on() */ 674 schedule_delayed_work_on(cpu, &work.work, 0); 675 wait_for_completion(&work.complete); 676 destroy_delayed_work_on_stack(&work.work); 677 break; 678 case CPU_DEAD: 679 if (hdev) { 680 free_irq(hdev->irq, hdev); 681 hdev->flags &= ~HPET_DEV_USED; 682 per_cpu(cpu_hpet_dev, cpu) = NULL; 683 } 684 break; 685 } 686 return NOTIFY_OK; 687 } 688 #else 689 690 static void hpet_msi_capability_lookup(unsigned int start_timer) 691 { 692 return; 693 } 694 695 #ifdef CONFIG_HPET 696 static void hpet_reserve_msi_timers(struct hpet_data *hd) 697 { 698 return; 699 } 700 #endif 701 702 static int hpet_cpuhp_notify(struct notifier_block *n, 703 unsigned long action, void *hcpu) 704 { 705 return NOTIFY_OK; 706 } 707 708 #endif 709 710 /* 711 * Clock source related code 712 */ 713 static cycle_t read_hpet(struct clocksource *cs) 714 { 715 return (cycle_t)hpet_readl(HPET_COUNTER); 716 } 717 718 static struct clocksource clocksource_hpet = { 719 .name = "hpet", 720 .rating = 250, 721 .read = read_hpet, 722 .mask = HPET_MASK, 723 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 724 .resume = hpet_resume_counter, 725 .archdata = { .vclock_mode = VCLOCK_HPET }, 726 }; 727 728 static int hpet_clocksource_register(void) 729 { 730 u64 start, now; 731 cycle_t t1; 732 733 /* Start the counter */ 734 hpet_restart_counter(); 735 736 /* Verify whether hpet counter works */ 737 t1 = hpet_readl(HPET_COUNTER); 738 rdtscll(start); 739 740 /* 741 * We don't know the TSC frequency yet, but waiting for 742 * 200000 TSC cycles is safe: 743 * 4 GHz == 50us 744 * 1 GHz == 200us 745 */ 746 do { 747 rep_nop(); 748 rdtscll(now); 749 } while ((now - start) < 200000UL); 750 751 if (t1 == hpet_readl(HPET_COUNTER)) { 752 printk(KERN_WARNING 753 "HPET counter not counting. HPET disabled\n"); 754 return -ENODEV; 755 } 756 757 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); 758 return 0; 759 } 760 761 static u32 *hpet_boot_cfg; 762 763 /** 764 * hpet_enable - Try to setup the HPET timer. Returns 1 on success. 765 */ 766 int __init hpet_enable(void) 767 { 768 u32 hpet_period, cfg, id; 769 u64 freq; 770 unsigned int i, last; 771 772 if (!is_hpet_capable()) 773 return 0; 774 775 hpet_set_mapping(); 776 777 /* 778 * Read the period and check for a sane value: 779 */ 780 hpet_period = hpet_readl(HPET_PERIOD); 781 782 /* 783 * AMD SB700 based systems with spread spectrum enabled use a 784 * SMM based HPET emulation to provide proper frequency 785 * setting. The SMM code is initialized with the first HPET 786 * register access and takes some time to complete. During 787 * this time the config register reads 0xffffffff. We check 788 * for max. 1000 loops whether the config register reads a non 789 * 0xffffffff value to make sure that HPET is up and running 790 * before we go further. A counting loop is safe, as the HPET 791 * access takes thousands of CPU cycles. On non SB700 based 792 * machines this check is only done once and has no side 793 * effects. 794 */ 795 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { 796 if (i == 1000) { 797 printk(KERN_WARNING 798 "HPET config register value = 0xFFFFFFFF. " 799 "Disabling HPET\n"); 800 goto out_nohpet; 801 } 802 } 803 804 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) 805 goto out_nohpet; 806 807 /* 808 * The period is a femto seconds value. Convert it to a 809 * frequency. 810 */ 811 freq = FSEC_PER_SEC; 812 do_div(freq, hpet_period); 813 hpet_freq = freq; 814 815 /* 816 * Read the HPET ID register to retrieve the IRQ routing 817 * information and the number of channels 818 */ 819 id = hpet_readl(HPET_ID); 820 hpet_print_config(); 821 822 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT; 823 824 #ifdef CONFIG_HPET_EMULATE_RTC 825 /* 826 * The legacy routing mode needs at least two channels, tick timer 827 * and the rtc emulation channel. 828 */ 829 if (!last) 830 goto out_nohpet; 831 #endif 832 833 cfg = hpet_readl(HPET_CFG); 834 hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg), 835 GFP_KERNEL); 836 if (hpet_boot_cfg) 837 *hpet_boot_cfg = cfg; 838 else 839 pr_warn("HPET initial state will not be saved\n"); 840 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY); 841 hpet_writel(cfg, HPET_CFG); 842 if (cfg) 843 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n", 844 cfg); 845 846 for (i = 0; i <= last; ++i) { 847 cfg = hpet_readl(HPET_Tn_CFG(i)); 848 if (hpet_boot_cfg) 849 hpet_boot_cfg[i + 1] = cfg; 850 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB); 851 hpet_writel(cfg, HPET_Tn_CFG(i)); 852 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP 853 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE 854 | HPET_TN_FSB | HPET_TN_FSB_CAP); 855 if (cfg) 856 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n", 857 cfg, i); 858 } 859 hpet_print_config(); 860 861 if (hpet_clocksource_register()) 862 goto out_nohpet; 863 864 if (id & HPET_ID_LEGSUP) { 865 hpet_legacy_clockevent_register(); 866 return 1; 867 } 868 return 0; 869 870 out_nohpet: 871 hpet_clear_mapping(); 872 hpet_address = 0; 873 return 0; 874 } 875 876 /* 877 * Needs to be late, as the reserve_timer code calls kalloc ! 878 * 879 * Not a problem on i386 as hpet_enable is called from late_time_init, 880 * but on x86_64 it is necessary ! 881 */ 882 static __init int hpet_late_init(void) 883 { 884 int cpu; 885 886 if (boot_hpet_disable) 887 return -ENODEV; 888 889 if (!hpet_address) { 890 if (!force_hpet_address) 891 return -ENODEV; 892 893 hpet_address = force_hpet_address; 894 hpet_enable(); 895 } 896 897 if (!hpet_virt_address) 898 return -ENODEV; 899 900 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP) 901 hpet_msi_capability_lookup(2); 902 else 903 hpet_msi_capability_lookup(0); 904 905 hpet_reserve_platform_timers(hpet_readl(HPET_ID)); 906 hpet_print_config(); 907 908 if (hpet_msi_disable) 909 return 0; 910 911 if (boot_cpu_has(X86_FEATURE_ARAT)) 912 return 0; 913 914 cpu_notifier_register_begin(); 915 for_each_online_cpu(cpu) { 916 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); 917 } 918 919 /* This notifier should be called after workqueue is ready */ 920 __hotcpu_notifier(hpet_cpuhp_notify, -20); 921 cpu_notifier_register_done(); 922 923 return 0; 924 } 925 fs_initcall(hpet_late_init); 926 927 void hpet_disable(void) 928 { 929 if (is_hpet_capable() && hpet_virt_address) { 930 unsigned int cfg = hpet_readl(HPET_CFG), id, last; 931 932 if (hpet_boot_cfg) 933 cfg = *hpet_boot_cfg; 934 else if (hpet_legacy_int_enabled) { 935 cfg &= ~HPET_CFG_LEGACY; 936 hpet_legacy_int_enabled = 0; 937 } 938 cfg &= ~HPET_CFG_ENABLE; 939 hpet_writel(cfg, HPET_CFG); 940 941 if (!hpet_boot_cfg) 942 return; 943 944 id = hpet_readl(HPET_ID); 945 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); 946 947 for (id = 0; id <= last; ++id) 948 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id)); 949 950 if (*hpet_boot_cfg & HPET_CFG_ENABLE) 951 hpet_writel(*hpet_boot_cfg, HPET_CFG); 952 } 953 } 954 955 #ifdef CONFIG_HPET_EMULATE_RTC 956 957 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET 958 * is enabled, we support RTC interrupt functionality in software. 959 * RTC has 3 kinds of interrupts: 960 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock 961 * is updated 962 * 2) Alarm Interrupt - generate an interrupt at a specific time of day 963 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies 964 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) 965 * (1) and (2) above are implemented using polling at a frequency of 966 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt 967 * overhead. (DEFAULT_RTC_INT_FREQ) 968 * For (3), we use interrupts at 64Hz or user specified periodic 969 * frequency, whichever is higher. 970 */ 971 #include <linux/mc146818rtc.h> 972 #include <linux/rtc.h> 973 #include <asm/rtc.h> 974 975 #define DEFAULT_RTC_INT_FREQ 64 976 #define DEFAULT_RTC_SHIFT 6 977 #define RTC_NUM_INTS 1 978 979 static unsigned long hpet_rtc_flags; 980 static int hpet_prev_update_sec; 981 static struct rtc_time hpet_alarm_time; 982 static unsigned long hpet_pie_count; 983 static u32 hpet_t1_cmp; 984 static u32 hpet_default_delta; 985 static u32 hpet_pie_delta; 986 static unsigned long hpet_pie_limit; 987 988 static rtc_irq_handler irq_handler; 989 990 /* 991 * Check that the hpet counter c1 is ahead of the c2 992 */ 993 static inline int hpet_cnt_ahead(u32 c1, u32 c2) 994 { 995 return (s32)(c2 - c1) < 0; 996 } 997 998 /* 999 * Registers a IRQ handler. 1000 */ 1001 int hpet_register_irq_handler(rtc_irq_handler handler) 1002 { 1003 if (!is_hpet_enabled()) 1004 return -ENODEV; 1005 if (irq_handler) 1006 return -EBUSY; 1007 1008 irq_handler = handler; 1009 1010 return 0; 1011 } 1012 EXPORT_SYMBOL_GPL(hpet_register_irq_handler); 1013 1014 /* 1015 * Deregisters the IRQ handler registered with hpet_register_irq_handler() 1016 * and does cleanup. 1017 */ 1018 void hpet_unregister_irq_handler(rtc_irq_handler handler) 1019 { 1020 if (!is_hpet_enabled()) 1021 return; 1022 1023 irq_handler = NULL; 1024 hpet_rtc_flags = 0; 1025 } 1026 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); 1027 1028 /* 1029 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode 1030 * is not supported by all HPET implementations for timer 1. 1031 * 1032 * hpet_rtc_timer_init() is called when the rtc is initialized. 1033 */ 1034 int hpet_rtc_timer_init(void) 1035 { 1036 unsigned int cfg, cnt, delta; 1037 unsigned long flags; 1038 1039 if (!is_hpet_enabled()) 1040 return 0; 1041 1042 if (!hpet_default_delta) { 1043 uint64_t clc; 1044 1045 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1046 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; 1047 hpet_default_delta = clc; 1048 } 1049 1050 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1051 delta = hpet_default_delta; 1052 else 1053 delta = hpet_pie_delta; 1054 1055 local_irq_save(flags); 1056 1057 cnt = delta + hpet_readl(HPET_COUNTER); 1058 hpet_writel(cnt, HPET_T1_CMP); 1059 hpet_t1_cmp = cnt; 1060 1061 cfg = hpet_readl(HPET_T1_CFG); 1062 cfg &= ~HPET_TN_PERIODIC; 1063 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 1064 hpet_writel(cfg, HPET_T1_CFG); 1065 1066 local_irq_restore(flags); 1067 1068 return 1; 1069 } 1070 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); 1071 1072 static void hpet_disable_rtc_channel(void) 1073 { 1074 unsigned long cfg; 1075 cfg = hpet_readl(HPET_T1_CFG); 1076 cfg &= ~HPET_TN_ENABLE; 1077 hpet_writel(cfg, HPET_T1_CFG); 1078 } 1079 1080 /* 1081 * The functions below are called from rtc driver. 1082 * Return 0 if HPET is not being used. 1083 * Otherwise do the necessary changes and return 1. 1084 */ 1085 int hpet_mask_rtc_irq_bit(unsigned long bit_mask) 1086 { 1087 if (!is_hpet_enabled()) 1088 return 0; 1089 1090 hpet_rtc_flags &= ~bit_mask; 1091 if (unlikely(!hpet_rtc_flags)) 1092 hpet_disable_rtc_channel(); 1093 1094 return 1; 1095 } 1096 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); 1097 1098 int hpet_set_rtc_irq_bit(unsigned long bit_mask) 1099 { 1100 unsigned long oldbits = hpet_rtc_flags; 1101 1102 if (!is_hpet_enabled()) 1103 return 0; 1104 1105 hpet_rtc_flags |= bit_mask; 1106 1107 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) 1108 hpet_prev_update_sec = -1; 1109 1110 if (!oldbits) 1111 hpet_rtc_timer_init(); 1112 1113 return 1; 1114 } 1115 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); 1116 1117 int hpet_set_alarm_time(unsigned char hrs, unsigned char min, 1118 unsigned char sec) 1119 { 1120 if (!is_hpet_enabled()) 1121 return 0; 1122 1123 hpet_alarm_time.tm_hour = hrs; 1124 hpet_alarm_time.tm_min = min; 1125 hpet_alarm_time.tm_sec = sec; 1126 1127 return 1; 1128 } 1129 EXPORT_SYMBOL_GPL(hpet_set_alarm_time); 1130 1131 int hpet_set_periodic_freq(unsigned long freq) 1132 { 1133 uint64_t clc; 1134 1135 if (!is_hpet_enabled()) 1136 return 0; 1137 1138 if (freq <= DEFAULT_RTC_INT_FREQ) 1139 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; 1140 else { 1141 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1142 do_div(clc, freq); 1143 clc >>= hpet_clockevent.shift; 1144 hpet_pie_delta = clc; 1145 hpet_pie_limit = 0; 1146 } 1147 return 1; 1148 } 1149 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); 1150 1151 int hpet_rtc_dropped_irq(void) 1152 { 1153 return is_hpet_enabled(); 1154 } 1155 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); 1156 1157 static void hpet_rtc_timer_reinit(void) 1158 { 1159 unsigned int delta; 1160 int lost_ints = -1; 1161 1162 if (unlikely(!hpet_rtc_flags)) 1163 hpet_disable_rtc_channel(); 1164 1165 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1166 delta = hpet_default_delta; 1167 else 1168 delta = hpet_pie_delta; 1169 1170 /* 1171 * Increment the comparator value until we are ahead of the 1172 * current count. 1173 */ 1174 do { 1175 hpet_t1_cmp += delta; 1176 hpet_writel(hpet_t1_cmp, HPET_T1_CMP); 1177 lost_ints++; 1178 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); 1179 1180 if (lost_ints) { 1181 if (hpet_rtc_flags & RTC_PIE) 1182 hpet_pie_count += lost_ints; 1183 if (printk_ratelimit()) 1184 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", 1185 lost_ints); 1186 } 1187 } 1188 1189 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) 1190 { 1191 struct rtc_time curr_time; 1192 unsigned long rtc_int_flag = 0; 1193 1194 hpet_rtc_timer_reinit(); 1195 memset(&curr_time, 0, sizeof(struct rtc_time)); 1196 1197 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) 1198 get_rtc_time(&curr_time); 1199 1200 if (hpet_rtc_flags & RTC_UIE && 1201 curr_time.tm_sec != hpet_prev_update_sec) { 1202 if (hpet_prev_update_sec >= 0) 1203 rtc_int_flag = RTC_UF; 1204 hpet_prev_update_sec = curr_time.tm_sec; 1205 } 1206 1207 if (hpet_rtc_flags & RTC_PIE && 1208 ++hpet_pie_count >= hpet_pie_limit) { 1209 rtc_int_flag |= RTC_PF; 1210 hpet_pie_count = 0; 1211 } 1212 1213 if (hpet_rtc_flags & RTC_AIE && 1214 (curr_time.tm_sec == hpet_alarm_time.tm_sec) && 1215 (curr_time.tm_min == hpet_alarm_time.tm_min) && 1216 (curr_time.tm_hour == hpet_alarm_time.tm_hour)) 1217 rtc_int_flag |= RTC_AF; 1218 1219 if (rtc_int_flag) { 1220 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); 1221 if (irq_handler) 1222 irq_handler(rtc_int_flag, dev_id); 1223 } 1224 return IRQ_HANDLED; 1225 } 1226 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); 1227 #endif 1228