1 /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support. 2 * 3 * Copyright (C) 2001, 2002, 2003, 2007, 2008 David S. Miller (davem@davemloft.net) 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/types.h> 8 #include <linux/pci.h> 9 #include <linux/init.h> 10 #include <linux/slab.h> 11 #include <linux/interrupt.h> 12 #include <linux/of_device.h> 13 14 #include <asm/iommu.h> 15 #include <asm/irq.h> 16 #include <asm/pstate.h> 17 #include <asm/prom.h> 18 #include <asm/upa.h> 19 20 #include "pci_impl.h" 21 #include "iommu_common.h" 22 23 #define DRIVER_NAME "schizo" 24 #define PFX DRIVER_NAME ": " 25 26 /* This is a convention that at least Excalibur and Merlin 27 * follow. I suppose the SCHIZO used in Starcat and friends 28 * will do similar. 29 * 30 * The only way I could see this changing is if the newlink 31 * block requires more space in Schizo's address space than 32 * they predicted, thus requiring an address space reorg when 33 * the newer Schizo is taped out. 34 */ 35 36 /* Streaming buffer control register. */ 37 #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ 38 #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ 39 #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ 40 #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ 41 #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ 42 43 /* IOMMU control register. */ 44 #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ 45 #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ 46 #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ 47 #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ 48 #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ 49 #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ 50 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ 51 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ 52 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ 53 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ 54 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ 55 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ 56 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ 57 #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ 58 #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ 59 #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ 60 #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ 61 #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ 62 63 /* Schizo config space address format is nearly identical to 64 * that of PSYCHO: 65 * 66 * 32 24 23 16 15 11 10 8 7 2 1 0 67 * --------------------------------------------------------- 68 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 | 69 * --------------------------------------------------------- 70 */ 71 #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space) 72 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \ 73 (((unsigned long)(BUS) << 16) | \ 74 ((unsigned long)(DEVFN) << 8) | \ 75 ((unsigned long)(REG))) 76 77 static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm, 78 unsigned char bus, 79 unsigned int devfn, 80 int where) 81 { 82 if (!pbm) 83 return NULL; 84 bus -= pbm->pci_first_busno; 85 return (void *) 86 (SCHIZO_CONFIG_BASE(pbm) | 87 SCHIZO_CONFIG_ENCODE(bus, devfn, where)); 88 } 89 90 /* SCHIZO error handling support. */ 91 enum schizo_error_type { 92 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR 93 }; 94 95 static DEFINE_SPINLOCK(stc_buf_lock); 96 static unsigned long stc_error_buf[128]; 97 static unsigned long stc_tag_buf[16]; 98 static unsigned long stc_line_buf[16]; 99 100 #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */ 101 #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */ 102 #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */ 103 #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */ 104 #define SCHIZO_SERR_INO 0x34 /* Safari interface error */ 105 106 #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */ 107 #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */ 108 #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */ 109 110 #define SCHIZO_STCERR_WRITE 0x2UL 111 #define SCHIZO_STCERR_READ 0x1UL 112 113 #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL 114 #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL 115 #define SCHIZO_STCTAG_VALID 0x8000000000000000UL 116 #define SCHIZO_STCTAG_READ 0x4000000000000000UL 117 118 #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL 119 #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL 120 #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL 121 #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL 122 #define SCHIZO_STCLINE_VALID 0x0000000000600000UL 123 #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL 124 125 static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm, 126 enum schizo_error_type type) 127 { 128 struct strbuf *strbuf = &pbm->stc; 129 unsigned long regbase = pbm->pbm_regs; 130 unsigned long err_base, tag_base, line_base; 131 u64 control; 132 int i; 133 134 err_base = regbase + SCHIZO_STC_ERR; 135 tag_base = regbase + SCHIZO_STC_TAG; 136 line_base = regbase + SCHIZO_STC_LINE; 137 138 spin_lock(&stc_buf_lock); 139 140 /* This is __REALLY__ dangerous. When we put the 141 * streaming buffer into diagnostic mode to probe 142 * it's tags and error status, we _must_ clear all 143 * of the line tag valid bits before re-enabling 144 * the streaming buffer. If any dirty data lives 145 * in the STC when we do this, we will end up 146 * invalidating it before it has a chance to reach 147 * main memory. 148 */ 149 control = upa_readq(strbuf->strbuf_control); 150 upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB), 151 strbuf->strbuf_control); 152 for (i = 0; i < 128; i++) { 153 unsigned long val; 154 155 val = upa_readq(err_base + (i * 8UL)); 156 upa_writeq(0UL, err_base + (i * 8UL)); 157 stc_error_buf[i] = val; 158 } 159 for (i = 0; i < 16; i++) { 160 stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL)); 161 stc_line_buf[i] = upa_readq(line_base + (i * 8UL)); 162 upa_writeq(0UL, tag_base + (i * 8UL)); 163 upa_writeq(0UL, line_base + (i * 8UL)); 164 } 165 166 /* OK, state is logged, exit diagnostic mode. */ 167 upa_writeq(control, strbuf->strbuf_control); 168 169 for (i = 0; i < 16; i++) { 170 int j, saw_error, first, last; 171 172 saw_error = 0; 173 first = i * 8; 174 last = first + 8; 175 for (j = first; j < last; j++) { 176 unsigned long errval = stc_error_buf[j]; 177 if (errval != 0) { 178 saw_error++; 179 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n", 180 pbm->name, 181 j, 182 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0, 183 (errval & SCHIZO_STCERR_READ) ? 1 : 0); 184 } 185 } 186 if (saw_error != 0) { 187 unsigned long tagval = stc_tag_buf[i]; 188 unsigned long lineval = stc_line_buf[i]; 189 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n", 190 pbm->name, 191 i, 192 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL), 193 (tagval & SCHIZO_STCTAG_VPN), 194 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0), 195 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0)); 196 197 /* XXX Should spit out per-bank error information... -DaveM */ 198 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)" 199 "V(%d)FOFN(%d)]\n", 200 pbm->name, 201 i, 202 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL), 203 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL), 204 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL), 205 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL), 206 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0), 207 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0)); 208 } 209 } 210 211 spin_unlock(&stc_buf_lock); 212 } 213 214 /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous 215 * controller level errors. 216 */ 217 218 #define SCHIZO_IOMMU_TAG 0xa580UL 219 #define SCHIZO_IOMMU_DATA 0xa600UL 220 221 #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL 222 #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL 223 #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL 224 #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL 225 #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL 226 #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL 227 #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL 228 229 #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL 230 #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL 231 #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL 232 233 static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm, 234 enum schizo_error_type type) 235 { 236 struct iommu *iommu = pbm->iommu; 237 unsigned long iommu_tag[16]; 238 unsigned long iommu_data[16]; 239 unsigned long flags; 240 u64 control; 241 int i; 242 243 spin_lock_irqsave(&iommu->lock, flags); 244 control = upa_readq(iommu->iommu_control); 245 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) { 246 unsigned long base; 247 char *type_string; 248 249 /* Clear the error encountered bit. */ 250 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR; 251 upa_writeq(control, iommu->iommu_control); 252 253 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) { 254 case 0: 255 type_string = "Protection Error"; 256 break; 257 case 1: 258 type_string = "Invalid Error"; 259 break; 260 case 2: 261 type_string = "TimeOut Error"; 262 break; 263 case 3: 264 default: 265 type_string = "ECC Error"; 266 break; 267 }; 268 printk("%s: IOMMU Error, type[%s]\n", 269 pbm->name, type_string); 270 271 /* Put the IOMMU into diagnostic mode and probe 272 * it's TLB for entries with error status. 273 * 274 * It is very possible for another DVMA to occur 275 * while we do this probe, and corrupt the system 276 * further. But we are so screwed at this point 277 * that we are likely to crash hard anyways, so 278 * get as much diagnostic information to the 279 * console as we can. 280 */ 281 upa_writeq(control | SCHIZO_IOMMU_CTRL_DENAB, 282 iommu->iommu_control); 283 284 base = pbm->pbm_regs; 285 286 for (i = 0; i < 16; i++) { 287 iommu_tag[i] = 288 upa_readq(base + SCHIZO_IOMMU_TAG + (i * 8UL)); 289 iommu_data[i] = 290 upa_readq(base + SCHIZO_IOMMU_DATA + (i * 8UL)); 291 292 /* Now clear out the entry. */ 293 upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL)); 294 upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL)); 295 } 296 297 /* Leave diagnostic mode. */ 298 upa_writeq(control, iommu->iommu_control); 299 300 for (i = 0; i < 16; i++) { 301 unsigned long tag, data; 302 303 tag = iommu_tag[i]; 304 if (!(tag & SCHIZO_IOMMU_TAG_ERR)) 305 continue; 306 307 data = iommu_data[i]; 308 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) { 309 case 0: 310 type_string = "Protection Error"; 311 break; 312 case 1: 313 type_string = "Invalid Error"; 314 break; 315 case 2: 316 type_string = "TimeOut Error"; 317 break; 318 case 3: 319 default: 320 type_string = "ECC Error"; 321 break; 322 }; 323 printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) " 324 "sz(%dK) vpg(%08lx)]\n", 325 pbm->name, i, type_string, 326 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL), 327 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0), 328 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0), 329 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8), 330 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT); 331 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n", 332 pbm->name, i, 333 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0), 334 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0), 335 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT); 336 } 337 } 338 if (pbm->stc.strbuf_enabled) 339 __schizo_check_stc_error_pbm(pbm, type); 340 spin_unlock_irqrestore(&iommu->lock, flags); 341 } 342 343 static void schizo_check_iommu_error(struct pci_pbm_info *pbm, 344 enum schizo_error_type type) 345 { 346 schizo_check_iommu_error_pbm(pbm, type); 347 if (pbm->sibling) 348 schizo_check_iommu_error_pbm(pbm->sibling, type); 349 } 350 351 /* Uncorrectable ECC error status gathering. */ 352 #define SCHIZO_UE_AFSR 0x10030UL 353 #define SCHIZO_UE_AFAR 0x10038UL 354 355 #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */ 356 #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */ 357 #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */ 358 #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */ 359 #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */ 360 #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */ 361 #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */ 362 #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */ 363 #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */ 364 #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */ 365 #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */ 366 #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */ 367 #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */ 368 #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */ 369 370 static irqreturn_t schizo_ue_intr(int irq, void *dev_id) 371 { 372 struct pci_pbm_info *pbm = dev_id; 373 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR; 374 unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR; 375 unsigned long afsr, afar, error_bits; 376 int reported, limit; 377 378 /* Latch uncorrectable error status. */ 379 afar = upa_readq(afar_reg); 380 381 /* If either of the error pending bits are set in the 382 * AFSR, the error status is being actively updated by 383 * the hardware and we must re-read to get a clean value. 384 */ 385 limit = 1000; 386 do { 387 afsr = upa_readq(afsr_reg); 388 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); 389 390 /* Clear the primary/secondary error status bits. */ 391 error_bits = afsr & 392 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR | 393 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA); 394 if (!error_bits) 395 return IRQ_NONE; 396 upa_writeq(error_bits, afsr_reg); 397 398 /* Log the error. */ 399 printk("%s: Uncorrectable Error, primary error type[%s]\n", 400 pbm->name, 401 (((error_bits & SCHIZO_UEAFSR_PPIO) ? 402 "PIO" : 403 ((error_bits & SCHIZO_UEAFSR_PDRD) ? 404 "DMA Read" : 405 ((error_bits & SCHIZO_UEAFSR_PDWR) ? 406 "DMA Write" : "???"))))); 407 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", 408 pbm->name, 409 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, 410 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, 411 (afsr & SCHIZO_UEAFSR_AID) >> 24UL); 412 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", 413 pbm->name, 414 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, 415 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, 416 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, 417 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, 418 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); 419 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); 420 printk("%s: UE Secondary errors [", pbm->name); 421 reported = 0; 422 if (afsr & SCHIZO_UEAFSR_SPIO) { 423 reported++; 424 printk("(PIO)"); 425 } 426 if (afsr & SCHIZO_UEAFSR_SDMA) { 427 reported++; 428 printk("(DMA)"); 429 } 430 if (!reported) 431 printk("(none)"); 432 printk("]\n"); 433 434 /* Interrogate IOMMU for error status. */ 435 schizo_check_iommu_error(pbm, UE_ERR); 436 437 return IRQ_HANDLED; 438 } 439 440 #define SCHIZO_CE_AFSR 0x10040UL 441 #define SCHIZO_CE_AFAR 0x10048UL 442 443 #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL 444 #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL 445 #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL 446 #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL 447 #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL 448 #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL 449 #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL 450 #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL 451 #define SCHIZO_CEAFSR_AID 0x000000001f000000UL 452 #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL 453 #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL 454 #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL 455 #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL 456 #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL 457 458 static irqreturn_t schizo_ce_intr(int irq, void *dev_id) 459 { 460 struct pci_pbm_info *pbm = dev_id; 461 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR; 462 unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR; 463 unsigned long afsr, afar, error_bits; 464 int reported, limit; 465 466 /* Latch error status. */ 467 afar = upa_readq(afar_reg); 468 469 /* If either of the error pending bits are set in the 470 * AFSR, the error status is being actively updated by 471 * the hardware and we must re-read to get a clean value. 472 */ 473 limit = 1000; 474 do { 475 afsr = upa_readq(afsr_reg); 476 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); 477 478 /* Clear primary/secondary error status bits. */ 479 error_bits = afsr & 480 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR | 481 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA); 482 if (!error_bits) 483 return IRQ_NONE; 484 upa_writeq(error_bits, afsr_reg); 485 486 /* Log the error. */ 487 printk("%s: Correctable Error, primary error type[%s]\n", 488 pbm->name, 489 (((error_bits & SCHIZO_CEAFSR_PPIO) ? 490 "PIO" : 491 ((error_bits & SCHIZO_CEAFSR_PDRD) ? 492 "DMA Read" : 493 ((error_bits & SCHIZO_CEAFSR_PDWR) ? 494 "DMA Write" : "???"))))); 495 496 /* XXX Use syndrome and afar to print out module string just like 497 * XXX UDB CE trap handler does... -DaveM 498 */ 499 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", 500 pbm->name, 501 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, 502 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, 503 (afsr & SCHIZO_UEAFSR_AID) >> 24UL); 504 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", 505 pbm->name, 506 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, 507 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, 508 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, 509 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, 510 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); 511 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); 512 printk("%s: CE Secondary errors [", pbm->name); 513 reported = 0; 514 if (afsr & SCHIZO_CEAFSR_SPIO) { 515 reported++; 516 printk("(PIO)"); 517 } 518 if (afsr & SCHIZO_CEAFSR_SDMA) { 519 reported++; 520 printk("(DMA)"); 521 } 522 if (!reported) 523 printk("(none)"); 524 printk("]\n"); 525 526 return IRQ_HANDLED; 527 } 528 529 #define SCHIZO_PCI_AFSR 0x2010UL 530 #define SCHIZO_PCI_AFAR 0x2018UL 531 532 #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */ 533 #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */ 534 #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */ 535 #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */ 536 #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */ 537 #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */ 538 #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */ 539 #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */ 540 #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */ 541 #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */ 542 #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */ 543 #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */ 544 #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */ 545 #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */ 546 #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */ 547 #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */ 548 #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */ 549 550 #define SCHIZO_PCI_CTRL (0x2000UL) 551 #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */ 552 #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */ 553 #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */ 554 #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */ 555 #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */ 556 #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */ 557 #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */ 558 #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */ 559 #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */ 560 #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */ 561 #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */ 562 #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */ 563 #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */ 564 #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */ 565 #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */ 566 #define SCHIZO_PCICTRL_PTO_SHIFT 24UL 567 #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */ 568 #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */ 569 #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */ 570 #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */ 571 #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */ 572 #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */ 573 #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */ 574 #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */ 575 #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */ 576 #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */ 577 #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */ 578 579 static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm) 580 { 581 unsigned long csr_reg, csr, csr_error_bits; 582 irqreturn_t ret = IRQ_NONE; 583 u16 stat; 584 585 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL; 586 csr = upa_readq(csr_reg); 587 csr_error_bits = 588 csr & (SCHIZO_PCICTRL_BUS_UNUS | 589 SCHIZO_PCICTRL_TTO_ERR | 590 SCHIZO_PCICTRL_RTRY_ERR | 591 SCHIZO_PCICTRL_DTO_ERR | 592 SCHIZO_PCICTRL_SBH_ERR | 593 SCHIZO_PCICTRL_SERR); 594 if (csr_error_bits) { 595 /* Clear the errors. */ 596 upa_writeq(csr, csr_reg); 597 598 /* Log 'em. */ 599 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS) 600 printk("%s: Bus unusable error asserted.\n", 601 pbm->name); 602 if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR) 603 printk("%s: PCI TRDY# timeout error asserted.\n", 604 pbm->name); 605 if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR) 606 printk("%s: PCI excessive retry error asserted.\n", 607 pbm->name); 608 if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR) 609 printk("%s: PCI discard timeout error asserted.\n", 610 pbm->name); 611 if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR) 612 printk("%s: PCI streaming byte hole error asserted.\n", 613 pbm->name); 614 if (csr_error_bits & SCHIZO_PCICTRL_SERR) 615 printk("%s: PCI SERR signal asserted.\n", 616 pbm->name); 617 ret = IRQ_HANDLED; 618 } 619 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat); 620 if (stat & (PCI_STATUS_PARITY | 621 PCI_STATUS_SIG_TARGET_ABORT | 622 PCI_STATUS_REC_TARGET_ABORT | 623 PCI_STATUS_REC_MASTER_ABORT | 624 PCI_STATUS_SIG_SYSTEM_ERROR)) { 625 printk("%s: PCI bus error, PCI_STATUS[%04x]\n", 626 pbm->name, stat); 627 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff); 628 ret = IRQ_HANDLED; 629 } 630 return ret; 631 } 632 633 static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id) 634 { 635 struct pci_pbm_info *pbm = dev_id; 636 unsigned long afsr_reg, afar_reg, base; 637 unsigned long afsr, afar, error_bits; 638 int reported; 639 640 base = pbm->pbm_regs; 641 642 afsr_reg = base + SCHIZO_PCI_AFSR; 643 afar_reg = base + SCHIZO_PCI_AFAR; 644 645 /* Latch error status. */ 646 afar = upa_readq(afar_reg); 647 afsr = upa_readq(afsr_reg); 648 649 /* Clear primary/secondary error status bits. */ 650 error_bits = afsr & 651 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 652 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 653 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | 654 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 655 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 656 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS); 657 if (!error_bits) 658 return schizo_pcierr_intr_other(pbm); 659 upa_writeq(error_bits, afsr_reg); 660 661 /* Log the error. */ 662 printk("%s: PCI Error, primary error type[%s]\n", 663 pbm->name, 664 (((error_bits & SCHIZO_PCIAFSR_PMA) ? 665 "Master Abort" : 666 ((error_bits & SCHIZO_PCIAFSR_PTA) ? 667 "Target Abort" : 668 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ? 669 "Excessive Retries" : 670 ((error_bits & SCHIZO_PCIAFSR_PPERR) ? 671 "Parity Error" : 672 ((error_bits & SCHIZO_PCIAFSR_PTTO) ? 673 "Timeout" : 674 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ? 675 "Bus Unusable" : "???")))))))); 676 printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n", 677 pbm->name, 678 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL, 679 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0, 680 ((afsr & SCHIZO_PCIAFSR_CFG) ? 681 "Config" : 682 ((afsr & SCHIZO_PCIAFSR_MEM) ? 683 "Memory" : 684 ((afsr & SCHIZO_PCIAFSR_IO) ? 685 "I/O" : "???")))); 686 printk("%s: PCI AFAR [%016lx]\n", 687 pbm->name, afar); 688 printk("%s: PCI Secondary errors [", 689 pbm->name); 690 reported = 0; 691 if (afsr & SCHIZO_PCIAFSR_SMA) { 692 reported++; 693 printk("(Master Abort)"); 694 } 695 if (afsr & SCHIZO_PCIAFSR_STA) { 696 reported++; 697 printk("(Target Abort)"); 698 } 699 if (afsr & SCHIZO_PCIAFSR_SRTRY) { 700 reported++; 701 printk("(Excessive Retries)"); 702 } 703 if (afsr & SCHIZO_PCIAFSR_SPERR) { 704 reported++; 705 printk("(Parity Error)"); 706 } 707 if (afsr & SCHIZO_PCIAFSR_STTO) { 708 reported++; 709 printk("(Timeout)"); 710 } 711 if (afsr & SCHIZO_PCIAFSR_SUNUS) { 712 reported++; 713 printk("(Bus Unusable)"); 714 } 715 if (!reported) 716 printk("(none)"); 717 printk("]\n"); 718 719 /* For the error types shown, scan PBM's PCI bus for devices 720 * which have logged that error type. 721 */ 722 723 /* If we see a Target Abort, this could be the result of an 724 * IOMMU translation error of some sort. It is extremely 725 * useful to log this information as usually it indicates 726 * a bug in the IOMMU support code or a PCI device driver. 727 */ 728 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) { 729 schizo_check_iommu_error(pbm, PCI_ERR); 730 pci_scan_for_target_abort(pbm, pbm->pci_bus); 731 } 732 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA)) 733 pci_scan_for_master_abort(pbm, pbm->pci_bus); 734 735 /* For excessive retries, PSYCHO/PBM will abort the device 736 * and there is no way to specifically check for excessive 737 * retries in the config space status registers. So what 738 * we hope is that we'll catch it via the master/target 739 * abort events. 740 */ 741 742 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR)) 743 pci_scan_for_parity_error(pbm, pbm->pci_bus); 744 745 return IRQ_HANDLED; 746 } 747 748 #define SCHIZO_SAFARI_ERRLOG 0x10018UL 749 750 #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL 751 752 #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */ 753 #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */ 754 #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */ 755 #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */ 756 #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */ 757 #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */ 758 #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */ 759 #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */ 760 #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */ 761 #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */ 762 #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */ 763 #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */ 764 #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */ 765 #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */ 766 #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */ 767 #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */ 768 #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */ 769 #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */ 770 #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */ 771 #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */ 772 #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */ 773 #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */ 774 #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */ 775 #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */ 776 #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */ 777 #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */ 778 #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */ 779 #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */ 780 #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */ 781 #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */ 782 #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */ 783 784 /* We only expect UNMAP errors here. The rest of the Safari errors 785 * are marked fatal and thus cause a system reset. 786 */ 787 static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id) 788 { 789 struct pci_pbm_info *pbm = dev_id; 790 u64 errlog; 791 792 errlog = upa_readq(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG); 793 upa_writeq(errlog & ~(SAFARI_ERRLOG_ERROUT), 794 pbm->controller_regs + SCHIZO_SAFARI_ERRLOG); 795 796 if (!(errlog & BUS_ERROR_UNMAP)) { 797 printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016llx]\n", 798 pbm->name, errlog); 799 800 return IRQ_HANDLED; 801 } 802 803 printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n", 804 pbm->name); 805 schizo_check_iommu_error(pbm, SAFARI_ERR); 806 807 return IRQ_HANDLED; 808 } 809 810 /* Nearly identical to PSYCHO equivalents... */ 811 #define SCHIZO_ECC_CTRL 0x10020UL 812 #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ 813 #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ 814 #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ 815 816 #define SCHIZO_SAFARI_ERRCTRL 0x10008UL 817 #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL 818 #define SCHIZO_SAFARI_IRQCTRL 0x10010UL 819 #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL 820 821 static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino) 822 { 823 ino &= IMAP_INO; 824 825 if (pbm->ino_bitmap & (1UL << ino)) 826 return 1; 827 828 return 0; 829 } 830 831 /* How the Tomatillo IRQs are routed around is pure guesswork here. 832 * 833 * All the Tomatillo devices I see in prtconf dumps seem to have only 834 * a single PCI bus unit attached to it. It would seem they are separate 835 * devices because their PortID (ie. JBUS ID) values are all different 836 * and thus the registers are mapped to totally different locations. 837 * 838 * However, two Tomatillo's look "similar" in that the only difference 839 * in their PortID is the lowest bit. 840 * 841 * So if we were to ignore this lower bit, it certainly looks like two 842 * PCI bus units of the same Tomatillo. I still have not really 843 * figured this out... 844 */ 845 static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm) 846 { 847 struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); 848 u64 tmp, err_mask, err_no_mask; 849 int err; 850 851 /* Tomatillo IRQ property layout is: 852 * 0: PCIERR 853 * 1: UE ERR 854 * 2: CE ERR 855 * 3: SERR 856 * 4: POWER FAIL? 857 */ 858 859 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) { 860 err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0, 861 "TOMATILLO_UE", pbm); 862 if (err) 863 printk(KERN_WARNING "%s: Could not register UE, " 864 "err=%d\n", pbm->name, err); 865 } 866 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) { 867 err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0, 868 "TOMATILLO_CE", pbm); 869 if (err) 870 printk(KERN_WARNING "%s: Could not register CE, " 871 "err=%d\n", pbm->name, err); 872 } 873 err = 0; 874 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) { 875 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 876 "TOMATILLO_PCIERR", pbm); 877 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) { 878 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 879 "TOMATILLO_PCIERR", pbm); 880 } 881 if (err) 882 printk(KERN_WARNING "%s: Could not register PCIERR, " 883 "err=%d\n", pbm->name, err); 884 885 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) { 886 err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0, 887 "TOMATILLO_SERR", pbm); 888 if (err) 889 printk(KERN_WARNING "%s: Could not register SERR, " 890 "err=%d\n", pbm->name, err); 891 } 892 893 /* Enable UE and CE interrupts for controller. */ 894 upa_writeq((SCHIZO_ECCCTRL_EE | 895 SCHIZO_ECCCTRL_UE | 896 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL); 897 898 /* Enable PCI Error interrupts and clear error 899 * bits. 900 */ 901 err_mask = (SCHIZO_PCICTRL_BUS_UNUS | 902 SCHIZO_PCICTRL_TTO_ERR | 903 SCHIZO_PCICTRL_RTRY_ERR | 904 SCHIZO_PCICTRL_SERR | 905 SCHIZO_PCICTRL_EEN); 906 907 err_no_mask = SCHIZO_PCICTRL_DTO_ERR; 908 909 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); 910 tmp |= err_mask; 911 tmp &= ~err_no_mask; 912 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); 913 914 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 915 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 916 SCHIZO_PCIAFSR_PTTO | 917 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 918 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 919 SCHIZO_PCIAFSR_STTO); 920 921 upa_writeq(err_mask, pbm->pbm_regs + SCHIZO_PCI_AFSR); 922 923 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR | 924 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD | 925 BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA | 926 BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO | 927 BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR | 928 BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B | 929 BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR | 930 BUS_ERROR_APERR | BUS_ERROR_UNMAP | 931 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT); 932 933 upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask), 934 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL); 935 936 upa_writeq((SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)), 937 pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL); 938 } 939 940 static void schizo_register_error_handlers(struct pci_pbm_info *pbm) 941 { 942 struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); 943 u64 tmp, err_mask, err_no_mask; 944 int err; 945 946 /* Schizo IRQ property layout is: 947 * 0: PCIERR 948 * 1: UE ERR 949 * 2: CE ERR 950 * 3: SERR 951 * 4: POWER FAIL? 952 */ 953 954 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) { 955 err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0, 956 "SCHIZO_UE", pbm); 957 if (err) 958 printk(KERN_WARNING "%s: Could not register UE, " 959 "err=%d\n", pbm->name, err); 960 } 961 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) { 962 err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0, 963 "SCHIZO_CE", pbm); 964 if (err) 965 printk(KERN_WARNING "%s: Could not register CE, " 966 "err=%d\n", pbm->name, err); 967 } 968 err = 0; 969 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) { 970 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 971 "SCHIZO_PCIERR", pbm); 972 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) { 973 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 974 "SCHIZO_PCIERR", pbm); 975 } 976 if (err) 977 printk(KERN_WARNING "%s: Could not register PCIERR, " 978 "err=%d\n", pbm->name, err); 979 980 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) { 981 err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0, 982 "SCHIZO_SERR", pbm); 983 if (err) 984 printk(KERN_WARNING "%s: Could not register SERR, " 985 "err=%d\n", pbm->name, err); 986 } 987 988 /* Enable UE and CE interrupts for controller. */ 989 upa_writeq((SCHIZO_ECCCTRL_EE | 990 SCHIZO_ECCCTRL_UE | 991 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL); 992 993 err_mask = (SCHIZO_PCICTRL_BUS_UNUS | 994 SCHIZO_PCICTRL_ESLCK | 995 SCHIZO_PCICTRL_TTO_ERR | 996 SCHIZO_PCICTRL_RTRY_ERR | 997 SCHIZO_PCICTRL_SBH_ERR | 998 SCHIZO_PCICTRL_SERR | 999 SCHIZO_PCICTRL_EEN); 1000 1001 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR | 1002 SCHIZO_PCICTRL_SBH_INT); 1003 1004 /* Enable PCI Error interrupts and clear error 1005 * bits for each PBM. 1006 */ 1007 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); 1008 tmp |= err_mask; 1009 tmp &= ~err_no_mask; 1010 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); 1011 1012 upa_writeq((SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 1013 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 1014 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | 1015 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 1016 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 1017 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS), 1018 pbm->pbm_regs + SCHIZO_PCI_AFSR); 1019 1020 /* Make all Safari error conditions fatal except unmapped 1021 * errors which we make generate interrupts. 1022 */ 1023 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS | 1024 BUS_ERROR_BADMA | BUS_ERROR_BADMB | 1025 BUS_ERROR_BADMC | 1026 BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | 1027 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB | 1028 BUS_ERROR_CIQTO | 1029 BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO | 1030 BUS_ERROR_UFPQTO | BUS_ERROR_APERR | 1031 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT | 1032 BUS_ERROR_ILL); 1033 #if 1 1034 /* XXX Something wrong with some Excalibur systems 1035 * XXX Sun is shipping. The behavior on a 2-cpu 1036 * XXX machine is that both CPU1 parity error bits 1037 * XXX are set and are immediately set again when 1038 * XXX their error status bits are cleared. Just 1039 * XXX ignore them for now. -DaveM 1040 */ 1041 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | 1042 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB); 1043 #endif 1044 1045 upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask), 1046 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL); 1047 } 1048 1049 static void pbm_config_busmastering(struct pci_pbm_info *pbm) 1050 { 1051 u8 *addr; 1052 1053 /* Set cache-line size to 64 bytes, this is actually 1054 * a nop but I do it for completeness. 1055 */ 1056 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, 1057 0, PCI_CACHE_LINE_SIZE); 1058 pci_config_write8(addr, 64 / sizeof(u32)); 1059 1060 /* Set PBM latency timer to 64 PCI clocks. */ 1061 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, 1062 0, PCI_LATENCY_TIMER); 1063 pci_config_write8(addr, 64); 1064 } 1065 1066 static void __devinit schizo_scan_bus(struct pci_pbm_info *pbm, 1067 struct device *parent) 1068 { 1069 pbm_config_busmastering(pbm); 1070 pbm->is_66mhz_capable = 1071 (of_find_property(pbm->op->dev.of_node, "66mhz-capable", NULL) 1072 != NULL); 1073 1074 pbm->pci_bus = pci_scan_one_pbm(pbm, parent); 1075 1076 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) 1077 tomatillo_register_error_handlers(pbm); 1078 else 1079 schizo_register_error_handlers(pbm); 1080 } 1081 1082 #define SCHIZO_STRBUF_CONTROL (0x02800UL) 1083 #define SCHIZO_STRBUF_FLUSH (0x02808UL) 1084 #define SCHIZO_STRBUF_FSYNC (0x02810UL) 1085 #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL) 1086 #define SCHIZO_STRBUF_CTXMATCH (0x10000UL) 1087 1088 static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm) 1089 { 1090 unsigned long base = pbm->pbm_regs; 1091 u64 control; 1092 1093 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1094 /* TOMATILLO lacks streaming cache. */ 1095 return; 1096 } 1097 1098 /* SCHIZO has context flushing. */ 1099 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL; 1100 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH; 1101 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC; 1102 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH; 1103 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH; 1104 1105 pbm->stc.strbuf_flushflag = (volatile unsigned long *) 1106 ((((unsigned long)&pbm->stc.__flushflag_buf[0]) 1107 + 63UL) 1108 & ~63UL); 1109 pbm->stc.strbuf_flushflag_pa = (unsigned long) 1110 __pa(pbm->stc.strbuf_flushflag); 1111 1112 /* Turn off LRU locking and diag mode, enable the 1113 * streaming buffer and leave the rerun-disable 1114 * setting however OBP set it. 1115 */ 1116 control = upa_readq(pbm->stc.strbuf_control); 1117 control &= ~(SCHIZO_STRBUF_CTRL_LPTR | 1118 SCHIZO_STRBUF_CTRL_LENAB | 1119 SCHIZO_STRBUF_CTRL_DENAB); 1120 control |= SCHIZO_STRBUF_CTRL_ENAB; 1121 upa_writeq(control, pbm->stc.strbuf_control); 1122 1123 pbm->stc.strbuf_enabled = 1; 1124 } 1125 1126 #define SCHIZO_IOMMU_CONTROL (0x00200UL) 1127 #define SCHIZO_IOMMU_TSBBASE (0x00208UL) 1128 #define SCHIZO_IOMMU_FLUSH (0x00210UL) 1129 #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL) 1130 1131 static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm) 1132 { 1133 static const u32 vdma_default[] = { 0xc0000000, 0x40000000 }; 1134 unsigned long i, tagbase, database; 1135 struct iommu *iommu = pbm->iommu; 1136 int tsbsize, err; 1137 const u32 *vdma; 1138 u32 dma_mask; 1139 u64 control; 1140 1141 vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL); 1142 if (!vdma) 1143 vdma = vdma_default; 1144 1145 dma_mask = vdma[0]; 1146 switch (vdma[1]) { 1147 case 0x20000000: 1148 dma_mask |= 0x1fffffff; 1149 tsbsize = 64; 1150 break; 1151 1152 case 0x40000000: 1153 dma_mask |= 0x3fffffff; 1154 tsbsize = 128; 1155 break; 1156 1157 case 0x80000000: 1158 dma_mask |= 0x7fffffff; 1159 tsbsize = 128; 1160 break; 1161 1162 default: 1163 printk(KERN_ERR PFX "Strange virtual-dma size.\n"); 1164 return -EINVAL; 1165 } 1166 1167 /* Register addresses, SCHIZO has iommu ctx flushing. */ 1168 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL; 1169 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE; 1170 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH; 1171 iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL); 1172 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH; 1173 1174 /* We use the main control/status register of SCHIZO as the write 1175 * completion register. 1176 */ 1177 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL; 1178 1179 /* 1180 * Invalidate TLB Entries. 1181 */ 1182 control = upa_readq(iommu->iommu_control); 1183 control |= SCHIZO_IOMMU_CTRL_DENAB; 1184 upa_writeq(control, iommu->iommu_control); 1185 1186 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA; 1187 1188 for (i = 0; i < 16; i++) { 1189 upa_writeq(0, pbm->pbm_regs + tagbase + (i * 8UL)); 1190 upa_writeq(0, pbm->pbm_regs + database + (i * 8UL)); 1191 } 1192 1193 /* Leave diag mode enabled for full-flushing done 1194 * in pci_iommu.c 1195 */ 1196 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask, 1197 pbm->numa_node); 1198 if (err) { 1199 printk(KERN_ERR PFX "iommu_table_init() fails with %d\n", err); 1200 return err; 1201 } 1202 1203 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase); 1204 1205 control = upa_readq(iommu->iommu_control); 1206 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ); 1207 switch (tsbsize) { 1208 case 64: 1209 control |= SCHIZO_IOMMU_TSBSZ_64K; 1210 break; 1211 case 128: 1212 control |= SCHIZO_IOMMU_TSBSZ_128K; 1213 break; 1214 } 1215 1216 control |= SCHIZO_IOMMU_CTRL_ENAB; 1217 upa_writeq(control, iommu->iommu_control); 1218 1219 return 0; 1220 } 1221 1222 #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL) 1223 #define SCHIZO_IRQ_RETRY_INF 0xffUL 1224 1225 #define SCHIZO_PCI_DIAG (0x2020UL) 1226 #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */ 1227 #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */ 1228 #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */ 1229 #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */ 1230 #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */ 1231 #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */ 1232 #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */ 1233 #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */ 1234 #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */ 1235 1236 #define TOMATILLO_PCI_IOC_CSR (0x2248UL) 1237 #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL 1238 #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL 1239 #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL 1240 #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL 1241 #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL 1242 #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL 1243 #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL 1244 #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL 1245 #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL 1246 #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL 1247 #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL 1248 #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL 1249 #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL 1250 #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL 1251 #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL 1252 1253 #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL) 1254 #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL) 1255 1256 static void schizo_pbm_hw_init(struct pci_pbm_info *pbm) 1257 { 1258 u64 tmp; 1259 1260 upa_writeq(5, pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY); 1261 1262 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); 1263 1264 /* Enable arbiter for all PCI slots. */ 1265 tmp |= 0xff; 1266 1267 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && 1268 pbm->chip_version >= 0x2) 1269 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT; 1270 1271 if (!of_find_property(pbm->op->dev.of_node, "no-bus-parking", NULL)) 1272 tmp |= SCHIZO_PCICTRL_PARK; 1273 else 1274 tmp &= ~SCHIZO_PCICTRL_PARK; 1275 1276 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && 1277 pbm->chip_version <= 0x1) 1278 tmp |= SCHIZO_PCICTRL_DTO_INT; 1279 else 1280 tmp &= ~SCHIZO_PCICTRL_DTO_INT; 1281 1282 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) 1283 tmp |= (SCHIZO_PCICTRL_MRM_PREF | 1284 SCHIZO_PCICTRL_RDO_PREF | 1285 SCHIZO_PCICTRL_RDL_PREF); 1286 1287 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); 1288 1289 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_DIAG); 1290 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB | 1291 SCHIZO_PCIDIAG_D_RETRY | 1292 SCHIZO_PCIDIAG_D_INTSYNC); 1293 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_DIAG); 1294 1295 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1296 /* Clear prefetch lengths to workaround a bug in 1297 * Jalapeno... 1298 */ 1299 tmp = (TOMATILLO_IOC_PART_WPENAB | 1300 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) | 1301 TOMATILLO_IOC_RDMULT_CPENAB | 1302 TOMATILLO_IOC_RDONE_CPENAB | 1303 TOMATILLO_IOC_RDLINE_CPENAB); 1304 1305 upa_writeq(tmp, pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR); 1306 } 1307 } 1308 1309 static int __devinit schizo_pbm_init(struct pci_pbm_info *pbm, 1310 struct platform_device *op, u32 portid, 1311 int chip_type) 1312 { 1313 const struct linux_prom64_registers *regs; 1314 struct device_node *dp = op->dev.of_node; 1315 const char *chipset_name; 1316 int is_pbm_a, err; 1317 1318 switch (chip_type) { 1319 case PBM_CHIP_TYPE_TOMATILLO: 1320 chipset_name = "TOMATILLO"; 1321 break; 1322 1323 case PBM_CHIP_TYPE_SCHIZO_PLUS: 1324 chipset_name = "SCHIZO+"; 1325 break; 1326 1327 case PBM_CHIP_TYPE_SCHIZO: 1328 default: 1329 chipset_name = "SCHIZO"; 1330 break; 1331 }; 1332 1333 /* For SCHIZO, three OBP regs: 1334 * 1) PBM controller regs 1335 * 2) Schizo front-end controller regs (same for both PBMs) 1336 * 3) PBM PCI config space 1337 * 1338 * For TOMATILLO, four OBP regs: 1339 * 1) PBM controller regs 1340 * 2) Tomatillo front-end controller regs 1341 * 3) PBM PCI config space 1342 * 4) Ichip regs 1343 */ 1344 regs = of_get_property(dp, "reg", NULL); 1345 1346 is_pbm_a = ((regs[0].phys_addr & 0x00700000) == 0x00600000); 1347 1348 pbm->next = pci_pbm_root; 1349 pci_pbm_root = pbm; 1350 1351 pbm->numa_node = -1; 1352 1353 pbm->pci_ops = &sun4u_pci_ops; 1354 pbm->config_space_reg_bits = 8; 1355 1356 pbm->index = pci_num_pbms++; 1357 1358 pbm->portid = portid; 1359 pbm->op = op; 1360 1361 pbm->chip_type = chip_type; 1362 pbm->chip_version = of_getintprop_default(dp, "version#", 0); 1363 pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0); 1364 1365 pbm->pbm_regs = regs[0].phys_addr; 1366 pbm->controller_regs = regs[1].phys_addr - 0x10000UL; 1367 1368 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) 1369 pbm->sync_reg = regs[3].phys_addr + 0x1a18UL; 1370 1371 pbm->name = dp->full_name; 1372 1373 printk("%s: %s PCI Bus Module ver[%x:%x]\n", 1374 pbm->name, chipset_name, 1375 pbm->chip_version, pbm->chip_revision); 1376 1377 schizo_pbm_hw_init(pbm); 1378 1379 pci_determine_mem_io_space(pbm); 1380 1381 pci_get_pbm_props(pbm); 1382 1383 err = schizo_pbm_iommu_init(pbm); 1384 if (err) 1385 return err; 1386 1387 schizo_pbm_strbuf_init(pbm); 1388 1389 schizo_scan_bus(pbm, &op->dev); 1390 1391 return 0; 1392 } 1393 1394 static inline int portid_compare(u32 x, u32 y, int chip_type) 1395 { 1396 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1397 if (x == (y ^ 1)) 1398 return 1; 1399 return 0; 1400 } 1401 return (x == y); 1402 } 1403 1404 static struct pci_pbm_info * __devinit schizo_find_sibling(u32 portid, 1405 int chip_type) 1406 { 1407 struct pci_pbm_info *pbm; 1408 1409 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { 1410 if (portid_compare(pbm->portid, portid, chip_type)) 1411 return pbm; 1412 } 1413 return NULL; 1414 } 1415 1416 static int __devinit __schizo_init(struct platform_device *op, unsigned long chip_type) 1417 { 1418 struct device_node *dp = op->dev.of_node; 1419 struct pci_pbm_info *pbm; 1420 struct iommu *iommu; 1421 u32 portid; 1422 int err; 1423 1424 portid = of_getintprop_default(dp, "portid", 0xff); 1425 1426 err = -ENOMEM; 1427 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); 1428 if (!pbm) { 1429 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n"); 1430 goto out_err; 1431 } 1432 1433 pbm->sibling = schizo_find_sibling(portid, chip_type); 1434 1435 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); 1436 if (!iommu) { 1437 printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n"); 1438 goto out_free_pbm; 1439 } 1440 1441 pbm->iommu = iommu; 1442 1443 if (schizo_pbm_init(pbm, op, portid, chip_type)) 1444 goto out_free_iommu; 1445 1446 if (pbm->sibling) 1447 pbm->sibling->sibling = pbm; 1448 1449 dev_set_drvdata(&op->dev, pbm); 1450 1451 return 0; 1452 1453 out_free_iommu: 1454 kfree(pbm->iommu); 1455 1456 out_free_pbm: 1457 kfree(pbm); 1458 1459 out_err: 1460 return err; 1461 } 1462 1463 static int __devinit schizo_probe(struct platform_device *op, 1464 const struct of_device_id *match) 1465 { 1466 return __schizo_init(op, (unsigned long) match->data); 1467 } 1468 1469 /* The ordering of this table is very important. Some Tomatillo 1470 * nodes announce that they are compatible with both pci108e,a801 1471 * and pci108e,8001. So list the chips in reverse chronological 1472 * order. 1473 */ 1474 static struct of_device_id __initdata schizo_match[] = { 1475 { 1476 .name = "pci", 1477 .compatible = "pci108e,a801", 1478 .data = (void *) PBM_CHIP_TYPE_TOMATILLO, 1479 }, 1480 { 1481 .name = "pci", 1482 .compatible = "pci108e,8002", 1483 .data = (void *) PBM_CHIP_TYPE_SCHIZO_PLUS, 1484 }, 1485 { 1486 .name = "pci", 1487 .compatible = "pci108e,8001", 1488 .data = (void *) PBM_CHIP_TYPE_SCHIZO, 1489 }, 1490 {}, 1491 }; 1492 1493 static struct of_platform_driver schizo_driver = { 1494 .driver = { 1495 .name = DRIVER_NAME, 1496 .owner = THIS_MODULE, 1497 .of_match_table = schizo_match, 1498 }, 1499 .probe = schizo_probe, 1500 }; 1501 1502 static int __init schizo_init(void) 1503 { 1504 return of_register_platform_driver(&schizo_driver); 1505 } 1506 1507 subsys_initcall(schizo_init); 1508