1 /* 2 * SH7723 Setup 3 * 4 * Copyright (C) 2008 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/mm.h> 14 #include <linux/serial_sci.h> 15 #include <linux/uio_driver.h> 16 #include <linux/usb/r8a66597.h> 17 #include <linux/sh_timer.h> 18 #include <linux/sh_intc.h> 19 #include <linux/io.h> 20 #include <asm/clock.h> 21 #include <asm/mmzone.h> 22 #include <cpu/sh7723.h> 23 24 /* Serial */ 25 static struct plat_sci_port scif0_platform_data = { 26 .scscr = SCSCR_REIE, 27 .type = PORT_SCIF, 28 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 29 }; 30 31 static struct resource scif0_resources[] = { 32 DEFINE_RES_MEM(0xffe00000, 0x100), 33 DEFINE_RES_IRQ(evt2irq(0xc00)), 34 }; 35 36 static struct platform_device scif0_device = { 37 .name = "sh-sci", 38 .id = 0, 39 .resource = scif0_resources, 40 .num_resources = ARRAY_SIZE(scif0_resources), 41 .dev = { 42 .platform_data = &scif0_platform_data, 43 }, 44 }; 45 46 static struct plat_sci_port scif1_platform_data = { 47 .scscr = SCSCR_REIE, 48 .type = PORT_SCIF, 49 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 50 }; 51 52 static struct resource scif1_resources[] = { 53 DEFINE_RES_MEM(0xffe10000, 0x100), 54 DEFINE_RES_IRQ(evt2irq(0xc20)), 55 }; 56 57 static struct platform_device scif1_device = { 58 .name = "sh-sci", 59 .id = 1, 60 .resource = scif1_resources, 61 .num_resources = ARRAY_SIZE(scif1_resources), 62 .dev = { 63 .platform_data = &scif1_platform_data, 64 }, 65 }; 66 67 static struct plat_sci_port scif2_platform_data = { 68 .scscr = SCSCR_REIE, 69 .type = PORT_SCIF, 70 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 71 }; 72 73 static struct resource scif2_resources[] = { 74 DEFINE_RES_MEM(0xffe20000, 0x100), 75 DEFINE_RES_IRQ(evt2irq(0xc40)), 76 }; 77 78 static struct platform_device scif2_device = { 79 .name = "sh-sci", 80 .id = 2, 81 .resource = scif2_resources, 82 .num_resources = ARRAY_SIZE(scif2_resources), 83 .dev = { 84 .platform_data = &scif2_platform_data, 85 }, 86 }; 87 88 static struct plat_sci_port scif3_platform_data = { 89 .sampling_rate = 8, 90 .type = PORT_SCIFA, 91 }; 92 93 static struct resource scif3_resources[] = { 94 DEFINE_RES_MEM(0xa4e30000, 0x100), 95 DEFINE_RES_IRQ(evt2irq(0x900)), 96 }; 97 98 static struct platform_device scif3_device = { 99 .name = "sh-sci", 100 .id = 3, 101 .resource = scif3_resources, 102 .num_resources = ARRAY_SIZE(scif3_resources), 103 .dev = { 104 .platform_data = &scif3_platform_data, 105 }, 106 }; 107 108 static struct plat_sci_port scif4_platform_data = { 109 .sampling_rate = 8, 110 .type = PORT_SCIFA, 111 }; 112 113 static struct resource scif4_resources[] = { 114 DEFINE_RES_MEM(0xa4e40000, 0x100), 115 DEFINE_RES_IRQ(evt2irq(0xd00)), 116 }; 117 118 static struct platform_device scif4_device = { 119 .name = "sh-sci", 120 .id = 4, 121 .resource = scif4_resources, 122 .num_resources = ARRAY_SIZE(scif4_resources), 123 .dev = { 124 .platform_data = &scif4_platform_data, 125 }, 126 }; 127 128 static struct plat_sci_port scif5_platform_data = { 129 .sampling_rate = 8, 130 .type = PORT_SCIFA, 131 }; 132 133 static struct resource scif5_resources[] = { 134 DEFINE_RES_MEM(0xa4e50000, 0x100), 135 DEFINE_RES_IRQ(evt2irq(0xfa0)), 136 }; 137 138 static struct platform_device scif5_device = { 139 .name = "sh-sci", 140 .id = 5, 141 .resource = scif5_resources, 142 .num_resources = ARRAY_SIZE(scif5_resources), 143 .dev = { 144 .platform_data = &scif5_platform_data, 145 }, 146 }; 147 148 static struct uio_info vpu_platform_data = { 149 .name = "VPU5", 150 .version = "0", 151 .irq = evt2irq(0x980), 152 }; 153 154 static struct resource vpu_resources[] = { 155 [0] = { 156 .name = "VPU", 157 .start = 0xfe900000, 158 .end = 0xfe902807, 159 .flags = IORESOURCE_MEM, 160 }, 161 [1] = { 162 /* place holder for contiguous memory */ 163 }, 164 }; 165 166 static struct platform_device vpu_device = { 167 .name = "uio_pdrv_genirq", 168 .id = 0, 169 .dev = { 170 .platform_data = &vpu_platform_data, 171 }, 172 .resource = vpu_resources, 173 .num_resources = ARRAY_SIZE(vpu_resources), 174 }; 175 176 static struct uio_info veu0_platform_data = { 177 .name = "VEU2H", 178 .version = "0", 179 .irq = evt2irq(0x8c0), 180 }; 181 182 static struct resource veu0_resources[] = { 183 [0] = { 184 .name = "VEU2H0", 185 .start = 0xfe920000, 186 .end = 0xfe92027b, 187 .flags = IORESOURCE_MEM, 188 }, 189 [1] = { 190 /* place holder for contiguous memory */ 191 }, 192 }; 193 194 static struct platform_device veu0_device = { 195 .name = "uio_pdrv_genirq", 196 .id = 1, 197 .dev = { 198 .platform_data = &veu0_platform_data, 199 }, 200 .resource = veu0_resources, 201 .num_resources = ARRAY_SIZE(veu0_resources), 202 }; 203 204 static struct uio_info veu1_platform_data = { 205 .name = "VEU2H", 206 .version = "0", 207 .irq = evt2irq(0x560), 208 }; 209 210 static struct resource veu1_resources[] = { 211 [0] = { 212 .name = "VEU2H1", 213 .start = 0xfe924000, 214 .end = 0xfe92427b, 215 .flags = IORESOURCE_MEM, 216 }, 217 [1] = { 218 /* place holder for contiguous memory */ 219 }, 220 }; 221 222 static struct platform_device veu1_device = { 223 .name = "uio_pdrv_genirq", 224 .id = 2, 225 .dev = { 226 .platform_data = &veu1_platform_data, 227 }, 228 .resource = veu1_resources, 229 .num_resources = ARRAY_SIZE(veu1_resources), 230 }; 231 232 static struct sh_timer_config cmt_platform_data = { 233 .channels_mask = 0x20, 234 }; 235 236 static struct resource cmt_resources[] = { 237 DEFINE_RES_MEM(0x044a0000, 0x70), 238 DEFINE_RES_IRQ(evt2irq(0xf00)), 239 }; 240 241 static struct platform_device cmt_device = { 242 .name = "sh-cmt-32", 243 .id = 0, 244 .dev = { 245 .platform_data = &cmt_platform_data, 246 }, 247 .resource = cmt_resources, 248 .num_resources = ARRAY_SIZE(cmt_resources), 249 }; 250 251 static struct sh_timer_config tmu0_platform_data = { 252 .channels_mask = 7, 253 }; 254 255 static struct resource tmu0_resources[] = { 256 DEFINE_RES_MEM(0xffd80000, 0x2c), 257 DEFINE_RES_IRQ(evt2irq(0x400)), 258 DEFINE_RES_IRQ(evt2irq(0x420)), 259 DEFINE_RES_IRQ(evt2irq(0x440)), 260 }; 261 262 static struct platform_device tmu0_device = { 263 .name = "sh-tmu", 264 .id = 0, 265 .dev = { 266 .platform_data = &tmu0_platform_data, 267 }, 268 .resource = tmu0_resources, 269 .num_resources = ARRAY_SIZE(tmu0_resources), 270 }; 271 272 static struct sh_timer_config tmu1_platform_data = { 273 .channels_mask = 7, 274 }; 275 276 static struct resource tmu1_resources[] = { 277 DEFINE_RES_MEM(0xffd90000, 0x2c), 278 DEFINE_RES_IRQ(evt2irq(0x920)), 279 DEFINE_RES_IRQ(evt2irq(0x940)), 280 DEFINE_RES_IRQ(evt2irq(0x960)), 281 }; 282 283 static struct platform_device tmu1_device = { 284 .name = "sh-tmu", 285 .id = 1, 286 .dev = { 287 .platform_data = &tmu1_platform_data, 288 }, 289 .resource = tmu1_resources, 290 .num_resources = ARRAY_SIZE(tmu1_resources), 291 }; 292 293 static struct resource rtc_resources[] = { 294 [0] = { 295 .start = 0xa465fec0, 296 .end = 0xa465fec0 + 0x58 - 1, 297 .flags = IORESOURCE_IO, 298 }, 299 [1] = { 300 /* Period IRQ */ 301 .start = evt2irq(0xaa0), 302 .flags = IORESOURCE_IRQ, 303 }, 304 [2] = { 305 /* Carry IRQ */ 306 .start = evt2irq(0xac0), 307 .flags = IORESOURCE_IRQ, 308 }, 309 [3] = { 310 /* Alarm IRQ */ 311 .start = evt2irq(0xa80), 312 .flags = IORESOURCE_IRQ, 313 }, 314 }; 315 316 static struct platform_device rtc_device = { 317 .name = "sh-rtc", 318 .id = -1, 319 .num_resources = ARRAY_SIZE(rtc_resources), 320 .resource = rtc_resources, 321 }; 322 323 static struct r8a66597_platdata r8a66597_data = { 324 .on_chip = 1, 325 }; 326 327 static struct resource sh7723_usb_host_resources[] = { 328 [0] = { 329 .start = 0xa4d80000, 330 .end = 0xa4d800ff, 331 .flags = IORESOURCE_MEM, 332 }, 333 [1] = { 334 .start = evt2irq(0xa20), 335 .end = evt2irq(0xa20), 336 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 337 }, 338 }; 339 340 static struct platform_device sh7723_usb_host_device = { 341 .name = "r8a66597_hcd", 342 .id = 0, 343 .dev = { 344 .dma_mask = NULL, /* not use dma */ 345 .coherent_dma_mask = 0xffffffff, 346 .platform_data = &r8a66597_data, 347 }, 348 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources), 349 .resource = sh7723_usb_host_resources, 350 }; 351 352 static struct resource iic_resources[] = { 353 [0] = { 354 .name = "IIC", 355 .start = 0x04470000, 356 .end = 0x04470017, 357 .flags = IORESOURCE_MEM, 358 }, 359 [1] = { 360 .start = evt2irq(0xe00), 361 .end = evt2irq(0xe60), 362 .flags = IORESOURCE_IRQ, 363 }, 364 }; 365 366 static struct platform_device iic_device = { 367 .name = "i2c-sh_mobile", 368 .id = 0, /* "i2c0" clock */ 369 .num_resources = ARRAY_SIZE(iic_resources), 370 .resource = iic_resources, 371 }; 372 373 static struct platform_device *sh7723_devices[] __initdata = { 374 &scif0_device, 375 &scif1_device, 376 &scif2_device, 377 &scif3_device, 378 &scif4_device, 379 &scif5_device, 380 &cmt_device, 381 &tmu0_device, 382 &tmu1_device, 383 &rtc_device, 384 &iic_device, 385 &sh7723_usb_host_device, 386 &vpu_device, 387 &veu0_device, 388 &veu1_device, 389 }; 390 391 static int __init sh7723_devices_setup(void) 392 { 393 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 394 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 395 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 396 397 return platform_add_devices(sh7723_devices, 398 ARRAY_SIZE(sh7723_devices)); 399 } 400 arch_initcall(sh7723_devices_setup); 401 402 static struct platform_device *sh7723_early_devices[] __initdata = { 403 &scif0_device, 404 &scif1_device, 405 &scif2_device, 406 &scif3_device, 407 &scif4_device, 408 &scif5_device, 409 &cmt_device, 410 &tmu0_device, 411 &tmu1_device, 412 }; 413 414 void __init plat_early_device_setup(void) 415 { 416 early_platform_add_devices(sh7723_early_devices, 417 ARRAY_SIZE(sh7723_early_devices)); 418 } 419 420 #define RAMCR_CACHE_L2FC 0x0002 421 #define RAMCR_CACHE_L2E 0x0001 422 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 423 424 void l2_cache_init(void) 425 { 426 /* Enable L2 cache */ 427 __raw_writel(L2_CACHE_ENABLE, RAMCR); 428 } 429 430 enum { 431 UNUSED=0, 432 ENABLED, 433 DISABLED, 434 435 /* interrupt sources */ 436 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 437 HUDI, 438 DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3, 439 _2DG_TRI,_2DG_INI,_2DG_CEI, 440 DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3, 441 VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI, 442 SCIFA_SCIFA0, 443 VPU_VPUI, 444 TPU_TPUI, 445 ADC_ADI, 446 USB_USI0, 447 RTC_ATI,RTC_PRI,RTC_CUI, 448 DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR, 449 DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR, 450 KEYSC_KEYI, 451 SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2, 452 MSIOF_MSIOFI0,MSIOF_MSIOFI1, 453 SCIFA_SCIFA1, 454 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I, 455 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI, 456 CMT_CMTI, 457 TSIF_TSIFI, 458 SIU_SIUI, 459 SCIFA_SCIFA2, 460 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 461 IRDA_IRDAI, 462 ATAPI_ATAPII, 463 VEU2H1_VEU2HI, 464 LCDC_LCDCI, 465 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2, 466 467 /* interrupt groups */ 468 DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG, 469 SDHI1, RTC, DMAC1B, SDHI0, 470 }; 471 472 static struct intc_vect vectors[] __initdata = { 473 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 474 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 475 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 476 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 477 478 INTC_VECT(DMAC1A_DEI0,0x700), 479 INTC_VECT(DMAC1A_DEI1,0x720), 480 INTC_VECT(DMAC1A_DEI2,0x740), 481 INTC_VECT(DMAC1A_DEI3,0x760), 482 483 INTC_VECT(_2DG_TRI, 0x780), 484 INTC_VECT(_2DG_INI, 0x7A0), 485 INTC_VECT(_2DG_CEI, 0x7C0), 486 487 INTC_VECT(DMAC0A_DEI0,0x800), 488 INTC_VECT(DMAC0A_DEI1,0x820), 489 INTC_VECT(DMAC0A_DEI2,0x840), 490 INTC_VECT(DMAC0A_DEI3,0x860), 491 492 INTC_VECT(VIO_CEUI,0x880), 493 INTC_VECT(VIO_BEUI,0x8A0), 494 INTC_VECT(VIO_VEU2HI,0x8C0), 495 INTC_VECT(VIO_VOUI,0x8E0), 496 497 INTC_VECT(SCIFA_SCIFA0,0x900), 498 INTC_VECT(VPU_VPUI,0x980), 499 INTC_VECT(TPU_TPUI,0x9A0), 500 INTC_VECT(ADC_ADI,0x9E0), 501 INTC_VECT(USB_USI0,0xA20), 502 503 INTC_VECT(RTC_ATI,0xA80), 504 INTC_VECT(RTC_PRI,0xAA0), 505 INTC_VECT(RTC_CUI,0xAC0), 506 507 INTC_VECT(DMAC1B_DEI4,0xB00), 508 INTC_VECT(DMAC1B_DEI5,0xB20), 509 INTC_VECT(DMAC1B_DADERR,0xB40), 510 511 INTC_VECT(DMAC0B_DEI4,0xB80), 512 INTC_VECT(DMAC0B_DEI5,0xBA0), 513 INTC_VECT(DMAC0B_DADERR,0xBC0), 514 515 INTC_VECT(KEYSC_KEYI,0xBE0), 516 INTC_VECT(SCIF_SCIF0,0xC00), 517 INTC_VECT(SCIF_SCIF1,0xC20), 518 INTC_VECT(SCIF_SCIF2,0xC40), 519 INTC_VECT(MSIOF_MSIOFI0,0xC80), 520 INTC_VECT(MSIOF_MSIOFI1,0xCA0), 521 INTC_VECT(SCIFA_SCIFA1,0xD00), 522 523 INTC_VECT(FLCTL_FLSTEI,0xD80), 524 INTC_VECT(FLCTL_FLTENDI,0xDA0), 525 INTC_VECT(FLCTL_FLTREQ0I,0xDC0), 526 INTC_VECT(FLCTL_FLTREQ1I,0xDE0), 527 528 INTC_VECT(I2C_ALI,0xE00), 529 INTC_VECT(I2C_TACKI,0xE20), 530 INTC_VECT(I2C_WAITI,0xE40), 531 INTC_VECT(I2C_DTEI,0xE60), 532 533 INTC_VECT(SDHI0, 0xE80), 534 INTC_VECT(SDHI0, 0xEA0), 535 INTC_VECT(SDHI0, 0xEC0), 536 537 INTC_VECT(CMT_CMTI,0xF00), 538 INTC_VECT(TSIF_TSIFI,0xF20), 539 INTC_VECT(SIU_SIUI,0xF80), 540 INTC_VECT(SCIFA_SCIFA2,0xFA0), 541 542 INTC_VECT(TMU0_TUNI0,0x400), 543 INTC_VECT(TMU0_TUNI1,0x420), 544 INTC_VECT(TMU0_TUNI2,0x440), 545 546 INTC_VECT(IRDA_IRDAI,0x480), 547 INTC_VECT(ATAPI_ATAPII,0x4A0), 548 549 INTC_VECT(SDHI1, 0x4E0), 550 INTC_VECT(SDHI1, 0x500), 551 INTC_VECT(SDHI1, 0x520), 552 553 INTC_VECT(VEU2H1_VEU2HI,0x560), 554 INTC_VECT(LCDC_LCDCI,0x580), 555 556 INTC_VECT(TMU1_TUNI0,0x920), 557 INTC_VECT(TMU1_TUNI1,0x940), 558 INTC_VECT(TMU1_TUNI2,0x960), 559 560 }; 561 562 static struct intc_group groups[] __initdata = { 563 INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3), 564 INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3), 565 INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI), 566 INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR), 567 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I), 568 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI), 569 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI), 570 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI), 571 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR), 572 }; 573 574 static struct intc_mask_reg mask_registers[] __initdata = { 575 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 576 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 577 0, ENABLED, ENABLED, ENABLED } }, 578 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 579 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, 580 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 581 { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } }, 582 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 583 { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } }, 584 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 585 { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } }, 586 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 587 { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } }, 588 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 589 { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } }, 590 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 591 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 592 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 593 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 594 { 0, ENABLED, ENABLED, ENABLED, 595 0, 0, SCIFA_SCIFA2, SIU_SIUI } }, 596 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 597 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, 598 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 599 { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } }, 600 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 601 { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } }, 602 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */ 603 { 0,0,0,0,0,0,0,ATAPI_ATAPII } }, 604 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 605 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 606 }; 607 608 static struct intc_prio_reg prio_registers[] __initdata = { 609 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } }, 610 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} }, 611 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} }, 612 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 613 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } }, 614 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } }, 615 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } }, 616 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } }, 617 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } }, 618 { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } }, 619 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } }, 620 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } }, 621 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 622 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 623 }; 624 625 static struct intc_sense_reg sense_registers[] __initdata = { 626 { 0xa414001c, 16, 2, /* ICR1 */ 627 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 628 }; 629 630 static struct intc_mask_reg ack_registers[] __initdata = { 631 { 0xa4140024, 0, 8, /* INTREQ00 */ 632 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 633 }; 634 635 static struct intc_desc intc_desc __initdata = { 636 .name = "sh7723", 637 .force_enable = ENABLED, 638 .force_disable = DISABLED, 639 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 640 prio_registers, sense_registers, ack_registers), 641 }; 642 643 void __init plat_irq_setup(void) 644 { 645 register_intc_controller(&intc_desc); 646 } 647