1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Regents of the University of California 4 * Copyright (c) 2020 Western Digital Corporation or its affiliates. 5 */ 6 7 #ifndef _ASM_RISCV_SBI_H 8 #define _ASM_RISCV_SBI_H 9 10 #include <linux/types.h> 11 #include <linux/cpumask.h> 12 13 #ifdef CONFIG_RISCV_SBI 14 enum sbi_ext_id { 15 #ifdef CONFIG_RISCV_SBI_V01 16 SBI_EXT_0_1_SET_TIMER = 0x0, 17 SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, 18 SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, 19 SBI_EXT_0_1_CLEAR_IPI = 0x3, 20 SBI_EXT_0_1_SEND_IPI = 0x4, 21 SBI_EXT_0_1_REMOTE_FENCE_I = 0x5, 22 SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, 23 SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, 24 SBI_EXT_0_1_SHUTDOWN = 0x8, 25 #endif 26 SBI_EXT_BASE = 0x10, 27 SBI_EXT_TIME = 0x54494D45, 28 SBI_EXT_IPI = 0x735049, 29 SBI_EXT_RFENCE = 0x52464E43, 30 SBI_EXT_HSM = 0x48534D, 31 SBI_EXT_SRST = 0x53525354, 32 SBI_EXT_PMU = 0x504D55, 33 34 /* Experimentals extensions must lie within this range */ 35 SBI_EXT_EXPERIMENTAL_START = 0x08000000, 36 SBI_EXT_EXPERIMENTAL_END = 0x08FFFFFF, 37 38 /* Vendor extensions must lie within this range */ 39 SBI_EXT_VENDOR_START = 0x09000000, 40 SBI_EXT_VENDOR_END = 0x09FFFFFF, 41 }; 42 43 enum sbi_ext_base_fid { 44 SBI_EXT_BASE_GET_SPEC_VERSION = 0, 45 SBI_EXT_BASE_GET_IMP_ID, 46 SBI_EXT_BASE_GET_IMP_VERSION, 47 SBI_EXT_BASE_PROBE_EXT, 48 SBI_EXT_BASE_GET_MVENDORID, 49 SBI_EXT_BASE_GET_MARCHID, 50 SBI_EXT_BASE_GET_MIMPID, 51 }; 52 53 enum sbi_ext_time_fid { 54 SBI_EXT_TIME_SET_TIMER = 0, 55 }; 56 57 enum sbi_ext_ipi_fid { 58 SBI_EXT_IPI_SEND_IPI = 0, 59 }; 60 61 enum sbi_ext_rfence_fid { 62 SBI_EXT_RFENCE_REMOTE_FENCE_I = 0, 63 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, 64 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, 65 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID, 66 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA, 67 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID, 68 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA, 69 }; 70 71 enum sbi_ext_hsm_fid { 72 SBI_EXT_HSM_HART_START = 0, 73 SBI_EXT_HSM_HART_STOP, 74 SBI_EXT_HSM_HART_STATUS, 75 SBI_EXT_HSM_HART_SUSPEND, 76 }; 77 78 enum sbi_hsm_hart_state { 79 SBI_HSM_STATE_STARTED = 0, 80 SBI_HSM_STATE_STOPPED, 81 SBI_HSM_STATE_START_PENDING, 82 SBI_HSM_STATE_STOP_PENDING, 83 SBI_HSM_STATE_SUSPENDED, 84 SBI_HSM_STATE_SUSPEND_PENDING, 85 SBI_HSM_STATE_RESUME_PENDING, 86 }; 87 88 #define SBI_HSM_SUSP_BASE_MASK 0x7fffffff 89 #define SBI_HSM_SUSP_NON_RET_BIT 0x80000000 90 #define SBI_HSM_SUSP_PLAT_BASE 0x10000000 91 92 #define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000 93 #define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE 94 #define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK 95 #define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT 96 #define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \ 97 SBI_HSM_SUSP_PLAT_BASE) 98 #define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \ 99 SBI_HSM_SUSP_BASE_MASK) 100 101 enum sbi_ext_srst_fid { 102 SBI_EXT_SRST_RESET = 0, 103 }; 104 105 enum sbi_srst_reset_type { 106 SBI_SRST_RESET_TYPE_SHUTDOWN = 0, 107 SBI_SRST_RESET_TYPE_COLD_REBOOT, 108 SBI_SRST_RESET_TYPE_WARM_REBOOT, 109 }; 110 111 enum sbi_srst_reset_reason { 112 SBI_SRST_RESET_REASON_NONE = 0, 113 SBI_SRST_RESET_REASON_SYS_FAILURE, 114 }; 115 116 enum sbi_ext_pmu_fid { 117 SBI_EXT_PMU_NUM_COUNTERS = 0, 118 SBI_EXT_PMU_COUNTER_GET_INFO, 119 SBI_EXT_PMU_COUNTER_CFG_MATCH, 120 SBI_EXT_PMU_COUNTER_START, 121 SBI_EXT_PMU_COUNTER_STOP, 122 SBI_EXT_PMU_COUNTER_FW_READ, 123 }; 124 125 union sbi_pmu_ctr_info { 126 unsigned long value; 127 struct { 128 unsigned long csr:12; 129 unsigned long width:6; 130 #if __riscv_xlen == 32 131 unsigned long reserved:13; 132 #else 133 unsigned long reserved:45; 134 #endif 135 unsigned long type:1; 136 }; 137 }; 138 139 #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) 140 #define RISCV_PMU_RAW_EVENT_IDX 0x20000 141 142 /** General pmu event codes specified in SBI PMU extension */ 143 enum sbi_pmu_hw_generic_events_t { 144 SBI_PMU_HW_NO_EVENT = 0, 145 SBI_PMU_HW_CPU_CYCLES = 1, 146 SBI_PMU_HW_INSTRUCTIONS = 2, 147 SBI_PMU_HW_CACHE_REFERENCES = 3, 148 SBI_PMU_HW_CACHE_MISSES = 4, 149 SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5, 150 SBI_PMU_HW_BRANCH_MISSES = 6, 151 SBI_PMU_HW_BUS_CYCLES = 7, 152 SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8, 153 SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9, 154 SBI_PMU_HW_REF_CPU_CYCLES = 10, 155 156 SBI_PMU_HW_GENERAL_MAX, 157 }; 158 159 /** 160 * Special "firmware" events provided by the firmware, even if the hardware 161 * does not support performance events. These events are encoded as a raw 162 * event type in Linux kernel perf framework. 163 */ 164 enum sbi_pmu_fw_generic_events_t { 165 SBI_PMU_FW_MISALIGNED_LOAD = 0, 166 SBI_PMU_FW_MISALIGNED_STORE = 1, 167 SBI_PMU_FW_ACCESS_LOAD = 2, 168 SBI_PMU_FW_ACCESS_STORE = 3, 169 SBI_PMU_FW_ILLEGAL_INSN = 4, 170 SBI_PMU_FW_SET_TIMER = 5, 171 SBI_PMU_FW_IPI_SENT = 6, 172 SBI_PMU_FW_IPI_RECVD = 7, 173 SBI_PMU_FW_FENCE_I_SENT = 8, 174 SBI_PMU_FW_FENCE_I_RECVD = 9, 175 SBI_PMU_FW_SFENCE_VMA_SENT = 10, 176 SBI_PMU_FW_SFENCE_VMA_RCVD = 11, 177 SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12, 178 SBI_PMU_FW_SFENCE_VMA_ASID_RCVD = 13, 179 180 SBI_PMU_FW_HFENCE_GVMA_SENT = 14, 181 SBI_PMU_FW_HFENCE_GVMA_RCVD = 15, 182 SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16, 183 SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17, 184 185 SBI_PMU_FW_HFENCE_VVMA_SENT = 18, 186 SBI_PMU_FW_HFENCE_VVMA_RCVD = 19, 187 SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20, 188 SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21, 189 SBI_PMU_FW_MAX, 190 }; 191 192 /* SBI PMU event types */ 193 enum sbi_pmu_event_type { 194 SBI_PMU_EVENT_TYPE_HW = 0x0, 195 SBI_PMU_EVENT_TYPE_CACHE = 0x1, 196 SBI_PMU_EVENT_TYPE_RAW = 0x2, 197 SBI_PMU_EVENT_TYPE_FW = 0xf, 198 }; 199 200 /* SBI PMU event types */ 201 enum sbi_pmu_ctr_type { 202 SBI_PMU_CTR_TYPE_HW = 0x0, 203 SBI_PMU_CTR_TYPE_FW, 204 }; 205 206 /* Helper macros to decode event idx */ 207 #define SBI_PMU_EVENT_IDX_OFFSET 20 208 #define SBI_PMU_EVENT_IDX_MASK 0xFFFFF 209 #define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF 210 #define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000 211 #define SBI_PMU_EVENT_RAW_IDX 0x20000 212 #define SBI_PMU_FIXED_CTR_MASK 0x07 213 214 #define SBI_PMU_EVENT_CACHE_ID_CODE_MASK 0xFFF8 215 #define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06 216 #define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01 217 218 #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF 219 220 /* Flags defined for config matching function */ 221 #define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) 222 #define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) 223 #define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) 224 #define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) 225 #define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) 226 #define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) 227 #define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) 228 #define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) 229 230 /* Flags defined for counter start function */ 231 #define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) 232 233 /* Flags defined for counter stop function */ 234 #define SBI_PMU_STOP_FLAG_RESET (1 << 0) 235 236 #define SBI_SPEC_VERSION_DEFAULT 0x1 237 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 238 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f 239 #define SBI_SPEC_VERSION_MINOR_MASK 0xffffff 240 241 /* SBI return error codes */ 242 #define SBI_SUCCESS 0 243 #define SBI_ERR_FAILURE -1 244 #define SBI_ERR_NOT_SUPPORTED -2 245 #define SBI_ERR_INVALID_PARAM -3 246 #define SBI_ERR_DENIED -4 247 #define SBI_ERR_INVALID_ADDRESS -5 248 #define SBI_ERR_ALREADY_AVAILABLE -6 249 #define SBI_ERR_ALREADY_STARTED -7 250 #define SBI_ERR_ALREADY_STOPPED -8 251 252 extern unsigned long sbi_spec_version; 253 struct sbiret { 254 long error; 255 long value; 256 }; 257 258 void sbi_init(void); 259 struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, 260 unsigned long arg1, unsigned long arg2, 261 unsigned long arg3, unsigned long arg4, 262 unsigned long arg5); 263 264 void sbi_console_putchar(int ch); 265 int sbi_console_getchar(void); 266 long sbi_get_mvendorid(void); 267 long sbi_get_marchid(void); 268 long sbi_get_mimpid(void); 269 void sbi_set_timer(uint64_t stime_value); 270 void sbi_shutdown(void); 271 void sbi_clear_ipi(void); 272 int sbi_send_ipi(const struct cpumask *cpu_mask); 273 int sbi_remote_fence_i(const struct cpumask *cpu_mask); 274 int sbi_remote_sfence_vma(const struct cpumask *cpu_mask, 275 unsigned long start, 276 unsigned long size); 277 278 int sbi_remote_sfence_vma_asid(const struct cpumask *cpu_mask, 279 unsigned long start, 280 unsigned long size, 281 unsigned long asid); 282 int sbi_remote_hfence_gvma(const struct cpumask *cpu_mask, 283 unsigned long start, 284 unsigned long size); 285 int sbi_remote_hfence_gvma_vmid(const struct cpumask *cpu_mask, 286 unsigned long start, 287 unsigned long size, 288 unsigned long vmid); 289 int sbi_remote_hfence_vvma(const struct cpumask *cpu_mask, 290 unsigned long start, 291 unsigned long size); 292 int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask, 293 unsigned long start, 294 unsigned long size, 295 unsigned long asid); 296 int sbi_probe_extension(int ext); 297 298 /* Check if current SBI specification version is 0.1 or not */ 299 static inline int sbi_spec_is_0_1(void) 300 { 301 return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0; 302 } 303 304 /* Get the major version of SBI */ 305 static inline unsigned long sbi_major_version(void) 306 { 307 return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) & 308 SBI_SPEC_VERSION_MAJOR_MASK; 309 } 310 311 /* Get the minor version of SBI */ 312 static inline unsigned long sbi_minor_version(void) 313 { 314 return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK; 315 } 316 317 /* Make SBI version */ 318 static inline unsigned long sbi_mk_version(unsigned long major, 319 unsigned long minor) 320 { 321 return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << 322 SBI_SPEC_VERSION_MAJOR_SHIFT) | minor; 323 } 324 325 int sbi_err_map_linux_errno(int err); 326 #else /* CONFIG_RISCV_SBI */ 327 static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; } 328 static inline void sbi_init(void) {} 329 #endif /* CONFIG_RISCV_SBI */ 330 331 unsigned long riscv_cached_mvendorid(unsigned int cpu_id); 332 unsigned long riscv_cached_marchid(unsigned int cpu_id); 333 unsigned long riscv_cached_mimpid(unsigned int cpu_id); 334 335 #endif /* _ASM_RISCV_SBI_H */ 336