1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Erratas to be applied for Andes CPU cores 4 * 5 * Copyright (C) 2023 Renesas Electronics Corporation. 6 * 7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 8 */ 9 10 #include <linux/memory.h> 11 #include <linux/module.h> 12 13 #include <asm/alternative.h> 14 #include <asm/cacheflush.h> 15 #include <asm/errata_list.h> 16 #include <asm/patch.h> 17 #include <asm/processor.h> 18 #include <asm/sbi.h> 19 #include <asm/vendorid_list.h> 20 21 #define ANDESTECH_AX45MP_MARCHID 0x8000000000008a45UL 22 #define ANDESTECH_AX45MP_MIMPID 0x500UL 23 #define ANDESTECH_SBI_EXT_ANDES 0x0900031E 24 25 #define ANDES_SBI_EXT_IOCP_SW_WORKAROUND 1 26 27 static long ax45mp_iocp_sw_workaround(void) 28 { 29 struct sbiret ret; 30 31 /* 32 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and 33 * cache is controllable only then CMO will be applied to the platform. 34 */ 35 ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND, 36 0, 0, 0, 0, 0, 0); 37 38 return ret.error ? 0 : ret.value; 39 } 40 41 static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid) 42 { 43 if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO)) 44 return false; 45 46 if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID) 47 return false; 48 49 if (!ax45mp_iocp_sw_workaround()) 50 return false; 51 52 /* Set this just to make core cbo code happy */ 53 riscv_cbom_block_size = 1; 54 riscv_noncoherent_supported(); 55 56 return true; 57 } 58 59 void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, 60 unsigned long archid, unsigned long impid, 61 unsigned int stage) 62 { 63 errata_probe_iocp(stage, archid, impid); 64 65 /* we have nothing to patch here ATM so just return back */ 66 } 67