1 /* 2 * Single-step support. 3 * 4 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 #include <linux/kernel.h> 12 #include <linux/kprobes.h> 13 #include <linux/ptrace.h> 14 #include <linux/prefetch.h> 15 #include <asm/sstep.h> 16 #include <asm/processor.h> 17 #include <linux/uaccess.h> 18 #include <asm/cpu_has_feature.h> 19 #include <asm/cputable.h> 20 21 extern char system_call_common[]; 22 23 #ifdef CONFIG_PPC64 24 /* Bits in SRR1 that are copied from MSR */ 25 #define MSR_MASK 0xffffffff87c0ffffUL 26 #else 27 #define MSR_MASK 0x87c0ffff 28 #endif 29 30 /* Bits in XER */ 31 #define XER_SO 0x80000000U 32 #define XER_OV 0x40000000U 33 #define XER_CA 0x20000000U 34 35 #ifdef CONFIG_PPC_FPU 36 /* 37 * Functions in ldstfp.S 38 */ 39 extern int do_lfs(int rn, unsigned long ea); 40 extern int do_lfd(int rn, unsigned long ea); 41 extern int do_stfs(int rn, unsigned long ea); 42 extern int do_stfd(int rn, unsigned long ea); 43 extern int do_lvx(int rn, unsigned long ea); 44 extern int do_stvx(int rn, unsigned long ea); 45 extern int do_lxvd2x(int rn, unsigned long ea); 46 extern int do_stxvd2x(int rn, unsigned long ea); 47 #endif 48 49 /* 50 * Emulate the truncation of 64 bit values in 32-bit mode. 51 */ 52 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr, 53 unsigned long val) 54 { 55 #ifdef __powerpc64__ 56 if ((msr & MSR_64BIT) == 0) 57 val &= 0xffffffffUL; 58 #endif 59 return val; 60 } 61 62 /* 63 * Determine whether a conditional branch instruction would branch. 64 */ 65 static nokprobe_inline int branch_taken(unsigned int instr, struct pt_regs *regs) 66 { 67 unsigned int bo = (instr >> 21) & 0x1f; 68 unsigned int bi; 69 70 if ((bo & 4) == 0) { 71 /* decrement counter */ 72 --regs->ctr; 73 if (((bo >> 1) & 1) ^ (regs->ctr == 0)) 74 return 0; 75 } 76 if ((bo & 0x10) == 0) { 77 /* check bit from CR */ 78 bi = (instr >> 16) & 0x1f; 79 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1)) 80 return 0; 81 } 82 return 1; 83 } 84 85 static nokprobe_inline long address_ok(struct pt_regs *regs, unsigned long ea, int nb) 86 { 87 if (!user_mode(regs)) 88 return 1; 89 return __access_ok(ea, nb, USER_DS); 90 } 91 92 /* 93 * Calculate effective address for a D-form instruction 94 */ 95 static nokprobe_inline unsigned long dform_ea(unsigned int instr, struct pt_regs *regs) 96 { 97 int ra; 98 unsigned long ea; 99 100 ra = (instr >> 16) & 0x1f; 101 ea = (signed short) instr; /* sign-extend */ 102 if (ra) 103 ea += regs->gpr[ra]; 104 105 return truncate_if_32bit(regs->msr, ea); 106 } 107 108 #ifdef __powerpc64__ 109 /* 110 * Calculate effective address for a DS-form instruction 111 */ 112 static nokprobe_inline unsigned long dsform_ea(unsigned int instr, struct pt_regs *regs) 113 { 114 int ra; 115 unsigned long ea; 116 117 ra = (instr >> 16) & 0x1f; 118 ea = (signed short) (instr & ~3); /* sign-extend */ 119 if (ra) 120 ea += regs->gpr[ra]; 121 122 return truncate_if_32bit(regs->msr, ea); 123 } 124 #endif /* __powerpc64 */ 125 126 /* 127 * Calculate effective address for an X-form instruction 128 */ 129 static nokprobe_inline unsigned long xform_ea(unsigned int instr, 130 struct pt_regs *regs) 131 { 132 int ra, rb; 133 unsigned long ea; 134 135 ra = (instr >> 16) & 0x1f; 136 rb = (instr >> 11) & 0x1f; 137 ea = regs->gpr[rb]; 138 if (ra) 139 ea += regs->gpr[ra]; 140 141 return truncate_if_32bit(regs->msr, ea); 142 } 143 144 /* 145 * Return the largest power of 2, not greater than sizeof(unsigned long), 146 * such that x is a multiple of it. 147 */ 148 static nokprobe_inline unsigned long max_align(unsigned long x) 149 { 150 x |= sizeof(unsigned long); 151 return x & -x; /* isolates rightmost bit */ 152 } 153 154 155 static nokprobe_inline unsigned long byterev_2(unsigned long x) 156 { 157 return ((x >> 8) & 0xff) | ((x & 0xff) << 8); 158 } 159 160 static nokprobe_inline unsigned long byterev_4(unsigned long x) 161 { 162 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) | 163 ((x & 0xff00) << 8) | ((x & 0xff) << 24); 164 } 165 166 #ifdef __powerpc64__ 167 static nokprobe_inline unsigned long byterev_8(unsigned long x) 168 { 169 return (byterev_4(x) << 32) | byterev_4(x >> 32); 170 } 171 #endif 172 173 static nokprobe_inline int read_mem_aligned(unsigned long *dest, 174 unsigned long ea, int nb) 175 { 176 int err = 0; 177 unsigned long x = 0; 178 179 switch (nb) { 180 case 1: 181 err = __get_user(x, (unsigned char __user *) ea); 182 break; 183 case 2: 184 err = __get_user(x, (unsigned short __user *) ea); 185 break; 186 case 4: 187 err = __get_user(x, (unsigned int __user *) ea); 188 break; 189 #ifdef __powerpc64__ 190 case 8: 191 err = __get_user(x, (unsigned long __user *) ea); 192 break; 193 #endif 194 } 195 if (!err) 196 *dest = x; 197 return err; 198 } 199 200 static nokprobe_inline int read_mem_unaligned(unsigned long *dest, 201 unsigned long ea, int nb, struct pt_regs *regs) 202 { 203 int err; 204 unsigned long x, b, c; 205 #ifdef __LITTLE_ENDIAN__ 206 int len = nb; /* save a copy of the length for byte reversal */ 207 #endif 208 209 /* unaligned, do this in pieces */ 210 x = 0; 211 for (; nb > 0; nb -= c) { 212 #ifdef __LITTLE_ENDIAN__ 213 c = 1; 214 #endif 215 #ifdef __BIG_ENDIAN__ 216 c = max_align(ea); 217 #endif 218 if (c > nb) 219 c = max_align(nb); 220 err = read_mem_aligned(&b, ea, c); 221 if (err) 222 return err; 223 x = (x << (8 * c)) + b; 224 ea += c; 225 } 226 #ifdef __LITTLE_ENDIAN__ 227 switch (len) { 228 case 2: 229 *dest = byterev_2(x); 230 break; 231 case 4: 232 *dest = byterev_4(x); 233 break; 234 #ifdef __powerpc64__ 235 case 8: 236 *dest = byterev_8(x); 237 break; 238 #endif 239 } 240 #endif 241 #ifdef __BIG_ENDIAN__ 242 *dest = x; 243 #endif 244 return 0; 245 } 246 247 /* 248 * Read memory at address ea for nb bytes, return 0 for success 249 * or -EFAULT if an error occurred. 250 */ 251 static int read_mem(unsigned long *dest, unsigned long ea, int nb, 252 struct pt_regs *regs) 253 { 254 if (!address_ok(regs, ea, nb)) 255 return -EFAULT; 256 if ((ea & (nb - 1)) == 0) 257 return read_mem_aligned(dest, ea, nb); 258 return read_mem_unaligned(dest, ea, nb, regs); 259 } 260 NOKPROBE_SYMBOL(read_mem); 261 262 static nokprobe_inline int write_mem_aligned(unsigned long val, 263 unsigned long ea, int nb) 264 { 265 int err = 0; 266 267 switch (nb) { 268 case 1: 269 err = __put_user(val, (unsigned char __user *) ea); 270 break; 271 case 2: 272 err = __put_user(val, (unsigned short __user *) ea); 273 break; 274 case 4: 275 err = __put_user(val, (unsigned int __user *) ea); 276 break; 277 #ifdef __powerpc64__ 278 case 8: 279 err = __put_user(val, (unsigned long __user *) ea); 280 break; 281 #endif 282 } 283 return err; 284 } 285 286 static nokprobe_inline int write_mem_unaligned(unsigned long val, 287 unsigned long ea, int nb, struct pt_regs *regs) 288 { 289 int err; 290 unsigned long c; 291 292 #ifdef __LITTLE_ENDIAN__ 293 switch (nb) { 294 case 2: 295 val = byterev_2(val); 296 break; 297 case 4: 298 val = byterev_4(val); 299 break; 300 #ifdef __powerpc64__ 301 case 8: 302 val = byterev_8(val); 303 break; 304 #endif 305 } 306 #endif 307 /* unaligned or little-endian, do this in pieces */ 308 for (; nb > 0; nb -= c) { 309 #ifdef __LITTLE_ENDIAN__ 310 c = 1; 311 #endif 312 #ifdef __BIG_ENDIAN__ 313 c = max_align(ea); 314 #endif 315 if (c > nb) 316 c = max_align(nb); 317 err = write_mem_aligned(val >> (nb - c) * 8, ea, c); 318 if (err) 319 return err; 320 ea += c; 321 } 322 return 0; 323 } 324 325 /* 326 * Write memory at address ea for nb bytes, return 0 for success 327 * or -EFAULT if an error occurred. 328 */ 329 static int write_mem(unsigned long val, unsigned long ea, int nb, 330 struct pt_regs *regs) 331 { 332 if (!address_ok(regs, ea, nb)) 333 return -EFAULT; 334 if ((ea & (nb - 1)) == 0) 335 return write_mem_aligned(val, ea, nb); 336 return write_mem_unaligned(val, ea, nb, regs); 337 } 338 NOKPROBE_SYMBOL(write_mem); 339 340 #ifdef CONFIG_PPC_FPU 341 /* 342 * Check the address and alignment, and call func to do the actual 343 * load or store. 344 */ 345 static int do_fp_load(int rn, int (*func)(int, unsigned long), 346 unsigned long ea, int nb, 347 struct pt_regs *regs) 348 { 349 int err; 350 union { 351 double dbl; 352 unsigned long ul[2]; 353 struct { 354 #ifdef __BIG_ENDIAN__ 355 unsigned _pad_; 356 unsigned word; 357 #endif 358 #ifdef __LITTLE_ENDIAN__ 359 unsigned word; 360 unsigned _pad_; 361 #endif 362 } single; 363 } data; 364 unsigned long ptr; 365 366 if (!address_ok(regs, ea, nb)) 367 return -EFAULT; 368 if ((ea & 3) == 0) 369 return (*func)(rn, ea); 370 ptr = (unsigned long) &data.ul; 371 if (sizeof(unsigned long) == 8 || nb == 4) { 372 err = read_mem_unaligned(&data.ul[0], ea, nb, regs); 373 if (nb == 4) 374 ptr = (unsigned long)&(data.single.word); 375 } else { 376 /* reading a double on 32-bit */ 377 err = read_mem_unaligned(&data.ul[0], ea, 4, regs); 378 if (!err) 379 err = read_mem_unaligned(&data.ul[1], ea + 4, 4, regs); 380 } 381 if (err) 382 return err; 383 return (*func)(rn, ptr); 384 } 385 NOKPROBE_SYMBOL(do_fp_load); 386 387 static int do_fp_store(int rn, int (*func)(int, unsigned long), 388 unsigned long ea, int nb, 389 struct pt_regs *regs) 390 { 391 int err; 392 union { 393 double dbl; 394 unsigned long ul[2]; 395 struct { 396 #ifdef __BIG_ENDIAN__ 397 unsigned _pad_; 398 unsigned word; 399 #endif 400 #ifdef __LITTLE_ENDIAN__ 401 unsigned word; 402 unsigned _pad_; 403 #endif 404 } single; 405 } data; 406 unsigned long ptr; 407 408 if (!address_ok(regs, ea, nb)) 409 return -EFAULT; 410 if ((ea & 3) == 0) 411 return (*func)(rn, ea); 412 ptr = (unsigned long) &data.ul[0]; 413 if (sizeof(unsigned long) == 8 || nb == 4) { 414 if (nb == 4) 415 ptr = (unsigned long)&(data.single.word); 416 err = (*func)(rn, ptr); 417 if (err) 418 return err; 419 err = write_mem_unaligned(data.ul[0], ea, nb, regs); 420 } else { 421 /* writing a double on 32-bit */ 422 err = (*func)(rn, ptr); 423 if (err) 424 return err; 425 err = write_mem_unaligned(data.ul[0], ea, 4, regs); 426 if (!err) 427 err = write_mem_unaligned(data.ul[1], ea + 4, 4, regs); 428 } 429 return err; 430 } 431 NOKPROBE_SYMBOL(do_fp_store); 432 #endif 433 434 #ifdef CONFIG_ALTIVEC 435 /* For Altivec/VMX, no need to worry about alignment */ 436 static nokprobe_inline int do_vec_load(int rn, int (*func)(int, unsigned long), 437 unsigned long ea, struct pt_regs *regs) 438 { 439 if (!address_ok(regs, ea & ~0xfUL, 16)) 440 return -EFAULT; 441 return (*func)(rn, ea); 442 } 443 444 static nokprobe_inline int do_vec_store(int rn, int (*func)(int, unsigned long), 445 unsigned long ea, struct pt_regs *regs) 446 { 447 if (!address_ok(regs, ea & ~0xfUL, 16)) 448 return -EFAULT; 449 return (*func)(rn, ea); 450 } 451 #endif /* CONFIG_ALTIVEC */ 452 453 #ifdef CONFIG_VSX 454 static nokprobe_inline int do_vsx_load(int rn, int (*func)(int, unsigned long), 455 unsigned long ea, struct pt_regs *regs) 456 { 457 int err; 458 unsigned long val[2]; 459 460 if (!address_ok(regs, ea, 16)) 461 return -EFAULT; 462 if ((ea & 3) == 0) 463 return (*func)(rn, ea); 464 err = read_mem_unaligned(&val[0], ea, 8, regs); 465 if (!err) 466 err = read_mem_unaligned(&val[1], ea + 8, 8, regs); 467 if (!err) 468 err = (*func)(rn, (unsigned long) &val[0]); 469 return err; 470 } 471 472 static nokprobe_inline int do_vsx_store(int rn, int (*func)(int, unsigned long), 473 unsigned long ea, struct pt_regs *regs) 474 { 475 int err; 476 unsigned long val[2]; 477 478 if (!address_ok(regs, ea, 16)) 479 return -EFAULT; 480 if ((ea & 3) == 0) 481 return (*func)(rn, ea); 482 err = (*func)(rn, (unsigned long) &val[0]); 483 if (err) 484 return err; 485 err = write_mem_unaligned(val[0], ea, 8, regs); 486 if (!err) 487 err = write_mem_unaligned(val[1], ea + 8, 8, regs); 488 return err; 489 } 490 #endif /* CONFIG_VSX */ 491 492 #define __put_user_asmx(x, addr, err, op, cr) \ 493 __asm__ __volatile__( \ 494 "1: " op " %2,0,%3\n" \ 495 " mfcr %1\n" \ 496 "2:\n" \ 497 ".section .fixup,\"ax\"\n" \ 498 "3: li %0,%4\n" \ 499 " b 2b\n" \ 500 ".previous\n" \ 501 EX_TABLE(1b, 3b) \ 502 : "=r" (err), "=r" (cr) \ 503 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err)) 504 505 #define __get_user_asmx(x, addr, err, op) \ 506 __asm__ __volatile__( \ 507 "1: "op" %1,0,%2\n" \ 508 "2:\n" \ 509 ".section .fixup,\"ax\"\n" \ 510 "3: li %0,%3\n" \ 511 " b 2b\n" \ 512 ".previous\n" \ 513 EX_TABLE(1b, 3b) \ 514 : "=r" (err), "=r" (x) \ 515 : "r" (addr), "i" (-EFAULT), "0" (err)) 516 517 #define __cacheop_user_asmx(addr, err, op) \ 518 __asm__ __volatile__( \ 519 "1: "op" 0,%1\n" \ 520 "2:\n" \ 521 ".section .fixup,\"ax\"\n" \ 522 "3: li %0,%3\n" \ 523 " b 2b\n" \ 524 ".previous\n" \ 525 EX_TABLE(1b, 3b) \ 526 : "=r" (err) \ 527 : "r" (addr), "i" (-EFAULT), "0" (err)) 528 529 static nokprobe_inline void set_cr0(struct pt_regs *regs, int rd) 530 { 531 long val = regs->gpr[rd]; 532 533 regs->ccr = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000); 534 #ifdef __powerpc64__ 535 if (!(regs->msr & MSR_64BIT)) 536 val = (int) val; 537 #endif 538 if (val < 0) 539 regs->ccr |= 0x80000000; 540 else if (val > 0) 541 regs->ccr |= 0x40000000; 542 else 543 regs->ccr |= 0x20000000; 544 } 545 546 static nokprobe_inline void add_with_carry(struct pt_regs *regs, int rd, 547 unsigned long val1, unsigned long val2, 548 unsigned long carry_in) 549 { 550 unsigned long val = val1 + val2; 551 552 if (carry_in) 553 ++val; 554 regs->gpr[rd] = val; 555 #ifdef __powerpc64__ 556 if (!(regs->msr & MSR_64BIT)) { 557 val = (unsigned int) val; 558 val1 = (unsigned int) val1; 559 } 560 #endif 561 if (val < val1 || (carry_in && val == val1)) 562 regs->xer |= XER_CA; 563 else 564 regs->xer &= ~XER_CA; 565 } 566 567 static nokprobe_inline void do_cmp_signed(struct pt_regs *regs, long v1, long v2, 568 int crfld) 569 { 570 unsigned int crval, shift; 571 572 crval = (regs->xer >> 31) & 1; /* get SO bit */ 573 if (v1 < v2) 574 crval |= 8; 575 else if (v1 > v2) 576 crval |= 4; 577 else 578 crval |= 2; 579 shift = (7 - crfld) * 4; 580 regs->ccr = (regs->ccr & ~(0xf << shift)) | (crval << shift); 581 } 582 583 static nokprobe_inline void do_cmp_unsigned(struct pt_regs *regs, unsigned long v1, 584 unsigned long v2, int crfld) 585 { 586 unsigned int crval, shift; 587 588 crval = (regs->xer >> 31) & 1; /* get SO bit */ 589 if (v1 < v2) 590 crval |= 8; 591 else if (v1 > v2) 592 crval |= 4; 593 else 594 crval |= 2; 595 shift = (7 - crfld) * 4; 596 regs->ccr = (regs->ccr & ~(0xf << shift)) | (crval << shift); 597 } 598 599 static nokprobe_inline int trap_compare(long v1, long v2) 600 { 601 int ret = 0; 602 603 if (v1 < v2) 604 ret |= 0x10; 605 else if (v1 > v2) 606 ret |= 0x08; 607 else 608 ret |= 0x04; 609 if ((unsigned long)v1 < (unsigned long)v2) 610 ret |= 0x02; 611 else if ((unsigned long)v1 > (unsigned long)v2) 612 ret |= 0x01; 613 return ret; 614 } 615 616 /* 617 * Elements of 32-bit rotate and mask instructions. 618 */ 619 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \ 620 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb))) 621 #ifdef __powerpc64__ 622 #define MASK64_L(mb) (~0UL >> (mb)) 623 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me)) 624 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb))) 625 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32)) 626 #else 627 #define DATA32(x) (x) 628 #endif 629 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x)) 630 631 /* 632 * Decode an instruction, and execute it if that can be done just by 633 * modifying *regs (i.e. integer arithmetic and logical instructions, 634 * branches, and barrier instructions). 635 * Returns 1 if the instruction has been executed, or 0 if not. 636 * Sets *op to indicate what the instruction does. 637 */ 638 int analyse_instr(struct instruction_op *op, struct pt_regs *regs, 639 unsigned int instr) 640 { 641 unsigned int opcode, ra, rb, rd, spr, u; 642 unsigned long int imm; 643 unsigned long int val, val2; 644 unsigned int mb, me, sh; 645 long ival; 646 647 op->type = COMPUTE; 648 649 opcode = instr >> 26; 650 switch (opcode) { 651 case 16: /* bc */ 652 op->type = BRANCH; 653 imm = (signed short)(instr & 0xfffc); 654 if ((instr & 2) == 0) 655 imm += regs->nip; 656 regs->nip += 4; 657 regs->nip = truncate_if_32bit(regs->msr, regs->nip); 658 if (instr & 1) 659 regs->link = regs->nip; 660 if (branch_taken(instr, regs)) 661 regs->nip = truncate_if_32bit(regs->msr, imm); 662 return 1; 663 #ifdef CONFIG_PPC64 664 case 17: /* sc */ 665 if ((instr & 0xfe2) == 2) 666 op->type = SYSCALL; 667 else 668 op->type = UNKNOWN; 669 return 0; 670 #endif 671 case 18: /* b */ 672 op->type = BRANCH; 673 imm = instr & 0x03fffffc; 674 if (imm & 0x02000000) 675 imm -= 0x04000000; 676 if ((instr & 2) == 0) 677 imm += regs->nip; 678 if (instr & 1) 679 regs->link = truncate_if_32bit(regs->msr, regs->nip + 4); 680 imm = truncate_if_32bit(regs->msr, imm); 681 regs->nip = imm; 682 return 1; 683 case 19: 684 switch ((instr >> 1) & 0x3ff) { 685 case 0: /* mcrf */ 686 rd = (instr >> 21) & 0x1c; 687 ra = (instr >> 16) & 0x1c; 688 val = (regs->ccr >> ra) & 0xf; 689 regs->ccr = (regs->ccr & ~(0xfUL << rd)) | (val << rd); 690 goto instr_done; 691 692 case 16: /* bclr */ 693 case 528: /* bcctr */ 694 op->type = BRANCH; 695 imm = (instr & 0x400)? regs->ctr: regs->link; 696 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4); 697 imm = truncate_if_32bit(regs->msr, imm); 698 if (instr & 1) 699 regs->link = regs->nip; 700 if (branch_taken(instr, regs)) 701 regs->nip = imm; 702 return 1; 703 704 case 18: /* rfid, scary */ 705 if (regs->msr & MSR_PR) 706 goto priv; 707 op->type = RFI; 708 return 0; 709 710 case 150: /* isync */ 711 op->type = BARRIER; 712 isync(); 713 goto instr_done; 714 715 case 33: /* crnor */ 716 case 129: /* crandc */ 717 case 193: /* crxor */ 718 case 225: /* crnand */ 719 case 257: /* crand */ 720 case 289: /* creqv */ 721 case 417: /* crorc */ 722 case 449: /* cror */ 723 ra = (instr >> 16) & 0x1f; 724 rb = (instr >> 11) & 0x1f; 725 rd = (instr >> 21) & 0x1f; 726 ra = (regs->ccr >> (31 - ra)) & 1; 727 rb = (regs->ccr >> (31 - rb)) & 1; 728 val = (instr >> (6 + ra * 2 + rb)) & 1; 729 regs->ccr = (regs->ccr & ~(1UL << (31 - rd))) | 730 (val << (31 - rd)); 731 goto instr_done; 732 } 733 break; 734 case 31: 735 switch ((instr >> 1) & 0x3ff) { 736 case 598: /* sync */ 737 op->type = BARRIER; 738 #ifdef __powerpc64__ 739 switch ((instr >> 21) & 3) { 740 case 1: /* lwsync */ 741 asm volatile("lwsync" : : : "memory"); 742 goto instr_done; 743 case 2: /* ptesync */ 744 asm volatile("ptesync" : : : "memory"); 745 goto instr_done; 746 } 747 #endif 748 mb(); 749 goto instr_done; 750 751 case 854: /* eieio */ 752 op->type = BARRIER; 753 eieio(); 754 goto instr_done; 755 } 756 break; 757 } 758 759 /* Following cases refer to regs->gpr[], so we need all regs */ 760 if (!FULL_REGS(regs)) 761 return 0; 762 763 rd = (instr >> 21) & 0x1f; 764 ra = (instr >> 16) & 0x1f; 765 rb = (instr >> 11) & 0x1f; 766 767 switch (opcode) { 768 #ifdef __powerpc64__ 769 case 2: /* tdi */ 770 if (rd & trap_compare(regs->gpr[ra], (short) instr)) 771 goto trap; 772 goto instr_done; 773 #endif 774 case 3: /* twi */ 775 if (rd & trap_compare((int)regs->gpr[ra], (short) instr)) 776 goto trap; 777 goto instr_done; 778 779 case 7: /* mulli */ 780 regs->gpr[rd] = regs->gpr[ra] * (short) instr; 781 goto instr_done; 782 783 case 8: /* subfic */ 784 imm = (short) instr; 785 add_with_carry(regs, rd, ~regs->gpr[ra], imm, 1); 786 goto instr_done; 787 788 case 10: /* cmpli */ 789 imm = (unsigned short) instr; 790 val = regs->gpr[ra]; 791 #ifdef __powerpc64__ 792 if ((rd & 1) == 0) 793 val = (unsigned int) val; 794 #endif 795 do_cmp_unsigned(regs, val, imm, rd >> 2); 796 goto instr_done; 797 798 case 11: /* cmpi */ 799 imm = (short) instr; 800 val = regs->gpr[ra]; 801 #ifdef __powerpc64__ 802 if ((rd & 1) == 0) 803 val = (int) val; 804 #endif 805 do_cmp_signed(regs, val, imm, rd >> 2); 806 goto instr_done; 807 808 case 12: /* addic */ 809 imm = (short) instr; 810 add_with_carry(regs, rd, regs->gpr[ra], imm, 0); 811 goto instr_done; 812 813 case 13: /* addic. */ 814 imm = (short) instr; 815 add_with_carry(regs, rd, regs->gpr[ra], imm, 0); 816 set_cr0(regs, rd); 817 goto instr_done; 818 819 case 14: /* addi */ 820 imm = (short) instr; 821 if (ra) 822 imm += regs->gpr[ra]; 823 regs->gpr[rd] = imm; 824 goto instr_done; 825 826 case 15: /* addis */ 827 imm = ((short) instr) << 16; 828 if (ra) 829 imm += regs->gpr[ra]; 830 regs->gpr[rd] = imm; 831 goto instr_done; 832 833 case 20: /* rlwimi */ 834 mb = (instr >> 6) & 0x1f; 835 me = (instr >> 1) & 0x1f; 836 val = DATA32(regs->gpr[rd]); 837 imm = MASK32(mb, me); 838 regs->gpr[ra] = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm); 839 goto logical_done; 840 841 case 21: /* rlwinm */ 842 mb = (instr >> 6) & 0x1f; 843 me = (instr >> 1) & 0x1f; 844 val = DATA32(regs->gpr[rd]); 845 regs->gpr[ra] = ROTATE(val, rb) & MASK32(mb, me); 846 goto logical_done; 847 848 case 23: /* rlwnm */ 849 mb = (instr >> 6) & 0x1f; 850 me = (instr >> 1) & 0x1f; 851 rb = regs->gpr[rb] & 0x1f; 852 val = DATA32(regs->gpr[rd]); 853 regs->gpr[ra] = ROTATE(val, rb) & MASK32(mb, me); 854 goto logical_done; 855 856 case 24: /* ori */ 857 imm = (unsigned short) instr; 858 regs->gpr[ra] = regs->gpr[rd] | imm; 859 goto instr_done; 860 861 case 25: /* oris */ 862 imm = (unsigned short) instr; 863 regs->gpr[ra] = regs->gpr[rd] | (imm << 16); 864 goto instr_done; 865 866 case 26: /* xori */ 867 imm = (unsigned short) instr; 868 regs->gpr[ra] = regs->gpr[rd] ^ imm; 869 goto instr_done; 870 871 case 27: /* xoris */ 872 imm = (unsigned short) instr; 873 regs->gpr[ra] = regs->gpr[rd] ^ (imm << 16); 874 goto instr_done; 875 876 case 28: /* andi. */ 877 imm = (unsigned short) instr; 878 regs->gpr[ra] = regs->gpr[rd] & imm; 879 set_cr0(regs, ra); 880 goto instr_done; 881 882 case 29: /* andis. */ 883 imm = (unsigned short) instr; 884 regs->gpr[ra] = regs->gpr[rd] & (imm << 16); 885 set_cr0(regs, ra); 886 goto instr_done; 887 888 #ifdef __powerpc64__ 889 case 30: /* rld* */ 890 mb = ((instr >> 6) & 0x1f) | (instr & 0x20); 891 val = regs->gpr[rd]; 892 if ((instr & 0x10) == 0) { 893 sh = rb | ((instr & 2) << 4); 894 val = ROTATE(val, sh); 895 switch ((instr >> 2) & 3) { 896 case 0: /* rldicl */ 897 regs->gpr[ra] = val & MASK64_L(mb); 898 goto logical_done; 899 case 1: /* rldicr */ 900 regs->gpr[ra] = val & MASK64_R(mb); 901 goto logical_done; 902 case 2: /* rldic */ 903 regs->gpr[ra] = val & MASK64(mb, 63 - sh); 904 goto logical_done; 905 case 3: /* rldimi */ 906 imm = MASK64(mb, 63 - sh); 907 regs->gpr[ra] = (regs->gpr[ra] & ~imm) | 908 (val & imm); 909 goto logical_done; 910 } 911 } else { 912 sh = regs->gpr[rb] & 0x3f; 913 val = ROTATE(val, sh); 914 switch ((instr >> 1) & 7) { 915 case 0: /* rldcl */ 916 regs->gpr[ra] = val & MASK64_L(mb); 917 goto logical_done; 918 case 1: /* rldcr */ 919 regs->gpr[ra] = val & MASK64_R(mb); 920 goto logical_done; 921 } 922 } 923 #endif 924 break; /* illegal instruction */ 925 926 case 31: 927 switch ((instr >> 1) & 0x3ff) { 928 case 4: /* tw */ 929 if (rd == 0x1f || 930 (rd & trap_compare((int)regs->gpr[ra], 931 (int)regs->gpr[rb]))) 932 goto trap; 933 goto instr_done; 934 #ifdef __powerpc64__ 935 case 68: /* td */ 936 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb])) 937 goto trap; 938 goto instr_done; 939 #endif 940 case 83: /* mfmsr */ 941 if (regs->msr & MSR_PR) 942 goto priv; 943 op->type = MFMSR; 944 op->reg = rd; 945 return 0; 946 case 146: /* mtmsr */ 947 if (regs->msr & MSR_PR) 948 goto priv; 949 op->type = MTMSR; 950 op->reg = rd; 951 op->val = 0xffffffff & ~(MSR_ME | MSR_LE); 952 return 0; 953 #ifdef CONFIG_PPC64 954 case 178: /* mtmsrd */ 955 if (regs->msr & MSR_PR) 956 goto priv; 957 op->type = MTMSR; 958 op->reg = rd; 959 /* only MSR_EE and MSR_RI get changed if bit 15 set */ 960 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */ 961 imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL; 962 op->val = imm; 963 return 0; 964 #endif 965 966 case 19: /* mfcr */ 967 regs->gpr[rd] = regs->ccr; 968 regs->gpr[rd] &= 0xffffffffUL; 969 goto instr_done; 970 971 case 144: /* mtcrf */ 972 imm = 0xf0000000UL; 973 val = regs->gpr[rd]; 974 for (sh = 0; sh < 8; ++sh) { 975 if (instr & (0x80000 >> sh)) 976 regs->ccr = (regs->ccr & ~imm) | 977 (val & imm); 978 imm >>= 4; 979 } 980 goto instr_done; 981 982 case 339: /* mfspr */ 983 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0); 984 switch (spr) { 985 case SPRN_XER: /* mfxer */ 986 regs->gpr[rd] = regs->xer; 987 regs->gpr[rd] &= 0xffffffffUL; 988 goto instr_done; 989 case SPRN_LR: /* mflr */ 990 regs->gpr[rd] = regs->link; 991 goto instr_done; 992 case SPRN_CTR: /* mfctr */ 993 regs->gpr[rd] = regs->ctr; 994 goto instr_done; 995 default: 996 op->type = MFSPR; 997 op->reg = rd; 998 op->spr = spr; 999 return 0; 1000 } 1001 break; 1002 1003 case 467: /* mtspr */ 1004 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0); 1005 switch (spr) { 1006 case SPRN_XER: /* mtxer */ 1007 regs->xer = (regs->gpr[rd] & 0xffffffffUL); 1008 goto instr_done; 1009 case SPRN_LR: /* mtlr */ 1010 regs->link = regs->gpr[rd]; 1011 goto instr_done; 1012 case SPRN_CTR: /* mtctr */ 1013 regs->ctr = regs->gpr[rd]; 1014 goto instr_done; 1015 default: 1016 op->type = MTSPR; 1017 op->val = regs->gpr[rd]; 1018 op->spr = spr; 1019 return 0; 1020 } 1021 break; 1022 1023 /* 1024 * Compare instructions 1025 */ 1026 case 0: /* cmp */ 1027 val = regs->gpr[ra]; 1028 val2 = regs->gpr[rb]; 1029 #ifdef __powerpc64__ 1030 if ((rd & 1) == 0) { 1031 /* word (32-bit) compare */ 1032 val = (int) val; 1033 val2 = (int) val2; 1034 } 1035 #endif 1036 do_cmp_signed(regs, val, val2, rd >> 2); 1037 goto instr_done; 1038 1039 case 32: /* cmpl */ 1040 val = regs->gpr[ra]; 1041 val2 = regs->gpr[rb]; 1042 #ifdef __powerpc64__ 1043 if ((rd & 1) == 0) { 1044 /* word (32-bit) compare */ 1045 val = (unsigned int) val; 1046 val2 = (unsigned int) val2; 1047 } 1048 #endif 1049 do_cmp_unsigned(regs, val, val2, rd >> 2); 1050 goto instr_done; 1051 1052 /* 1053 * Arithmetic instructions 1054 */ 1055 case 8: /* subfc */ 1056 add_with_carry(regs, rd, ~regs->gpr[ra], 1057 regs->gpr[rb], 1); 1058 goto arith_done; 1059 #ifdef __powerpc64__ 1060 case 9: /* mulhdu */ 1061 asm("mulhdu %0,%1,%2" : "=r" (regs->gpr[rd]) : 1062 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1063 goto arith_done; 1064 #endif 1065 case 10: /* addc */ 1066 add_with_carry(regs, rd, regs->gpr[ra], 1067 regs->gpr[rb], 0); 1068 goto arith_done; 1069 1070 case 11: /* mulhwu */ 1071 asm("mulhwu %0,%1,%2" : "=r" (regs->gpr[rd]) : 1072 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1073 goto arith_done; 1074 1075 case 40: /* subf */ 1076 regs->gpr[rd] = regs->gpr[rb] - regs->gpr[ra]; 1077 goto arith_done; 1078 #ifdef __powerpc64__ 1079 case 73: /* mulhd */ 1080 asm("mulhd %0,%1,%2" : "=r" (regs->gpr[rd]) : 1081 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1082 goto arith_done; 1083 #endif 1084 case 75: /* mulhw */ 1085 asm("mulhw %0,%1,%2" : "=r" (regs->gpr[rd]) : 1086 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); 1087 goto arith_done; 1088 1089 case 104: /* neg */ 1090 regs->gpr[rd] = -regs->gpr[ra]; 1091 goto arith_done; 1092 1093 case 136: /* subfe */ 1094 add_with_carry(regs, rd, ~regs->gpr[ra], regs->gpr[rb], 1095 regs->xer & XER_CA); 1096 goto arith_done; 1097 1098 case 138: /* adde */ 1099 add_with_carry(regs, rd, regs->gpr[ra], regs->gpr[rb], 1100 regs->xer & XER_CA); 1101 goto arith_done; 1102 1103 case 200: /* subfze */ 1104 add_with_carry(regs, rd, ~regs->gpr[ra], 0L, 1105 regs->xer & XER_CA); 1106 goto arith_done; 1107 1108 case 202: /* addze */ 1109 add_with_carry(regs, rd, regs->gpr[ra], 0L, 1110 regs->xer & XER_CA); 1111 goto arith_done; 1112 1113 case 232: /* subfme */ 1114 add_with_carry(regs, rd, ~regs->gpr[ra], -1L, 1115 regs->xer & XER_CA); 1116 goto arith_done; 1117 #ifdef __powerpc64__ 1118 case 233: /* mulld */ 1119 regs->gpr[rd] = regs->gpr[ra] * regs->gpr[rb]; 1120 goto arith_done; 1121 #endif 1122 case 234: /* addme */ 1123 add_with_carry(regs, rd, regs->gpr[ra], -1L, 1124 regs->xer & XER_CA); 1125 goto arith_done; 1126 1127 case 235: /* mullw */ 1128 regs->gpr[rd] = (unsigned int) regs->gpr[ra] * 1129 (unsigned int) regs->gpr[rb]; 1130 goto arith_done; 1131 1132 case 266: /* add */ 1133 regs->gpr[rd] = regs->gpr[ra] + regs->gpr[rb]; 1134 goto arith_done; 1135 #ifdef __powerpc64__ 1136 case 457: /* divdu */ 1137 regs->gpr[rd] = regs->gpr[ra] / regs->gpr[rb]; 1138 goto arith_done; 1139 #endif 1140 case 459: /* divwu */ 1141 regs->gpr[rd] = (unsigned int) regs->gpr[ra] / 1142 (unsigned int) regs->gpr[rb]; 1143 goto arith_done; 1144 #ifdef __powerpc64__ 1145 case 489: /* divd */ 1146 regs->gpr[rd] = (long int) regs->gpr[ra] / 1147 (long int) regs->gpr[rb]; 1148 goto arith_done; 1149 #endif 1150 case 491: /* divw */ 1151 regs->gpr[rd] = (int) regs->gpr[ra] / 1152 (int) regs->gpr[rb]; 1153 goto arith_done; 1154 1155 1156 /* 1157 * Logical instructions 1158 */ 1159 case 26: /* cntlzw */ 1160 asm("cntlzw %0,%1" : "=r" (regs->gpr[ra]) : 1161 "r" (regs->gpr[rd])); 1162 goto logical_done; 1163 #ifdef __powerpc64__ 1164 case 58: /* cntlzd */ 1165 asm("cntlzd %0,%1" : "=r" (regs->gpr[ra]) : 1166 "r" (regs->gpr[rd])); 1167 goto logical_done; 1168 #endif 1169 case 28: /* and */ 1170 regs->gpr[ra] = regs->gpr[rd] & regs->gpr[rb]; 1171 goto logical_done; 1172 1173 case 60: /* andc */ 1174 regs->gpr[ra] = regs->gpr[rd] & ~regs->gpr[rb]; 1175 goto logical_done; 1176 1177 case 124: /* nor */ 1178 regs->gpr[ra] = ~(regs->gpr[rd] | regs->gpr[rb]); 1179 goto logical_done; 1180 1181 case 284: /* xor */ 1182 regs->gpr[ra] = ~(regs->gpr[rd] ^ regs->gpr[rb]); 1183 goto logical_done; 1184 1185 case 316: /* xor */ 1186 regs->gpr[ra] = regs->gpr[rd] ^ regs->gpr[rb]; 1187 goto logical_done; 1188 1189 case 412: /* orc */ 1190 regs->gpr[ra] = regs->gpr[rd] | ~regs->gpr[rb]; 1191 goto logical_done; 1192 1193 case 444: /* or */ 1194 regs->gpr[ra] = regs->gpr[rd] | regs->gpr[rb]; 1195 goto logical_done; 1196 1197 case 476: /* nand */ 1198 regs->gpr[ra] = ~(regs->gpr[rd] & regs->gpr[rb]); 1199 goto logical_done; 1200 1201 case 922: /* extsh */ 1202 regs->gpr[ra] = (signed short) regs->gpr[rd]; 1203 goto logical_done; 1204 1205 case 954: /* extsb */ 1206 regs->gpr[ra] = (signed char) regs->gpr[rd]; 1207 goto logical_done; 1208 #ifdef __powerpc64__ 1209 case 986: /* extsw */ 1210 regs->gpr[ra] = (signed int) regs->gpr[rd]; 1211 goto logical_done; 1212 #endif 1213 1214 /* 1215 * Shift instructions 1216 */ 1217 case 24: /* slw */ 1218 sh = regs->gpr[rb] & 0x3f; 1219 if (sh < 32) 1220 regs->gpr[ra] = (regs->gpr[rd] << sh) & 0xffffffffUL; 1221 else 1222 regs->gpr[ra] = 0; 1223 goto logical_done; 1224 1225 case 536: /* srw */ 1226 sh = regs->gpr[rb] & 0x3f; 1227 if (sh < 32) 1228 regs->gpr[ra] = (regs->gpr[rd] & 0xffffffffUL) >> sh; 1229 else 1230 regs->gpr[ra] = 0; 1231 goto logical_done; 1232 1233 case 792: /* sraw */ 1234 sh = regs->gpr[rb] & 0x3f; 1235 ival = (signed int) regs->gpr[rd]; 1236 regs->gpr[ra] = ival >> (sh < 32 ? sh : 31); 1237 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0)) 1238 regs->xer |= XER_CA; 1239 else 1240 regs->xer &= ~XER_CA; 1241 goto logical_done; 1242 1243 case 824: /* srawi */ 1244 sh = rb; 1245 ival = (signed int) regs->gpr[rd]; 1246 regs->gpr[ra] = ival >> sh; 1247 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) 1248 regs->xer |= XER_CA; 1249 else 1250 regs->xer &= ~XER_CA; 1251 goto logical_done; 1252 1253 #ifdef __powerpc64__ 1254 case 27: /* sld */ 1255 sh = regs->gpr[rb] & 0x7f; 1256 if (sh < 64) 1257 regs->gpr[ra] = regs->gpr[rd] << sh; 1258 else 1259 regs->gpr[ra] = 0; 1260 goto logical_done; 1261 1262 case 539: /* srd */ 1263 sh = regs->gpr[rb] & 0x7f; 1264 if (sh < 64) 1265 regs->gpr[ra] = regs->gpr[rd] >> sh; 1266 else 1267 regs->gpr[ra] = 0; 1268 goto logical_done; 1269 1270 case 794: /* srad */ 1271 sh = regs->gpr[rb] & 0x7f; 1272 ival = (signed long int) regs->gpr[rd]; 1273 regs->gpr[ra] = ival >> (sh < 64 ? sh : 63); 1274 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0)) 1275 regs->xer |= XER_CA; 1276 else 1277 regs->xer &= ~XER_CA; 1278 goto logical_done; 1279 1280 case 826: /* sradi with sh_5 = 0 */ 1281 case 827: /* sradi with sh_5 = 1 */ 1282 sh = rb | ((instr & 2) << 4); 1283 ival = (signed long int) regs->gpr[rd]; 1284 regs->gpr[ra] = ival >> sh; 1285 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) 1286 regs->xer |= XER_CA; 1287 else 1288 regs->xer &= ~XER_CA; 1289 goto logical_done; 1290 #endif /* __powerpc64__ */ 1291 1292 /* 1293 * Cache instructions 1294 */ 1295 case 54: /* dcbst */ 1296 op->type = MKOP(CACHEOP, DCBST, 0); 1297 op->ea = xform_ea(instr, regs); 1298 return 0; 1299 1300 case 86: /* dcbf */ 1301 op->type = MKOP(CACHEOP, DCBF, 0); 1302 op->ea = xform_ea(instr, regs); 1303 return 0; 1304 1305 case 246: /* dcbtst */ 1306 op->type = MKOP(CACHEOP, DCBTST, 0); 1307 op->ea = xform_ea(instr, regs); 1308 op->reg = rd; 1309 return 0; 1310 1311 case 278: /* dcbt */ 1312 op->type = MKOP(CACHEOP, DCBTST, 0); 1313 op->ea = xform_ea(instr, regs); 1314 op->reg = rd; 1315 return 0; 1316 1317 case 982: /* icbi */ 1318 op->type = MKOP(CACHEOP, ICBI, 0); 1319 op->ea = xform_ea(instr, regs); 1320 return 0; 1321 } 1322 break; 1323 } 1324 1325 /* 1326 * Loads and stores. 1327 */ 1328 op->type = UNKNOWN; 1329 op->update_reg = ra; 1330 op->reg = rd; 1331 op->val = regs->gpr[rd]; 1332 u = (instr >> 20) & UPDATE; 1333 1334 switch (opcode) { 1335 case 31: 1336 u = instr & UPDATE; 1337 op->ea = xform_ea(instr, regs); 1338 switch ((instr >> 1) & 0x3ff) { 1339 case 20: /* lwarx */ 1340 op->type = MKOP(LARX, 0, 4); 1341 break; 1342 1343 case 150: /* stwcx. */ 1344 op->type = MKOP(STCX, 0, 4); 1345 break; 1346 1347 #ifdef __powerpc64__ 1348 case 84: /* ldarx */ 1349 op->type = MKOP(LARX, 0, 8); 1350 break; 1351 1352 case 214: /* stdcx. */ 1353 op->type = MKOP(STCX, 0, 8); 1354 break; 1355 1356 case 21: /* ldx */ 1357 case 53: /* ldux */ 1358 op->type = MKOP(LOAD, u, 8); 1359 break; 1360 #endif 1361 1362 case 23: /* lwzx */ 1363 case 55: /* lwzux */ 1364 op->type = MKOP(LOAD, u, 4); 1365 break; 1366 1367 case 87: /* lbzx */ 1368 case 119: /* lbzux */ 1369 op->type = MKOP(LOAD, u, 1); 1370 break; 1371 1372 #ifdef CONFIG_ALTIVEC 1373 case 103: /* lvx */ 1374 case 359: /* lvxl */ 1375 if (!(regs->msr & MSR_VEC)) 1376 goto vecunavail; 1377 op->type = MKOP(LOAD_VMX, 0, 16); 1378 break; 1379 1380 case 231: /* stvx */ 1381 case 487: /* stvxl */ 1382 if (!(regs->msr & MSR_VEC)) 1383 goto vecunavail; 1384 op->type = MKOP(STORE_VMX, 0, 16); 1385 break; 1386 #endif /* CONFIG_ALTIVEC */ 1387 1388 #ifdef __powerpc64__ 1389 case 149: /* stdx */ 1390 case 181: /* stdux */ 1391 op->type = MKOP(STORE, u, 8); 1392 break; 1393 #endif 1394 1395 case 151: /* stwx */ 1396 case 183: /* stwux */ 1397 op->type = MKOP(STORE, u, 4); 1398 break; 1399 1400 case 215: /* stbx */ 1401 case 247: /* stbux */ 1402 op->type = MKOP(STORE, u, 1); 1403 break; 1404 1405 case 279: /* lhzx */ 1406 case 311: /* lhzux */ 1407 op->type = MKOP(LOAD, u, 2); 1408 break; 1409 1410 #ifdef __powerpc64__ 1411 case 341: /* lwax */ 1412 case 373: /* lwaux */ 1413 op->type = MKOP(LOAD, SIGNEXT | u, 4); 1414 break; 1415 #endif 1416 1417 case 343: /* lhax */ 1418 case 375: /* lhaux */ 1419 op->type = MKOP(LOAD, SIGNEXT | u, 2); 1420 break; 1421 1422 case 407: /* sthx */ 1423 case 439: /* sthux */ 1424 op->type = MKOP(STORE, u, 2); 1425 break; 1426 1427 #ifdef __powerpc64__ 1428 case 532: /* ldbrx */ 1429 op->type = MKOP(LOAD, BYTEREV, 8); 1430 break; 1431 1432 #endif 1433 case 533: /* lswx */ 1434 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f); 1435 break; 1436 1437 case 534: /* lwbrx */ 1438 op->type = MKOP(LOAD, BYTEREV, 4); 1439 break; 1440 1441 case 597: /* lswi */ 1442 if (rb == 0) 1443 rb = 32; /* # bytes to load */ 1444 op->type = MKOP(LOAD_MULTI, 0, rb); 1445 op->ea = 0; 1446 if (ra) 1447 op->ea = truncate_if_32bit(regs->msr, 1448 regs->gpr[ra]); 1449 break; 1450 1451 #ifdef CONFIG_PPC_FPU 1452 case 535: /* lfsx */ 1453 case 567: /* lfsux */ 1454 if (!(regs->msr & MSR_FP)) 1455 goto fpunavail; 1456 op->type = MKOP(LOAD_FP, u, 4); 1457 break; 1458 1459 case 599: /* lfdx */ 1460 case 631: /* lfdux */ 1461 if (!(regs->msr & MSR_FP)) 1462 goto fpunavail; 1463 op->type = MKOP(LOAD_FP, u, 8); 1464 break; 1465 1466 case 663: /* stfsx */ 1467 case 695: /* stfsux */ 1468 if (!(regs->msr & MSR_FP)) 1469 goto fpunavail; 1470 op->type = MKOP(STORE_FP, u, 4); 1471 break; 1472 1473 case 727: /* stfdx */ 1474 case 759: /* stfdux */ 1475 if (!(regs->msr & MSR_FP)) 1476 goto fpunavail; 1477 op->type = MKOP(STORE_FP, u, 8); 1478 break; 1479 #endif 1480 1481 #ifdef __powerpc64__ 1482 case 660: /* stdbrx */ 1483 op->type = MKOP(STORE, BYTEREV, 8); 1484 op->val = byterev_8(regs->gpr[rd]); 1485 break; 1486 1487 #endif 1488 case 661: /* stswx */ 1489 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f); 1490 break; 1491 1492 case 662: /* stwbrx */ 1493 op->type = MKOP(STORE, BYTEREV, 4); 1494 op->val = byterev_4(regs->gpr[rd]); 1495 break; 1496 1497 case 725: 1498 if (rb == 0) 1499 rb = 32; /* # bytes to store */ 1500 op->type = MKOP(STORE_MULTI, 0, rb); 1501 op->ea = 0; 1502 if (ra) 1503 op->ea = truncate_if_32bit(regs->msr, 1504 regs->gpr[ra]); 1505 break; 1506 1507 case 790: /* lhbrx */ 1508 op->type = MKOP(LOAD, BYTEREV, 2); 1509 break; 1510 1511 case 918: /* sthbrx */ 1512 op->type = MKOP(STORE, BYTEREV, 2); 1513 op->val = byterev_2(regs->gpr[rd]); 1514 break; 1515 1516 #ifdef CONFIG_VSX 1517 case 844: /* lxvd2x */ 1518 case 876: /* lxvd2ux */ 1519 if (!(regs->msr & MSR_VSX)) 1520 goto vsxunavail; 1521 op->reg = rd | ((instr & 1) << 5); 1522 op->type = MKOP(LOAD_VSX, u, 16); 1523 break; 1524 1525 case 972: /* stxvd2x */ 1526 case 1004: /* stxvd2ux */ 1527 if (!(regs->msr & MSR_VSX)) 1528 goto vsxunavail; 1529 op->reg = rd | ((instr & 1) << 5); 1530 op->type = MKOP(STORE_VSX, u, 16); 1531 break; 1532 1533 #endif /* CONFIG_VSX */ 1534 } 1535 break; 1536 1537 case 32: /* lwz */ 1538 case 33: /* lwzu */ 1539 op->type = MKOP(LOAD, u, 4); 1540 op->ea = dform_ea(instr, regs); 1541 break; 1542 1543 case 34: /* lbz */ 1544 case 35: /* lbzu */ 1545 op->type = MKOP(LOAD, u, 1); 1546 op->ea = dform_ea(instr, regs); 1547 break; 1548 1549 case 36: /* stw */ 1550 case 37: /* stwu */ 1551 op->type = MKOP(STORE, u, 4); 1552 op->ea = dform_ea(instr, regs); 1553 break; 1554 1555 case 38: /* stb */ 1556 case 39: /* stbu */ 1557 op->type = MKOP(STORE, u, 1); 1558 op->ea = dform_ea(instr, regs); 1559 break; 1560 1561 case 40: /* lhz */ 1562 case 41: /* lhzu */ 1563 op->type = MKOP(LOAD, u, 2); 1564 op->ea = dform_ea(instr, regs); 1565 break; 1566 1567 case 42: /* lha */ 1568 case 43: /* lhau */ 1569 op->type = MKOP(LOAD, SIGNEXT | u, 2); 1570 op->ea = dform_ea(instr, regs); 1571 break; 1572 1573 case 44: /* sth */ 1574 case 45: /* sthu */ 1575 op->type = MKOP(STORE, u, 2); 1576 op->ea = dform_ea(instr, regs); 1577 break; 1578 1579 case 46: /* lmw */ 1580 if (ra >= rd) 1581 break; /* invalid form, ra in range to load */ 1582 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd)); 1583 op->ea = dform_ea(instr, regs); 1584 break; 1585 1586 case 47: /* stmw */ 1587 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd)); 1588 op->ea = dform_ea(instr, regs); 1589 break; 1590 1591 #ifdef CONFIG_PPC_FPU 1592 case 48: /* lfs */ 1593 case 49: /* lfsu */ 1594 if (!(regs->msr & MSR_FP)) 1595 goto fpunavail; 1596 op->type = MKOP(LOAD_FP, u, 4); 1597 op->ea = dform_ea(instr, regs); 1598 break; 1599 1600 case 50: /* lfd */ 1601 case 51: /* lfdu */ 1602 if (!(regs->msr & MSR_FP)) 1603 goto fpunavail; 1604 op->type = MKOP(LOAD_FP, u, 8); 1605 op->ea = dform_ea(instr, regs); 1606 break; 1607 1608 case 52: /* stfs */ 1609 case 53: /* stfsu */ 1610 if (!(regs->msr & MSR_FP)) 1611 goto fpunavail; 1612 op->type = MKOP(STORE_FP, u, 4); 1613 op->ea = dform_ea(instr, regs); 1614 break; 1615 1616 case 54: /* stfd */ 1617 case 55: /* stfdu */ 1618 if (!(regs->msr & MSR_FP)) 1619 goto fpunavail; 1620 op->type = MKOP(STORE_FP, u, 8); 1621 op->ea = dform_ea(instr, regs); 1622 break; 1623 #endif 1624 1625 #ifdef __powerpc64__ 1626 case 58: /* ld[u], lwa */ 1627 op->ea = dsform_ea(instr, regs); 1628 switch (instr & 3) { 1629 case 0: /* ld */ 1630 op->type = MKOP(LOAD, 0, 8); 1631 break; 1632 case 1: /* ldu */ 1633 op->type = MKOP(LOAD, UPDATE, 8); 1634 break; 1635 case 2: /* lwa */ 1636 op->type = MKOP(LOAD, SIGNEXT, 4); 1637 break; 1638 } 1639 break; 1640 1641 case 62: /* std[u] */ 1642 op->ea = dsform_ea(instr, regs); 1643 switch (instr & 3) { 1644 case 0: /* std */ 1645 op->type = MKOP(STORE, 0, 8); 1646 break; 1647 case 1: /* stdu */ 1648 op->type = MKOP(STORE, UPDATE, 8); 1649 break; 1650 } 1651 break; 1652 #endif /* __powerpc64__ */ 1653 1654 } 1655 return 0; 1656 1657 logical_done: 1658 if (instr & 1) 1659 set_cr0(regs, ra); 1660 goto instr_done; 1661 1662 arith_done: 1663 if (instr & 1) 1664 set_cr0(regs, rd); 1665 1666 instr_done: 1667 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4); 1668 return 1; 1669 1670 priv: 1671 op->type = INTERRUPT | 0x700; 1672 op->val = SRR1_PROGPRIV; 1673 return 0; 1674 1675 trap: 1676 op->type = INTERRUPT | 0x700; 1677 op->val = SRR1_PROGTRAP; 1678 return 0; 1679 1680 #ifdef CONFIG_PPC_FPU 1681 fpunavail: 1682 op->type = INTERRUPT | 0x800; 1683 return 0; 1684 #endif 1685 1686 #ifdef CONFIG_ALTIVEC 1687 vecunavail: 1688 op->type = INTERRUPT | 0xf20; 1689 return 0; 1690 #endif 1691 1692 #ifdef CONFIG_VSX 1693 vsxunavail: 1694 op->type = INTERRUPT | 0xf40; 1695 return 0; 1696 #endif 1697 } 1698 EXPORT_SYMBOL_GPL(analyse_instr); 1699 NOKPROBE_SYMBOL(analyse_instr); 1700 1701 /* 1702 * For PPC32 we always use stwu with r1 to change the stack pointer. 1703 * So this emulated store may corrupt the exception frame, now we 1704 * have to provide the exception frame trampoline, which is pushed 1705 * below the kprobed function stack. So we only update gpr[1] but 1706 * don't emulate the real store operation. We will do real store 1707 * operation safely in exception return code by checking this flag. 1708 */ 1709 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs) 1710 { 1711 #ifdef CONFIG_PPC32 1712 /* 1713 * Check if we will touch kernel stack overflow 1714 */ 1715 if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) { 1716 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n"); 1717 return -EINVAL; 1718 } 1719 #endif /* CONFIG_PPC32 */ 1720 /* 1721 * Check if we already set since that means we'll 1722 * lose the previous value. 1723 */ 1724 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE)); 1725 set_thread_flag(TIF_EMULATE_STACK_STORE); 1726 return 0; 1727 } 1728 1729 static nokprobe_inline void do_signext(unsigned long *valp, int size) 1730 { 1731 switch (size) { 1732 case 2: 1733 *valp = (signed short) *valp; 1734 break; 1735 case 4: 1736 *valp = (signed int) *valp; 1737 break; 1738 } 1739 } 1740 1741 static nokprobe_inline void do_byterev(unsigned long *valp, int size) 1742 { 1743 switch (size) { 1744 case 2: 1745 *valp = byterev_2(*valp); 1746 break; 1747 case 4: 1748 *valp = byterev_4(*valp); 1749 break; 1750 #ifdef __powerpc64__ 1751 case 8: 1752 *valp = byterev_8(*valp); 1753 break; 1754 #endif 1755 } 1756 } 1757 1758 /* 1759 * Emulate instructions that cause a transfer of control, 1760 * loads and stores, and a few other instructions. 1761 * Returns 1 if the step was emulated, 0 if not, 1762 * or -1 if the instruction is one that should not be stepped, 1763 * such as an rfid, or a mtmsrd that would clear MSR_RI. 1764 */ 1765 int emulate_step(struct pt_regs *regs, unsigned int instr) 1766 { 1767 struct instruction_op op; 1768 int r, err, size; 1769 unsigned long val; 1770 unsigned int cr; 1771 int i, rd, nb; 1772 1773 r = analyse_instr(&op, regs, instr); 1774 if (r != 0) 1775 return r; 1776 1777 err = 0; 1778 size = GETSIZE(op.type); 1779 switch (op.type & INSTR_TYPE_MASK) { 1780 case CACHEOP: 1781 if (!address_ok(regs, op.ea, 8)) 1782 return 0; 1783 switch (op.type & CACHEOP_MASK) { 1784 case DCBST: 1785 __cacheop_user_asmx(op.ea, err, "dcbst"); 1786 break; 1787 case DCBF: 1788 __cacheop_user_asmx(op.ea, err, "dcbf"); 1789 break; 1790 case DCBTST: 1791 if (op.reg == 0) 1792 prefetchw((void *) op.ea); 1793 break; 1794 case DCBT: 1795 if (op.reg == 0) 1796 prefetch((void *) op.ea); 1797 break; 1798 case ICBI: 1799 __cacheop_user_asmx(op.ea, err, "icbi"); 1800 break; 1801 } 1802 if (err) 1803 return 0; 1804 goto instr_done; 1805 1806 case LARX: 1807 if (op.ea & (size - 1)) 1808 break; /* can't handle misaligned */ 1809 if (!address_ok(regs, op.ea, size)) 1810 return 0; 1811 err = 0; 1812 switch (size) { 1813 case 4: 1814 __get_user_asmx(val, op.ea, err, "lwarx"); 1815 break; 1816 #ifdef __powerpc64__ 1817 case 8: 1818 __get_user_asmx(val, op.ea, err, "ldarx"); 1819 break; 1820 #endif 1821 default: 1822 return 0; 1823 } 1824 if (!err) 1825 regs->gpr[op.reg] = val; 1826 goto ldst_done; 1827 1828 case STCX: 1829 if (op.ea & (size - 1)) 1830 break; /* can't handle misaligned */ 1831 if (!address_ok(regs, op.ea, size)) 1832 return 0; 1833 err = 0; 1834 switch (size) { 1835 case 4: 1836 __put_user_asmx(op.val, op.ea, err, "stwcx.", cr); 1837 break; 1838 #ifdef __powerpc64__ 1839 case 8: 1840 __put_user_asmx(op.val, op.ea, err, "stdcx.", cr); 1841 break; 1842 #endif 1843 default: 1844 return 0; 1845 } 1846 if (!err) 1847 regs->ccr = (regs->ccr & 0x0fffffff) | 1848 (cr & 0xe0000000) | 1849 ((regs->xer >> 3) & 0x10000000); 1850 goto ldst_done; 1851 1852 case LOAD: 1853 err = read_mem(®s->gpr[op.reg], op.ea, size, regs); 1854 if (!err) { 1855 if (op.type & SIGNEXT) 1856 do_signext(®s->gpr[op.reg], size); 1857 if (op.type & BYTEREV) 1858 do_byterev(®s->gpr[op.reg], size); 1859 } 1860 goto ldst_done; 1861 1862 #ifdef CONFIG_PPC_FPU 1863 case LOAD_FP: 1864 if (size == 4) 1865 err = do_fp_load(op.reg, do_lfs, op.ea, size, regs); 1866 else 1867 err = do_fp_load(op.reg, do_lfd, op.ea, size, regs); 1868 goto ldst_done; 1869 #endif 1870 #ifdef CONFIG_ALTIVEC 1871 case LOAD_VMX: 1872 err = do_vec_load(op.reg, do_lvx, op.ea & ~0xfUL, regs); 1873 goto ldst_done; 1874 #endif 1875 #ifdef CONFIG_VSX 1876 case LOAD_VSX: 1877 err = do_vsx_load(op.reg, do_lxvd2x, op.ea, regs); 1878 goto ldst_done; 1879 #endif 1880 case LOAD_MULTI: 1881 if (regs->msr & MSR_LE) 1882 return 0; 1883 rd = op.reg; 1884 for (i = 0; i < size; i += 4) { 1885 nb = size - i; 1886 if (nb > 4) 1887 nb = 4; 1888 err = read_mem(®s->gpr[rd], op.ea, nb, regs); 1889 if (err) 1890 return 0; 1891 if (nb < 4) /* left-justify last bytes */ 1892 regs->gpr[rd] <<= 32 - 8 * nb; 1893 op.ea += 4; 1894 ++rd; 1895 } 1896 goto instr_done; 1897 1898 case STORE: 1899 if ((op.type & UPDATE) && size == sizeof(long) && 1900 op.reg == 1 && op.update_reg == 1 && 1901 !(regs->msr & MSR_PR) && 1902 op.ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) { 1903 err = handle_stack_update(op.ea, regs); 1904 goto ldst_done; 1905 } 1906 err = write_mem(op.val, op.ea, size, regs); 1907 goto ldst_done; 1908 1909 #ifdef CONFIG_PPC_FPU 1910 case STORE_FP: 1911 if (size == 4) 1912 err = do_fp_store(op.reg, do_stfs, op.ea, size, regs); 1913 else 1914 err = do_fp_store(op.reg, do_stfd, op.ea, size, regs); 1915 goto ldst_done; 1916 #endif 1917 #ifdef CONFIG_ALTIVEC 1918 case STORE_VMX: 1919 err = do_vec_store(op.reg, do_stvx, op.ea & ~0xfUL, regs); 1920 goto ldst_done; 1921 #endif 1922 #ifdef CONFIG_VSX 1923 case STORE_VSX: 1924 err = do_vsx_store(op.reg, do_stxvd2x, op.ea, regs); 1925 goto ldst_done; 1926 #endif 1927 case STORE_MULTI: 1928 if (regs->msr & MSR_LE) 1929 return 0; 1930 rd = op.reg; 1931 for (i = 0; i < size; i += 4) { 1932 val = regs->gpr[rd]; 1933 nb = size - i; 1934 if (nb > 4) 1935 nb = 4; 1936 else 1937 val >>= 32 - 8 * nb; 1938 err = write_mem(val, op.ea, nb, regs); 1939 if (err) 1940 return 0; 1941 op.ea += 4; 1942 ++rd; 1943 } 1944 goto instr_done; 1945 1946 case MFMSR: 1947 regs->gpr[op.reg] = regs->msr & MSR_MASK; 1948 goto instr_done; 1949 1950 case MTMSR: 1951 val = regs->gpr[op.reg]; 1952 if ((val & MSR_RI) == 0) 1953 /* can't step mtmsr[d] that would clear MSR_RI */ 1954 return -1; 1955 /* here op.val is the mask of bits to change */ 1956 regs->msr = (regs->msr & ~op.val) | (val & op.val); 1957 goto instr_done; 1958 1959 #ifdef CONFIG_PPC64 1960 case SYSCALL: /* sc */ 1961 /* 1962 * N.B. this uses knowledge about how the syscall 1963 * entry code works. If that is changed, this will 1964 * need to be changed also. 1965 */ 1966 if (regs->gpr[0] == 0x1ebe && 1967 cpu_has_feature(CPU_FTR_REAL_LE)) { 1968 regs->msr ^= MSR_LE; 1969 goto instr_done; 1970 } 1971 regs->gpr[9] = regs->gpr[13]; 1972 regs->gpr[10] = MSR_KERNEL; 1973 regs->gpr[11] = regs->nip + 4; 1974 regs->gpr[12] = regs->msr & MSR_MASK; 1975 regs->gpr[13] = (unsigned long) get_paca(); 1976 regs->nip = (unsigned long) &system_call_common; 1977 regs->msr = MSR_KERNEL; 1978 return 1; 1979 1980 case RFI: 1981 return -1; 1982 #endif 1983 } 1984 return 0; 1985 1986 ldst_done: 1987 if (err) 1988 return 0; 1989 if (op.type & UPDATE) 1990 regs->gpr[op.update_reg] = op.ea; 1991 1992 instr_done: 1993 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4); 1994 return 1; 1995 } 1996 NOKPROBE_SYMBOL(emulate_step); 1997