xref: /linux/arch/powerpc/kernel/setup_32.c (revision 6ed7ffddcf61f668114edb676417e5fb33773b59)
1 /*
2  * Common prep/pmac/chrp boot and setup code.
3  */
4 
5 #include <linux/module.h>
6 #include <linux/string.h>
7 #include <linux/sched.h>
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/reboot.h>
11 #include <linux/delay.h>
12 #include <linux/initrd.h>
13 #include <linux/tty.h>
14 #include <linux/bootmem.h>
15 #include <linux/seq_file.h>
16 #include <linux/root_dev.h>
17 #include <linux/cpu.h>
18 #include <linux/console.h>
19 #include <linux/memblock.h>
20 
21 #include <asm/io.h>
22 #include <asm/prom.h>
23 #include <asm/processor.h>
24 #include <asm/pgtable.h>
25 #include <asm/setup.h>
26 #include <asm/smp.h>
27 #include <asm/elf.h>
28 #include <asm/cputable.h>
29 #include <asm/bootx.h>
30 #include <asm/btext.h>
31 #include <asm/machdep.h>
32 #include <asm/uaccess.h>
33 #include <asm/pmac_feature.h>
34 #include <asm/sections.h>
35 #include <asm/nvram.h>
36 #include <asm/xmon.h>
37 #include <asm/time.h>
38 #include <asm/serial.h>
39 #include <asm/udbg.h>
40 #include <asm/mmu_context.h>
41 
42 #include "setup.h"
43 
44 #define DBG(fmt...)
45 
46 extern void bootx_init(unsigned long r4, unsigned long phys);
47 
48 int boot_cpuid = -1;
49 EXPORT_SYMBOL_GPL(boot_cpuid);
50 int boot_cpuid_phys;
51 EXPORT_SYMBOL_GPL(boot_cpuid_phys);
52 
53 int smp_hw_index[NR_CPUS];
54 
55 unsigned long ISA_DMA_THRESHOLD;
56 unsigned int DMA_MODE_READ;
57 unsigned int DMA_MODE_WRITE;
58 
59 #ifdef CONFIG_VGA_CONSOLE
60 unsigned long vgacon_remap_base;
61 EXPORT_SYMBOL(vgacon_remap_base);
62 #endif
63 
64 /*
65  * These are used in binfmt_elf.c to put aux entries on the stack
66  * for each elf executable being started.
67  */
68 int dcache_bsize;
69 int icache_bsize;
70 int ucache_bsize;
71 
72 /*
73  * We're called here very early in the boot.  We determine the machine
74  * type and call the appropriate low-level setup functions.
75  *  -- Cort <cort@fsmlabs.com>
76  *
77  * Note that the kernel may be running at an address which is different
78  * from the address that it was linked at, so we must use RELOC/PTRRELOC
79  * to access static data (including strings).  -- paulus
80  */
81 notrace unsigned long __init early_init(unsigned long dt_ptr)
82 {
83 	unsigned long offset = reloc_offset();
84 	struct cpu_spec *spec;
85 
86 	/* First zero the BSS -- use memset_io, some platforms don't have
87 	 * caches on yet */
88 	memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
89 			__bss_stop - __bss_start);
90 
91 	/*
92 	 * Identify the CPU type and fix up code sections
93 	 * that depend on which cpu we have.
94 	 */
95 	spec = identify_cpu(offset, mfspr(SPRN_PVR));
96 
97 	do_feature_fixups(spec->cpu_features,
98 			  PTRRELOC(&__start___ftr_fixup),
99 			  PTRRELOC(&__stop___ftr_fixup));
100 
101 	do_feature_fixups(spec->mmu_features,
102 			  PTRRELOC(&__start___mmu_ftr_fixup),
103 			  PTRRELOC(&__stop___mmu_ftr_fixup));
104 
105 	do_lwsync_fixups(spec->cpu_features,
106 			 PTRRELOC(&__start___lwsync_fixup),
107 			 PTRRELOC(&__stop___lwsync_fixup));
108 
109 	do_final_fixups();
110 
111 	return KERNELBASE + offset;
112 }
113 
114 
115 /*
116  * Find out what kind of machine we're on and save any data we need
117  * from the early boot process (devtree is copied on pmac by prom_init()).
118  * This is called very early on the boot process, after a minimal
119  * MMU environment has been set up but before MMU_init is called.
120  */
121 notrace void __init machine_init(u64 dt_ptr)
122 {
123 	lockdep_init();
124 
125 	/* Enable early debugging if any specified (see udbg.h) */
126 	udbg_early_init();
127 
128 	/* Do some early initialization based on the flat device tree */
129 	early_init_devtree(__va(dt_ptr));
130 
131 	early_init_mmu();
132 
133 	probe_machine();
134 
135 	setup_kdump_trampoline();
136 
137 #ifdef CONFIG_6xx
138 	if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
139 	    cpu_has_feature(CPU_FTR_CAN_NAP))
140 		ppc_md.power_save = ppc6xx_idle;
141 #endif
142 
143 #ifdef CONFIG_E500
144 	if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
145 	    cpu_has_feature(CPU_FTR_CAN_NAP))
146 		ppc_md.power_save = e500_idle;
147 #endif
148 	if (ppc_md.progress)
149 		ppc_md.progress("id mach(): done", 0x200);
150 }
151 
152 /* Checks "l2cr=xxxx" command-line option */
153 int __init ppc_setup_l2cr(char *str)
154 {
155 	if (cpu_has_feature(CPU_FTR_L2CR)) {
156 		unsigned long val = simple_strtoul(str, NULL, 0);
157 		printk(KERN_INFO "l2cr set to %lx\n", val);
158 		_set_L2CR(0);		/* force invalidate by disable cache */
159 		_set_L2CR(val);		/* and enable it */
160 	}
161 	return 1;
162 }
163 __setup("l2cr=", ppc_setup_l2cr);
164 
165 /* Checks "l3cr=xxxx" command-line option */
166 int __init ppc_setup_l3cr(char *str)
167 {
168 	if (cpu_has_feature(CPU_FTR_L3CR)) {
169 		unsigned long val = simple_strtoul(str, NULL, 0);
170 		printk(KERN_INFO "l3cr set to %lx\n", val);
171 		_set_L3CR(val);		/* and enable it */
172 	}
173 	return 1;
174 }
175 __setup("l3cr=", ppc_setup_l3cr);
176 
177 #ifdef CONFIG_GENERIC_NVRAM
178 
179 /* Generic nvram hooks used by drivers/char/gen_nvram.c */
180 unsigned char nvram_read_byte(int addr)
181 {
182 	if (ppc_md.nvram_read_val)
183 		return ppc_md.nvram_read_val(addr);
184 	return 0xff;
185 }
186 EXPORT_SYMBOL(nvram_read_byte);
187 
188 void nvram_write_byte(unsigned char val, int addr)
189 {
190 	if (ppc_md.nvram_write_val)
191 		ppc_md.nvram_write_val(addr, val);
192 }
193 EXPORT_SYMBOL(nvram_write_byte);
194 
195 ssize_t nvram_get_size(void)
196 {
197 	if (ppc_md.nvram_size)
198 		return ppc_md.nvram_size();
199 	return -1;
200 }
201 EXPORT_SYMBOL(nvram_get_size);
202 
203 void nvram_sync(void)
204 {
205 	if (ppc_md.nvram_sync)
206 		ppc_md.nvram_sync();
207 }
208 EXPORT_SYMBOL(nvram_sync);
209 
210 #endif /* CONFIG_NVRAM */
211 
212 int __init ppc_init(void)
213 {
214 	/* clear the progress line */
215 	if (ppc_md.progress)
216 		ppc_md.progress("             ", 0xffff);
217 
218 	/* call platform init */
219 	if (ppc_md.init != NULL) {
220 		ppc_md.init();
221 	}
222 	return 0;
223 }
224 
225 arch_initcall(ppc_init);
226 
227 static void __init irqstack_early_init(void)
228 {
229 	unsigned int i;
230 
231 	/* interrupt stacks must be in lowmem, we get that for free on ppc32
232 	 * as the memblock is limited to lowmem by default */
233 	for_each_possible_cpu(i) {
234 		softirq_ctx[i] = (struct thread_info *)
235 			__va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
236 		hardirq_ctx[i] = (struct thread_info *)
237 			__va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
238 	}
239 }
240 
241 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
242 static void __init exc_lvl_early_init(void)
243 {
244 	unsigned int i, hw_cpu;
245 
246 	/* interrupt stacks must be in lowmem, we get that for free on ppc32
247 	 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
248 	for_each_possible_cpu(i) {
249 		hw_cpu = get_hard_smp_processor_id(i);
250 		critirq_ctx[hw_cpu] = (struct thread_info *)
251 			__va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
252 #ifdef CONFIG_BOOKE
253 		dbgirq_ctx[hw_cpu] = (struct thread_info *)
254 			__va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
255 		mcheckirq_ctx[hw_cpu] = (struct thread_info *)
256 			__va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
257 #endif
258 	}
259 }
260 #else
261 #define exc_lvl_early_init()
262 #endif
263 
264 /* Warning, IO base is not yet inited */
265 void __init setup_arch(char **cmdline_p)
266 {
267 	*cmdline_p = cmd_line;
268 
269 	/* so udelay does something sensible, assume <= 1000 bogomips */
270 	loops_per_jiffy = 500000000 / HZ;
271 
272 	unflatten_device_tree();
273 	check_for_initrd();
274 
275 	if (ppc_md.init_early)
276 		ppc_md.init_early();
277 
278 	find_legacy_serial_ports();
279 
280 	smp_setup_cpu_maps();
281 
282 	/* Register early console */
283 	register_early_udbg_console();
284 
285 	xmon_setup();
286 
287 	/*
288 	 * Set cache line size based on type of cpu as a default.
289 	 * Systems with OF can look in the properties on the cpu node(s)
290 	 * for a possibly more accurate value.
291 	 */
292 	dcache_bsize = cur_cpu_spec->dcache_bsize;
293 	icache_bsize = cur_cpu_spec->icache_bsize;
294 	ucache_bsize = 0;
295 	if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
296 		ucache_bsize = icache_bsize = dcache_bsize;
297 
298 	/* reboot on panic */
299 	panic_timeout = 180;
300 
301 	if (ppc_md.panic)
302 		setup_panic();
303 
304 	init_mm.start_code = (unsigned long)_stext;
305 	init_mm.end_code = (unsigned long) _etext;
306 	init_mm.end_data = (unsigned long) _edata;
307 	init_mm.brk = klimit;
308 
309 	exc_lvl_early_init();
310 
311 	irqstack_early_init();
312 
313 	/* set up the bootmem stuff with available memory */
314 	do_init_bootmem();
315 	if ( ppc_md.progress ) ppc_md.progress("setup_arch: bootmem", 0x3eab);
316 
317 #ifdef CONFIG_DUMMY_CONSOLE
318 	conswitchp = &dummy_con;
319 #endif
320 
321 	if (ppc_md.setup_arch)
322 		ppc_md.setup_arch();
323 	if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab);
324 
325 	paging_init();
326 
327 	/* Initialize the MMU context management stuff */
328 	mmu_context_init();
329 
330 }
331