1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * 12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 14 * 15 * This file contains the entry point for the 64-bit kernel along 16 * with some early initialization code common to all 64-bit powerpc 17 * variants. 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 22 * 2 of the License, or (at your option) any later version. 23 */ 24 25#include <linux/threads.h> 26#include <asm/reg.h> 27#include <asm/page.h> 28#include <asm/mmu.h> 29#include <asm/ppc_asm.h> 30#include <asm/asm-offsets.h> 31#include <asm/bug.h> 32#include <asm/cputable.h> 33#include <asm/setup.h> 34#include <asm/hvcall.h> 35#include <asm/iseries/lpar_map.h> 36#include <asm/thread_info.h> 37#include <asm/firmware.h> 38#include <asm/page_64.h> 39#include <asm/irqflags.h> 40#include <asm/kvm_book3s_asm.h> 41 42/* The physical memory is layed out such that the secondary processor 43 * spin code sits at 0x0000...0x00ff. On server, the vectors follow 44 * using the layout described in exceptions-64s.S 45 */ 46 47/* 48 * Entering into this code we make the following assumptions: 49 * 50 * For pSeries or server processors: 51 * 1. The MMU is off & open firmware is running in real mode. 52 * 2. The kernel is entered at __start 53 * 54 * For iSeries: 55 * 1. The MMU is on (as it always is for iSeries) 56 * 2. The kernel is entered at system_reset_iSeries 57 * 58 * For Book3E processors: 59 * 1. The MMU is on running in AS0 in a state defined in ePAPR 60 * 2. The kernel is entered at __start 61 */ 62 63 .text 64 .globl _stext 65_stext: 66_GLOBAL(__start) 67 /* NOP this out unconditionally */ 68BEGIN_FTR_SECTION 69 b .__start_initialization_multiplatform 70END_FTR_SECTION(0, 1) 71 72 /* Catch branch to 0 in real mode */ 73 trap 74 75 /* Secondary processors spin on this value until it becomes nonzero. 76 * When it does it contains the real address of the descriptor 77 * of the function that the cpu should jump to to continue 78 * initialization. 79 */ 80 .globl __secondary_hold_spinloop 81__secondary_hold_spinloop: 82 .llong 0x0 83 84 /* Secondary processors write this value with their cpu # */ 85 /* after they enter the spin loop immediately below. */ 86 .globl __secondary_hold_acknowledge 87__secondary_hold_acknowledge: 88 .llong 0x0 89 90#ifdef CONFIG_PPC_ISERIES 91 /* 92 * At offset 0x20, there is a pointer to iSeries LPAR data. 93 * This is required by the hypervisor 94 */ 95 . = 0x20 96 .llong hvReleaseData-KERNELBASE 97#endif /* CONFIG_PPC_ISERIES */ 98 99#ifdef CONFIG_CRASH_DUMP 100 /* This flag is set to 1 by a loader if the kernel should run 101 * at the loaded address instead of the linked address. This 102 * is used by kexec-tools to keep the the kdump kernel in the 103 * crash_kernel region. The loader is responsible for 104 * observing the alignment requirement. 105 */ 106 /* Do not move this variable as kexec-tools knows about it. */ 107 . = 0x5c 108 .globl __run_at_load 109__run_at_load: 110 .long 0x72756e30 /* "run0" -- relocate to 0 by default */ 111#endif 112 113 . = 0x60 114/* 115 * The following code is used to hold secondary processors 116 * in a spin loop after they have entered the kernel, but 117 * before the bulk of the kernel has been relocated. This code 118 * is relocated to physical address 0x60 before prom_init is run. 119 * All of it must fit below the first exception vector at 0x100. 120 * Use .globl here not _GLOBAL because we want __secondary_hold 121 * to be the actual text address, not a descriptor. 122 */ 123 .globl __secondary_hold 124__secondary_hold: 125#ifndef CONFIG_PPC_BOOK3E 126 mfmsr r24 127 ori r24,r24,MSR_RI 128 mtmsrd r24 /* RI on */ 129#endif 130 /* Grab our physical cpu number */ 131 mr r24,r3 132 133 /* Tell the master cpu we're here */ 134 /* Relocation is off & we are located at an address less */ 135 /* than 0x100, so only need to grab low order offset. */ 136 std r24,__secondary_hold_acknowledge-_stext(0) 137 sync 138 139 /* All secondary cpus wait here until told to start. */ 140100: ld r4,__secondary_hold_spinloop-_stext(0) 141 cmpdi 0,r4,0 142 beq 100b 143 144#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 145 ld r4,0(r4) /* deref function descriptor */ 146 mtctr r4 147 mr r3,r24 148 li r4,0 149 bctr 150#else 151 BUG_OPCODE 152#endif 153 154/* This value is used to mark exception frames on the stack. */ 155 .section ".toc","aw" 156exception_marker: 157 .tc ID_72656773_68657265[TC],0x7265677368657265 158 .text 159 160/* 161 * On server, we include the exception vectors code here as it 162 * relies on absolute addressing which is only possible within 163 * this compilation unit 164 */ 165#ifdef CONFIG_PPC_BOOK3S 166#include "exceptions-64s.S" 167#endif 168 169/* KVM trampoline code needs to be close to the interrupt handlers */ 170 171#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 172#include "../kvm/book3s_rmhandlers.S" 173#endif 174 175_GLOBAL(generic_secondary_thread_init) 176 mr r24,r3 177 178 /* turn on 64-bit mode */ 179 bl .enable_64b_mode 180 181 /* get a valid TOC pointer, wherever we're mapped at */ 182 bl .relative_toc 183 184#ifdef CONFIG_PPC_BOOK3E 185 /* Book3E initialization */ 186 mr r3,r24 187 bl .book3e_secondary_thread_init 188#endif 189 b generic_secondary_common_init 190 191/* 192 * On pSeries and most other platforms, secondary processors spin 193 * in the following code. 194 * At entry, r3 = this processor's number (physical cpu id) 195 * 196 * On Book3E, r4 = 1 to indicate that the initial TLB entry for 197 * this core already exists (setup via some other mechanism such 198 * as SCOM before entry). 199 */ 200_GLOBAL(generic_secondary_smp_init) 201 mr r24,r3 202 mr r25,r4 203 204 /* turn on 64-bit mode */ 205 bl .enable_64b_mode 206 207 /* get a valid TOC pointer, wherever we're mapped at */ 208 bl .relative_toc 209 210#ifdef CONFIG_PPC_BOOK3E 211 /* Book3E initialization */ 212 mr r3,r24 213 mr r4,r25 214 bl .book3e_secondary_core_init 215#endif 216 217generic_secondary_common_init: 218 /* Set up a paca value for this processor. Since we have the 219 * physical cpu id in r24, we need to search the pacas to find 220 * which logical id maps to our physical one. 221 */ 222 LOAD_REG_ADDR(r13, paca) /* Load paca pointer */ 223 ld r13,0(r13) /* Get base vaddr of paca array */ 224 li r5,0 /* logical cpu id */ 2251: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 226 cmpw r6,r24 /* Compare to our id */ 227 beq 2f 228 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ 229 addi r5,r5,1 230 cmpwi r5,NR_CPUS 231 blt 1b 232 233 mr r3,r24 /* not found, copy phys to r3 */ 234 b .kexec_wait /* next kernel might do better */ 235 2362: mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG */ 237#ifdef CONFIG_PPC_BOOK3E 238 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ 239 mtspr SPRN_SPRG_TLB_EXFRAME,r12 240#endif 241 242 /* From now on, r24 is expected to be logical cpuid */ 243 mr r24,r5 2443: HMT_LOW 245 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 246 /* start. */ 247 248#ifndef CONFIG_SMP 249 b 3b /* Never go on non-SMP */ 250#else 251 cmpwi 0,r23,0 252 beq 3b /* Loop until told to go */ 253 254 sync /* order paca.run and cur_cpu_spec */ 255 256 /* See if we need to call a cpu state restore handler */ 257 LOAD_REG_ADDR(r23, cur_cpu_spec) 258 ld r23,0(r23) 259 ld r23,CPU_SPEC_RESTORE(r23) 260 cmpdi 0,r23,0 261 beq 4f 262 ld r23,0(r23) 263 mtctr r23 264 bctrl 265 2664: /* Create a temp kernel stack for use before relocation is on. */ 267 ld r1,PACAEMERGSP(r13) 268 subi r1,r1,STACK_FRAME_OVERHEAD 269 270 b __secondary_start 271#endif 272 273/* 274 * Turn the MMU off. 275 * Assumes we're mapped EA == RA if the MMU is on. 276 */ 277#ifdef CONFIG_PPC_BOOK3S 278_STATIC(__mmu_off) 279 mfmsr r3 280 andi. r0,r3,MSR_IR|MSR_DR 281 beqlr 282 mflr r4 283 andc r3,r3,r0 284 mtspr SPRN_SRR0,r4 285 mtspr SPRN_SRR1,r3 286 sync 287 rfid 288 b . /* prevent speculative execution */ 289#endif 290 291 292/* 293 * Here is our main kernel entry point. We support currently 2 kind of entries 294 * depending on the value of r5. 295 * 296 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 297 * in r3...r7 298 * 299 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 300 * DT block, r4 is a physical pointer to the kernel itself 301 * 302 */ 303_GLOBAL(__start_initialization_multiplatform) 304 /* Make sure we are running in 64 bits mode */ 305 bl .enable_64b_mode 306 307 /* Get TOC pointer (current runtime address) */ 308 bl .relative_toc 309 310 /* find out where we are now */ 311 bcl 20,31,$+4 3120: mflr r26 /* r26 = runtime addr here */ 313 addis r26,r26,(_stext - 0b)@ha 314 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ 315 316 /* 317 * Are we booted from a PROM Of-type client-interface ? 318 */ 319 cmpldi cr0,r5,0 320 beq 1f 321 b .__boot_from_prom /* yes -> prom */ 3221: 323 /* Save parameters */ 324 mr r31,r3 325 mr r30,r4 326 327#ifdef CONFIG_PPC_BOOK3E 328 bl .start_initialization_book3e 329 b .__after_prom_start 330#else 331 /* Setup some critical 970 SPRs before switching MMU off */ 332 mfspr r0,SPRN_PVR 333 srwi r0,r0,16 334 cmpwi r0,0x39 /* 970 */ 335 beq 1f 336 cmpwi r0,0x3c /* 970FX */ 337 beq 1f 338 cmpwi r0,0x44 /* 970MP */ 339 beq 1f 340 cmpwi r0,0x45 /* 970GX */ 341 bne 2f 3421: bl .__cpu_preinit_ppc970 3432: 344 345 /* Switch off MMU if not already off */ 346 bl .__mmu_off 347 b .__after_prom_start 348#endif /* CONFIG_PPC_BOOK3E */ 349 350_INIT_STATIC(__boot_from_prom) 351#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE 352 /* Save parameters */ 353 mr r31,r3 354 mr r30,r4 355 mr r29,r5 356 mr r28,r6 357 mr r27,r7 358 359 /* 360 * Align the stack to 16-byte boundary 361 * Depending on the size and layout of the ELF sections in the initial 362 * boot binary, the stack pointer may be unaligned on PowerMac 363 */ 364 rldicr r1,r1,0,59 365 366#ifdef CONFIG_RELOCATABLE 367 /* Relocate code for where we are now */ 368 mr r3,r26 369 bl .relocate 370#endif 371 372 /* Restore parameters */ 373 mr r3,r31 374 mr r4,r30 375 mr r5,r29 376 mr r6,r28 377 mr r7,r27 378 379 /* Do all of the interaction with OF client interface */ 380 mr r8,r26 381 bl .prom_init 382#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ 383 384 /* We never return. We also hit that trap if trying to boot 385 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ 386 trap 387 388_STATIC(__after_prom_start) 389#ifdef CONFIG_RELOCATABLE 390 /* process relocations for the final address of the kernel */ 391 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ 392 sldi r25,r25,32 393#ifdef CONFIG_CRASH_DUMP 394 lwz r7,__run_at_load-_stext(r26) 395 cmplwi cr0,r7,1 /* kdump kernel ? - stay where we are */ 396 bne 1f 397 add r25,r25,r26 398#endif 3991: mr r3,r25 400 bl .relocate 401#endif 402 403/* 404 * We need to run with _stext at physical address PHYSICAL_START. 405 * This will leave some code in the first 256B of 406 * real memory, which are reserved for software use. 407 * 408 * Note: This process overwrites the OF exception vectors. 409 */ 410 li r3,0 /* target addr */ 411#ifdef CONFIG_PPC_BOOK3E 412 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ 413#endif 414 mr. r4,r26 /* In some cases the loader may */ 415 beq 9f /* have already put us at zero */ 416 li r6,0x100 /* Start offset, the first 0x100 */ 417 /* bytes were copied earlier. */ 418#ifdef CONFIG_PPC_BOOK3E 419 tovirt(r6,r6) /* on booke, we already run at PAGE_OFFSET */ 420#endif 421 422#ifdef CONFIG_CRASH_DUMP 423/* 424 * Check if the kernel has to be running as relocatable kernel based on the 425 * variable __run_at_load, if it is set the kernel is treated as relocatable 426 * kernel, otherwise it will be moved to PHYSICAL_START 427 */ 428 lwz r7,__run_at_load-_stext(r26) 429 cmplwi cr0,r7,1 430 bne 3f 431 432 li r5,__end_interrupts - _stext /* just copy interrupts */ 433 b 5f 4343: 435#endif 436 lis r5,(copy_to_here - _stext)@ha 437 addi r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */ 438 439 bl .copy_and_flush /* copy the first n bytes */ 440 /* this includes the code being */ 441 /* executed here. */ 442 addis r8,r3,(4f - _stext)@ha /* Jump to the copy of this code */ 443 addi r8,r8,(4f - _stext)@l /* that we just made */ 444 mtctr r8 445 bctr 446 447p_end: .llong _end - _stext 448 4494: /* Now copy the rest of the kernel up to _end */ 450 addis r5,r26,(p_end - _stext)@ha 451 ld r5,(p_end - _stext)@l(r5) /* get _end */ 4525: bl .copy_and_flush /* copy the rest */ 453 4549: b .start_here_multiplatform 455 456/* 457 * Copy routine used to copy the kernel to start at physical address 0 458 * and flush and invalidate the caches as needed. 459 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 460 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 461 * 462 * Note: this routine *only* clobbers r0, r6 and lr 463 */ 464_GLOBAL(copy_and_flush) 465 addi r5,r5,-8 466 addi r6,r6,-8 4674: li r0,8 /* Use the smallest common */ 468 /* denominator cache line */ 469 /* size. This results in */ 470 /* extra cache line flushes */ 471 /* but operation is correct. */ 472 /* Can't get cache line size */ 473 /* from NACA as it is being */ 474 /* moved too. */ 475 476 mtctr r0 /* put # words/line in ctr */ 4773: addi r6,r6,8 /* copy a cache line */ 478 ldx r0,r6,r4 479 stdx r0,r6,r3 480 bdnz 3b 481 dcbst r6,r3 /* write it to memory */ 482 sync 483 icbi r6,r3 /* flush the icache line */ 484 cmpld 0,r6,r5 485 blt 4b 486 sync 487 addi r5,r5,8 488 addi r6,r6,8 489 blr 490 491.align 8 492copy_to_here: 493 494#ifdef CONFIG_SMP 495#ifdef CONFIG_PPC_PMAC 496/* 497 * On PowerMac, secondary processors starts from the reset vector, which 498 * is temporarily turned into a call to one of the functions below. 499 */ 500 .section ".text"; 501 .align 2 ; 502 503 .globl __secondary_start_pmac_0 504__secondary_start_pmac_0: 505 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 506 li r24,0 507 b 1f 508 li r24,1 509 b 1f 510 li r24,2 511 b 1f 512 li r24,3 5131: 514 515_GLOBAL(pmac_secondary_start) 516 /* turn on 64-bit mode */ 517 bl .enable_64b_mode 518 519 li r0,0 520 mfspr r3,SPRN_HID4 521 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 522 sync 523 mtspr SPRN_HID4,r3 524 isync 525 sync 526 slbia 527 528 /* get TOC pointer (real address) */ 529 bl .relative_toc 530 531 /* Copy some CPU settings from CPU 0 */ 532 bl .__restore_cpu_ppc970 533 534 /* pSeries do that early though I don't think we really need it */ 535 mfmsr r3 536 ori r3,r3,MSR_RI 537 mtmsrd r3 /* RI on */ 538 539 /* Set up a paca value for this processor. */ 540 LOAD_REG_ADDR(r4,paca) /* Load paca pointer */ 541 ld r4,0(r4) /* Get base vaddr of paca array */ 542 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ 543 add r13,r13,r4 /* for this processor. */ 544 mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG*/ 545 546 /* Create a temp kernel stack for use before relocation is on. */ 547 ld r1,PACAEMERGSP(r13) 548 subi r1,r1,STACK_FRAME_OVERHEAD 549 550 b __secondary_start 551 552#endif /* CONFIG_PPC_PMAC */ 553 554/* 555 * This function is called after the master CPU has released the 556 * secondary processors. The execution environment is relocation off. 557 * The paca for this processor has the following fields initialized at 558 * this point: 559 * 1. Processor number 560 * 2. Segment table pointer (virtual address) 561 * On entry the following are set: 562 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries 563 * r24 = cpu# (in Linux terms) 564 * r13 = paca virtual address 565 * SPRG_PACA = paca virtual address 566 */ 567 .section ".text"; 568 .align 2 ; 569 570 .globl __secondary_start 571__secondary_start: 572 /* Set thread priority to MEDIUM */ 573 HMT_MEDIUM 574 575 /* Initialize the kernel stack. Just a repeat for iSeries. */ 576 LOAD_REG_ADDR(r3, current_set) 577 sldi r28,r24,3 /* get current_set[cpu#] */ 578 ldx r14,r3,r28 579 addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD 580 std r14,PACAKSAVE(r13) 581 582 /* Do early setup for that CPU (stab, slb, hash table pointer) */ 583 bl .early_setup_secondary 584 585 /* 586 * setup the new stack pointer, but *don't* use this until 587 * translation is on. 588 */ 589 mr r1, r14 590 591 /* Clear backchain so we get nice backtraces */ 592 li r7,0 593 mtlr r7 594 595 /* enable MMU and jump to start_secondary */ 596 LOAD_REG_ADDR(r3, .start_secondary_prolog) 597 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 598#ifdef CONFIG_PPC_ISERIES 599BEGIN_FW_FTR_SECTION 600 ori r4,r4,MSR_EE 601 li r8,1 602 stb r8,PACAHARDIRQEN(r13) 603END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 604#endif 605BEGIN_FW_FTR_SECTION 606 stb r7,PACAHARDIRQEN(r13) 607END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) 608 stb r7,PACASOFTIRQEN(r13) 609 610 mtspr SPRN_SRR0,r3 611 mtspr SPRN_SRR1,r4 612 RFI 613 b . /* prevent speculative execution */ 614 615/* 616 * Running with relocation on at this point. All we want to do is 617 * zero the stack back-chain pointer and get the TOC virtual address 618 * before going into C code. 619 */ 620_GLOBAL(start_secondary_prolog) 621 ld r2,PACATOC(r13) 622 li r3,0 623 std r3,0(r1) /* Zero the stack frame pointer */ 624 bl .start_secondary 625 b . 626/* 627 * Reset stack pointer and call start_secondary 628 * to continue with online operation when woken up 629 * from cede in cpu offline. 630 */ 631_GLOBAL(start_secondary_resume) 632 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ 633 li r3,0 634 std r3,0(r1) /* Zero the stack frame pointer */ 635 bl .start_secondary 636 b . 637#endif 638 639/* 640 * This subroutine clobbers r11 and r12 641 */ 642_GLOBAL(enable_64b_mode) 643 mfmsr r11 /* grab the current MSR */ 644#ifdef CONFIG_PPC_BOOK3E 645 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ 646 mtmsr r11 647#else /* CONFIG_PPC_BOOK3E */ 648 li r12,(MSR_SF | MSR_ISF)@highest 649 sldi r12,r12,48 650 or r11,r11,r12 651 mtmsrd r11 652 isync 653#endif 654 blr 655 656/* 657 * This puts the TOC pointer into r2, offset by 0x8000 (as expected 658 * by the toolchain). It computes the correct value for wherever we 659 * are running at the moment, using position-independent code. 660 */ 661_GLOBAL(relative_toc) 662 mflr r0 663 bcl 20,31,$+4 6640: mflr r9 665 ld r2,(p_toc - 0b)(r9) 666 add r2,r2,r9 667 mtlr r0 668 blr 669 670p_toc: .llong __toc_start + 0x8000 - 0b 671 672/* 673 * This is where the main kernel code starts. 674 */ 675_INIT_STATIC(start_here_multiplatform) 676 /* set up the TOC (real address) */ 677 bl .relative_toc 678 679 /* Clear out the BSS. It may have been done in prom_init, 680 * already but that's irrelevant since prom_init will soon 681 * be detached from the kernel completely. Besides, we need 682 * to clear it now for kexec-style entry. 683 */ 684 LOAD_REG_ADDR(r11,__bss_stop) 685 LOAD_REG_ADDR(r8,__bss_start) 686 sub r11,r11,r8 /* bss size */ 687 addi r11,r11,7 /* round up to an even double word */ 688 srdi. r11,r11,3 /* shift right by 3 */ 689 beq 4f 690 addi r8,r8,-8 691 li r0,0 692 mtctr r11 /* zero this many doublewords */ 6933: stdu r0,8(r8) 694 bdnz 3b 6954: 696 697#ifndef CONFIG_PPC_BOOK3E 698 mfmsr r6 699 ori r6,r6,MSR_RI 700 mtmsrd r6 /* RI on */ 701#endif 702 703#ifdef CONFIG_RELOCATABLE 704 /* Save the physical address we're running at in kernstart_addr */ 705 LOAD_REG_ADDR(r4, kernstart_addr) 706 clrldi r0,r25,2 707 std r0,0(r4) 708#endif 709 710 /* The following gets the stack set up with the regs */ 711 /* pointing to the real addr of the kernel stack. This is */ 712 /* all done to support the C function call below which sets */ 713 /* up the htab. This is done because we have relocated the */ 714 /* kernel but are still running in real mode. */ 715 716 LOAD_REG_ADDR(r3,init_thread_union) 717 718 /* set up a stack pointer */ 719 addi r1,r3,THREAD_SIZE 720 li r0,0 721 stdu r0,-STACK_FRAME_OVERHEAD(r1) 722 723 /* Do very early kernel initializations, including initial hash table, 724 * stab and slb setup before we turn on relocation. */ 725 726 /* Restore parameters passed from prom_init/kexec */ 727 mr r3,r31 728 bl .early_setup /* also sets r13 and SPRG_PACA */ 729 730 LOAD_REG_ADDR(r3, .start_here_common) 731 ld r4,PACAKMSR(r13) 732 mtspr SPRN_SRR0,r3 733 mtspr SPRN_SRR1,r4 734 RFI 735 b . /* prevent speculative execution */ 736 737 /* This is where all platforms converge execution */ 738_INIT_GLOBAL(start_here_common) 739 /* relocation is on at this point */ 740 std r1,PACAKSAVE(r13) 741 742 /* Load the TOC (virtual address) */ 743 ld r2,PACATOC(r13) 744 745 bl .setup_system 746 747 /* Load up the kernel context */ 7485: 749 li r5,0 750 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */ 751#ifdef CONFIG_PPC_ISERIES 752BEGIN_FW_FTR_SECTION 753 mfmsr r5 754 ori r5,r5,MSR_EE /* Hard Enabled on iSeries*/ 755 mtmsrd r5 756 li r5,1 757END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 758#endif 759 stb r5,PACAHARDIRQEN(r13) /* Hard Disabled on others */ 760 761 bl .start_kernel 762 763 /* Not reached */ 764 BUG_OPCODE 765 766/* 767 * We put a few things here that have to be page-aligned. 768 * This stuff goes at the beginning of the bss, which is page-aligned. 769 */ 770 .section ".bss" 771 772 .align PAGE_SHIFT 773 774 .globl empty_zero_page 775empty_zero_page: 776 .space PAGE_SIZE 777 778 .globl swapper_pg_dir 779swapper_pg_dir: 780 .space PGD_TABLE_SIZE 781