1/* 2 * Boot code and exception vectors for Book3E processors 3 * 4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12#include <linux/threads.h> 13#include <asm/reg.h> 14#include <asm/page.h> 15#include <asm/ppc_asm.h> 16#include <asm/asm-offsets.h> 17#include <asm/cputable.h> 18#include <asm/setup.h> 19#include <asm/thread_info.h> 20#include <asm/reg_a2.h> 21#include <asm/exception-64e.h> 22#include <asm/bug.h> 23#include <asm/irqflags.h> 24#include <asm/ptrace.h> 25#include <asm/ppc-opcode.h> 26#include <asm/mmu.h> 27#include <asm/hw_irq.h> 28#include <asm/kvm_asm.h> 29#include <asm/kvm_booke_hv_asm.h> 30 31/* XXX This will ultimately add space for a special exception save 32 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc... 33 * when taking special interrupts. For now we don't support that, 34 * special interrupts from within a non-standard level will probably 35 * blow you up 36 */ 37#define SPECIAL_EXC_FRAME_SIZE INT_FRAME_SIZE 38 39/* Exception prolog code for all exceptions */ 40#define EXCEPTION_PROLOG(n, intnum, type, addition) \ 41 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \ 42 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \ 43 std r10,PACA_EX##type+EX_R10(r13); \ 44 std r11,PACA_EX##type+EX_R11(r13); \ 45 PROLOG_STORE_RESTORE_SCRATCH_##type; \ 46 mfcr r10; /* save CR */ \ 47 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \ 48 DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \ 49 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \ 50 addition; /* additional code for that exc. */ \ 51 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \ 52 type##_SET_KSTACK; /* get special stack if necessary */\ 53 andi. r10,r11,MSR_PR; /* save stack pointer */ \ 54 beq 1f; /* branch around if supervisor */ \ 55 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\ 561: cmpdi cr1,r1,0; /* check if SP makes sense */ \ 57 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \ 58 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */ 59 60/* Exception type-specific macros */ 61#define GEN_SET_KSTACK \ 62 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ 63#define SPRN_GEN_SRR0 SPRN_SRR0 64#define SPRN_GEN_SRR1 SPRN_SRR1 65 66#define GDBELL_SET_KSTACK GEN_SET_KSTACK 67#define SPRN_GDBELL_SRR0 SPRN_GSRR0 68#define SPRN_GDBELL_SRR1 SPRN_GSRR1 69 70#define CRIT_SET_KSTACK \ 71 ld r1,PACA_CRIT_STACK(r13); \ 72 subi r1,r1,SPECIAL_EXC_FRAME_SIZE; 73#define SPRN_CRIT_SRR0 SPRN_CSRR0 74#define SPRN_CRIT_SRR1 SPRN_CSRR1 75 76#define DBG_SET_KSTACK \ 77 ld r1,PACA_DBG_STACK(r13); \ 78 subi r1,r1,SPECIAL_EXC_FRAME_SIZE; 79#define SPRN_DBG_SRR0 SPRN_DSRR0 80#define SPRN_DBG_SRR1 SPRN_DSRR1 81 82#define MC_SET_KSTACK \ 83 ld r1,PACA_MC_STACK(r13); \ 84 subi r1,r1,SPECIAL_EXC_FRAME_SIZE; 85#define SPRN_MC_SRR0 SPRN_MCSRR0 86#define SPRN_MC_SRR1 SPRN_MCSRR1 87 88#define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \ 89 EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n)) 90 91#define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \ 92 EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n)) 93 94#define DBG_EXCEPTION_PROLOG(n, intnum, addition) \ 95 EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n)) 96 97#define MC_EXCEPTION_PROLOG(n, intnum, addition) \ 98 EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n)) 99 100#define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \ 101 EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n)) 102 103/* 104 * Store user-visible scratch in PACA exception slots and restore proper value 105 */ 106#define PROLOG_STORE_RESTORE_SCRATCH_GEN 107#define PROLOG_STORE_RESTORE_SCRATCH_GDBELL 108#define PROLOG_STORE_RESTORE_SCRATCH_DBG 109#define PROLOG_STORE_RESTORE_SCRATCH_MC 110 111#define PROLOG_STORE_RESTORE_SCRATCH_CRIT \ 112 mfspr r10,SPRN_SPRG_CRIT_SCRATCH; /* get r13 */ \ 113 std r10,PACA_EXCRIT+EX_R13(r13); \ 114 ld r11,PACA_SPRG3(r13); \ 115 mtspr SPRN_SPRG_CRIT_SCRATCH,r11; 116 117/* Variants of the "addition" argument for the prolog 118 */ 119#define PROLOG_ADDITION_NONE_GEN(n) 120#define PROLOG_ADDITION_NONE_GDBELL(n) 121#define PROLOG_ADDITION_NONE_CRIT(n) 122#define PROLOG_ADDITION_NONE_DBG(n) 123#define PROLOG_ADDITION_NONE_MC(n) 124 125#define PROLOG_ADDITION_MASKABLE_GEN(n) \ 126 lbz r10,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \ 127 cmpwi cr0,r10,0; /* yes -> go out of line */ \ 128 beq masked_interrupt_book3e_##n 129 130#define PROLOG_ADDITION_2REGS_GEN(n) \ 131 std r14,PACA_EXGEN+EX_R14(r13); \ 132 std r15,PACA_EXGEN+EX_R15(r13) 133 134#define PROLOG_ADDITION_1REG_GEN(n) \ 135 std r14,PACA_EXGEN+EX_R14(r13); 136 137#define PROLOG_ADDITION_2REGS_CRIT(n) \ 138 std r14,PACA_EXCRIT+EX_R14(r13); \ 139 std r15,PACA_EXCRIT+EX_R15(r13) 140 141#define PROLOG_ADDITION_2REGS_DBG(n) \ 142 std r14,PACA_EXDBG+EX_R14(r13); \ 143 std r15,PACA_EXDBG+EX_R15(r13) 144 145#define PROLOG_ADDITION_2REGS_MC(n) \ 146 std r14,PACA_EXMC+EX_R14(r13); \ 147 std r15,PACA_EXMC+EX_R15(r13) 148 149 150/* Core exception code for all exceptions except TLB misses. 151 * XXX: Needs to make SPRN_SPRG_GEN depend on exception type 152 */ 153#define EXCEPTION_COMMON(n, excf, ints) \ 154exc_##n##_common: \ 155 std r0,GPR0(r1); /* save r0 in stackframe */ \ 156 std r2,GPR2(r1); /* save r2 in stackframe */ \ 157 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 158 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 159 std r9,GPR9(r1); /* save r9 in stackframe */ \ 160 std r10,_NIP(r1); /* save SRR0 to stackframe */ \ 161 std r11,_MSR(r1); /* save SRR1 to stackframe */ \ 162 beq 2f; /* if from kernel mode */ \ 163 ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \ 1642: ld r3,excf+EX_R10(r13); /* get back r10 */ \ 165 ld r4,excf+EX_R11(r13); /* get back r11 */ \ 166 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */ \ 167 std r12,GPR12(r1); /* save r12 in stackframe */ \ 168 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 169 mflr r6; /* save LR in stackframe */ \ 170 mfctr r7; /* save CTR in stackframe */ \ 171 mfspr r8,SPRN_XER; /* save XER in stackframe */ \ 172 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \ 173 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \ 174 lbz r11,PACASOFTIRQEN(r13); /* get current IRQ softe */ \ 175 ld r12,exception_marker@toc(r2); \ 176 li r0,0; \ 177 std r3,GPR10(r1); /* save r10 to stackframe */ \ 178 std r4,GPR11(r1); /* save r11 to stackframe */ \ 179 std r5,GPR13(r1); /* save it to stackframe */ \ 180 std r6,_LINK(r1); \ 181 std r7,_CTR(r1); \ 182 std r8,_XER(r1); \ 183 li r3,(n)+1; /* indicate partial regs in trap */ \ 184 std r9,0(r1); /* store stack frame back link */ \ 185 std r10,_CCR(r1); /* store orig CR in stackframe */ \ 186 std r9,GPR1(r1); /* store stack frame back link */ \ 187 std r11,SOFTE(r1); /* and save it to stackframe */ \ 188 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \ 189 std r3,_TRAP(r1); /* set trap number */ \ 190 std r0,RESULT(r1); /* clear regs->result */ \ 191 ints; 192 193/* Variants for the "ints" argument. This one does nothing when we want 194 * to keep interrupts in their original state 195 */ 196#define INTS_KEEP 197 198/* This second version is meant for exceptions that don't immediately 199 * hard-enable. We set a bit in paca->irq_happened to ensure that 200 * a subsequent call to arch_local_irq_restore() will properly 201 * hard-enable and avoid the fast-path 202 */ 203#define INTS_DISABLE SOFT_DISABLE_INTS(r3,r4) 204 205/* This is called by exceptions that used INTS_KEEP (that did not touch 206 * irq indicators in the PACA). This will restore MSR:EE to it's previous 207 * value 208 * 209 * XXX In the long run, we may want to open-code it in order to separate the 210 * load from the wrtee, thus limiting the latency caused by the dependency 211 * but at this point, I'll favor code clarity until we have a near to final 212 * implementation 213 */ 214#define INTS_RESTORE_HARD \ 215 ld r11,_MSR(r1); \ 216 wrtee r11; 217 218/* XXX FIXME: Restore r14/r15 when necessary */ 219#define BAD_STACK_TRAMPOLINE(n) \ 220exc_##n##_bad_stack: \ 221 li r1,(n); /* get exception number */ \ 222 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \ 223 b bad_stack_book3e; /* bad stack error */ 224 225/* WARNING: If you change the layout of this stub, make sure you chcek 226 * the debug exception handler which handles single stepping 227 * into exceptions from userspace, and the MM code in 228 * arch/powerpc/mm/tlb_nohash.c which patches the branch here 229 * and would need to be updated if that branch is moved 230 */ 231#define EXCEPTION_STUB(loc, label) \ 232 . = interrupt_base_book3e + loc; \ 233 nop; /* To make debug interrupts happy */ \ 234 b exc_##label##_book3e; 235 236#define ACK_NONE(r) 237#define ACK_DEC(r) \ 238 lis r,TSR_DIS@h; \ 239 mtspr SPRN_TSR,r 240#define ACK_FIT(r) \ 241 lis r,TSR_FIS@h; \ 242 mtspr SPRN_TSR,r 243 244/* Used by asynchronous interrupt that may happen in the idle loop. 245 * 246 * This check if the thread was in the idle loop, and if yes, returns 247 * to the caller rather than the PC. This is to avoid a race if 248 * interrupts happen before the wait instruction. 249 */ 250#define CHECK_NAPPING() \ 251 CURRENT_THREAD_INFO(r11, r1); \ 252 ld r10,TI_LOCAL_FLAGS(r11); \ 253 andi. r9,r10,_TLF_NAPPING; \ 254 beq+ 1f; \ 255 ld r8,_LINK(r1); \ 256 rlwinm r7,r10,0,~_TLF_NAPPING; \ 257 std r8,_NIP(r1); \ 258 std r7,TI_LOCAL_FLAGS(r11); \ 2591: 260 261 262#define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \ 263 START_EXCEPTION(label); \ 264 NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\ 265 EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE) \ 266 ack(r8); \ 267 CHECK_NAPPING(); \ 268 addi r3,r1,STACK_FRAME_OVERHEAD; \ 269 bl hdlr; \ 270 b .ret_from_except_lite; 271 272/* This value is used to mark exception frames on the stack. */ 273 .section ".toc","aw" 274exception_marker: 275 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER 276 277 278/* 279 * And here we have the exception vectors ! 280 */ 281 282 .text 283 .balign 0x1000 284 .globl interrupt_base_book3e 285interrupt_base_book3e: /* fake trap */ 286 EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */ 287 EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */ 288 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */ 289 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */ 290 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */ 291 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */ 292 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */ 293 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */ 294 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */ 295 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */ 296 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */ 297 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */ 298 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */ 299 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */ 300 EXCEPTION_STUB(0x1c0, data_tlb_miss) 301 EXCEPTION_STUB(0x1e0, instruction_tlb_miss) 302 EXCEPTION_STUB(0x260, perfmon) 303 EXCEPTION_STUB(0x280, doorbell) 304 EXCEPTION_STUB(0x2a0, doorbell_crit) 305 EXCEPTION_STUB(0x2c0, guest_doorbell) 306 EXCEPTION_STUB(0x2e0, guest_doorbell_crit) 307 EXCEPTION_STUB(0x300, hypercall) 308 EXCEPTION_STUB(0x320, ehpriv) 309 310 .globl interrupt_end_book3e 311interrupt_end_book3e: 312 313/* Critical Input Interrupt */ 314 START_EXCEPTION(critical_input); 315 CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL, 316 PROLOG_ADDITION_NONE) 317// EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE) 318// bl special_reg_save_crit 319// CHECK_NAPPING(); 320// addi r3,r1,STACK_FRAME_OVERHEAD 321// bl .critical_exception 322// b ret_from_crit_except 323 b . 324 325/* Machine Check Interrupt */ 326 START_EXCEPTION(machine_check); 327 MC_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_MACHINE_CHECK, 328 PROLOG_ADDITION_NONE) 329// EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE) 330// bl special_reg_save_mc 331// addi r3,r1,STACK_FRAME_OVERHEAD 332// CHECK_NAPPING(); 333// bl .machine_check_exception 334// b ret_from_mc_except 335 b . 336 337/* Data Storage Interrupt */ 338 START_EXCEPTION(data_storage) 339 NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE, 340 PROLOG_ADDITION_2REGS) 341 mfspr r14,SPRN_DEAR 342 mfspr r15,SPRN_ESR 343 EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_DISABLE) 344 b storage_fault_common 345 346/* Instruction Storage Interrupt */ 347 START_EXCEPTION(instruction_storage); 348 NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE, 349 PROLOG_ADDITION_2REGS) 350 li r15,0 351 mr r14,r10 352 EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_DISABLE) 353 b storage_fault_common 354 355/* External Input Interrupt */ 356 MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL, 357 external_input, .do_IRQ, ACK_NONE) 358 359/* Alignment */ 360 START_EXCEPTION(alignment); 361 NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT, 362 PROLOG_ADDITION_2REGS) 363 mfspr r14,SPRN_DEAR 364 mfspr r15,SPRN_ESR 365 EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP) 366 b alignment_more /* no room, go out of line */ 367 368/* Program Interrupt */ 369 START_EXCEPTION(program); 370 NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM, 371 PROLOG_ADDITION_1REG) 372 mfspr r14,SPRN_ESR 373 EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE) 374 std r14,_DSISR(r1) 375 addi r3,r1,STACK_FRAME_OVERHEAD 376 ld r14,PACA_EXGEN+EX_R14(r13) 377 bl .save_nvgprs 378 bl .program_check_exception 379 b .ret_from_except 380 381/* Floating Point Unavailable Interrupt */ 382 START_EXCEPTION(fp_unavailable); 383 NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL, 384 PROLOG_ADDITION_NONE) 385 /* we can probably do a shorter exception entry for that one... */ 386 EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP) 387 ld r12,_MSR(r1) 388 andi. r0,r12,MSR_PR; 389 beq- 1f 390 bl .load_up_fpu 391 b fast_exception_return 3921: INTS_DISABLE 393 bl .save_nvgprs 394 addi r3,r1,STACK_FRAME_OVERHEAD 395 bl .kernel_fp_unavailable_exception 396 b .ret_from_except 397 398/* Decrementer Interrupt */ 399 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER, 400 decrementer, .timer_interrupt, ACK_DEC) 401 402/* Fixed Interval Timer Interrupt */ 403 MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT, 404 fixed_interval, .unknown_exception, ACK_FIT) 405 406/* Watchdog Timer Interrupt */ 407 START_EXCEPTION(watchdog); 408 CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG, 409 PROLOG_ADDITION_NONE) 410// EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE) 411// bl special_reg_save_crit 412// CHECK_NAPPING(); 413// addi r3,r1,STACK_FRAME_OVERHEAD 414// bl .unknown_exception 415// b ret_from_crit_except 416 b . 417 418/* System Call Interrupt */ 419 START_EXCEPTION(system_call) 420 mr r9,r13 /* keep a copy of userland r13 */ 421 mfspr r11,SPRN_SRR0 /* get return address */ 422 mfspr r12,SPRN_SRR1 /* get previous MSR */ 423 mfspr r13,SPRN_SPRG_PACA /* get our PACA */ 424 b system_call_common 425 426/* Auxiliary Processor Unavailable Interrupt */ 427 START_EXCEPTION(ap_unavailable); 428 NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL, 429 PROLOG_ADDITION_NONE) 430 EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_DISABLE) 431 bl .save_nvgprs 432 addi r3,r1,STACK_FRAME_OVERHEAD 433 bl .unknown_exception 434 b .ret_from_except 435 436/* Debug exception as a critical interrupt*/ 437 START_EXCEPTION(debug_crit); 438 CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, 439 PROLOG_ADDITION_2REGS) 440 441 /* 442 * If there is a single step or branch-taken exception in an 443 * exception entry sequence, it was probably meant to apply to 444 * the code where the exception occurred (since exception entry 445 * doesn't turn off DE automatically). We simulate the effect 446 * of turning off DE on entry to an exception handler by turning 447 * off DE in the CSRR1 value and clearing the debug status. 448 */ 449 450 mfspr r14,SPRN_DBSR /* check single-step/branch taken */ 451 andis. r15,r14,DBSR_IC@h 452 beq+ 1f 453 454 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e) 455 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e) 456 cmpld cr0,r10,r14 457 cmpld cr1,r10,r15 458 blt+ cr0,1f 459 bge+ cr1,1f 460 461 /* here it looks like we got an inappropriate debug exception. */ 462 lis r14,DBSR_IC@h /* clear the IC event */ 463 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */ 464 mtspr SPRN_DBSR,r14 465 mtspr SPRN_CSRR1,r11 466 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */ 467 ld r1,PACA_EXCRIT+EX_R1(r13) 468 ld r14,PACA_EXCRIT+EX_R14(r13) 469 ld r15,PACA_EXCRIT+EX_R15(r13) 470 mtcr r10 471 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */ 472 ld r11,PACA_EXCRIT+EX_R11(r13) 473 ld r13,PACA_EXCRIT+EX_R13(r13) 474 rfci 475 476 /* Normal debug exception */ 477 /* XXX We only handle coming from userspace for now since we can't 478 * quite save properly an interrupted kernel state yet 479 */ 4801: andi. r14,r11,MSR_PR; /* check for userspace again */ 481 beq kernel_dbg_exc; /* if from kernel mode */ 482 483 /* Now we mash up things to make it look like we are coming on a 484 * normal exception 485 */ 486 ld r15,PACA_EXCRIT+EX_R13(r13) 487 mtspr SPRN_SPRG_GEN_SCRATCH,r15 488 mfspr r14,SPRN_DBSR 489 EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE) 490 std r14,_DSISR(r1) 491 addi r3,r1,STACK_FRAME_OVERHEAD 492 mr r4,r14 493 ld r14,PACA_EXCRIT+EX_R14(r13) 494 ld r15,PACA_EXCRIT+EX_R15(r13) 495 bl .save_nvgprs 496 bl .DebugException 497 b .ret_from_except 498 499kernel_dbg_exc: 500 b . /* NYI */ 501 502/* Debug exception as a debug interrupt*/ 503 START_EXCEPTION(debug_debug); 504 DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, 505 PROLOG_ADDITION_2REGS) 506 507 /* 508 * If there is a single step or branch-taken exception in an 509 * exception entry sequence, it was probably meant to apply to 510 * the code where the exception occurred (since exception entry 511 * doesn't turn off DE automatically). We simulate the effect 512 * of turning off DE on entry to an exception handler by turning 513 * off DE in the DSRR1 value and clearing the debug status. 514 */ 515 516 mfspr r14,SPRN_DBSR /* check single-step/branch taken */ 517 andis. r15,r14,DBSR_IC@h 518 beq+ 1f 519 520 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e) 521 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e) 522 cmpld cr0,r10,r14 523 cmpld cr1,r10,r15 524 blt+ cr0,1f 525 bge+ cr1,1f 526 527 /* here it looks like we got an inappropriate debug exception. */ 528 lis r14,DBSR_IC@h /* clear the IC event */ 529 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */ 530 mtspr SPRN_DBSR,r14 531 mtspr SPRN_DSRR1,r11 532 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */ 533 ld r1,PACA_EXDBG+EX_R1(r13) 534 ld r14,PACA_EXDBG+EX_R14(r13) 535 ld r15,PACA_EXDBG+EX_R15(r13) 536 mtcr r10 537 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */ 538 ld r11,PACA_EXDBG+EX_R11(r13) 539 mfspr r13,SPRN_SPRG_DBG_SCRATCH 540 rfdi 541 542 /* Normal debug exception */ 543 /* XXX We only handle coming from userspace for now since we can't 544 * quite save properly an interrupted kernel state yet 545 */ 5461: andi. r14,r11,MSR_PR; /* check for userspace again */ 547 beq kernel_dbg_exc; /* if from kernel mode */ 548 549 /* Now we mash up things to make it look like we are coming on a 550 * normal exception 551 */ 552 mfspr r15,SPRN_SPRG_DBG_SCRATCH 553 mtspr SPRN_SPRG_GEN_SCRATCH,r15 554 mfspr r14,SPRN_DBSR 555 EXCEPTION_COMMON(0xd08, PACA_EXDBG, INTS_DISABLE) 556 std r14,_DSISR(r1) 557 addi r3,r1,STACK_FRAME_OVERHEAD 558 mr r4,r14 559 ld r14,PACA_EXDBG+EX_R14(r13) 560 ld r15,PACA_EXDBG+EX_R15(r13) 561 bl .save_nvgprs 562 bl .DebugException 563 b .ret_from_except 564 565 START_EXCEPTION(perfmon); 566 NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR, 567 PROLOG_ADDITION_NONE) 568 EXCEPTION_COMMON(0x260, PACA_EXGEN, INTS_DISABLE) 569 addi r3,r1,STACK_FRAME_OVERHEAD 570 bl .performance_monitor_exception 571 b .ret_from_except_lite 572 573/* Doorbell interrupt */ 574 MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL, 575 doorbell, .doorbell_exception, ACK_NONE) 576 577/* Doorbell critical Interrupt */ 578 START_EXCEPTION(doorbell_crit); 579 CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL, 580 PROLOG_ADDITION_NONE) 581// EXCEPTION_COMMON(0x2a0, PACA_EXCRIT, INTS_DISABLE) 582// bl special_reg_save_crit 583// CHECK_NAPPING(); 584// addi r3,r1,STACK_FRAME_OVERHEAD 585// bl .doorbell_critical_exception 586// b ret_from_crit_except 587 b . 588 589/* 590 * Guest doorbell interrupt 591 * This general exception use GSRRx save/restore registers 592 */ 593 START_EXCEPTION(guest_doorbell); 594 GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL, 595 PROLOG_ADDITION_NONE) 596 EXCEPTION_COMMON(0x2c0, PACA_EXGEN, INTS_KEEP) 597 addi r3,r1,STACK_FRAME_OVERHEAD 598 bl .save_nvgprs 599 INTS_RESTORE_HARD 600 bl .unknown_exception 601 b .ret_from_except 602 603/* Guest Doorbell critical Interrupt */ 604 START_EXCEPTION(guest_doorbell_crit); 605 CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT, 606 PROLOG_ADDITION_NONE) 607// EXCEPTION_COMMON(0x2e0, PACA_EXCRIT, INTS_DISABLE) 608// bl special_reg_save_crit 609// CHECK_NAPPING(); 610// addi r3,r1,STACK_FRAME_OVERHEAD 611// bl .guest_doorbell_critical_exception 612// b ret_from_crit_except 613 b . 614 615/* Hypervisor call */ 616 START_EXCEPTION(hypercall); 617 NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL, 618 PROLOG_ADDITION_NONE) 619 EXCEPTION_COMMON(0x310, PACA_EXGEN, INTS_KEEP) 620 addi r3,r1,STACK_FRAME_OVERHEAD 621 bl .save_nvgprs 622 INTS_RESTORE_HARD 623 bl .unknown_exception 624 b .ret_from_except 625 626/* Embedded Hypervisor priviledged */ 627 START_EXCEPTION(ehpriv); 628 NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV, 629 PROLOG_ADDITION_NONE) 630 EXCEPTION_COMMON(0x320, PACA_EXGEN, INTS_KEEP) 631 addi r3,r1,STACK_FRAME_OVERHEAD 632 bl .save_nvgprs 633 INTS_RESTORE_HARD 634 bl .unknown_exception 635 b .ret_from_except 636 637/* 638 * An interrupt came in while soft-disabled; We mark paca->irq_happened 639 * accordingly and if the interrupt is level sensitive, we hard disable 640 */ 641 642.macro masked_interrupt_book3e paca_irq full_mask 643 lbz r10,PACAIRQHAPPENED(r13) 644 ori r10,r10,\paca_irq 645 stb r10,PACAIRQHAPPENED(r13) 646 647 .if \full_mask == 1 648 rldicl r10,r11,48,1 /* clear MSR_EE */ 649 rotldi r11,r10,16 650 mtspr SPRN_SRR1,r11 651 .endif 652 653 lwz r11,PACA_EXGEN+EX_CR(r13) 654 mtcr r11 655 ld r10,PACA_EXGEN+EX_R10(r13) 656 ld r11,PACA_EXGEN+EX_R11(r13) 657 mfspr r13,SPRN_SPRG_GEN_SCRATCH 658 rfi 659 b . 660.endm 661 662masked_interrupt_book3e_0x500: 663 // XXX When adding support for EPR, use PACA_IRQ_EE_EDGE 664 masked_interrupt_book3e PACA_IRQ_EE 1 665 666masked_interrupt_book3e_0x900: 667 ACK_DEC(r10); 668 masked_interrupt_book3e PACA_IRQ_DEC 0 669 670masked_interrupt_book3e_0x980: 671 ACK_FIT(r10); 672 masked_interrupt_book3e PACA_IRQ_DEC 0 673 674masked_interrupt_book3e_0x280: 675masked_interrupt_book3e_0x2c0: 676 masked_interrupt_book3e PACA_IRQ_DBELL 0 677 678/* 679 * Called from arch_local_irq_enable when an interrupt needs 680 * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280 681 * to indicate the kind of interrupt. MSR:EE is already off. 682 * We generate a stackframe like if a real interrupt had happened. 683 * 684 * Note: While MSR:EE is off, we need to make sure that _MSR 685 * in the generated frame has EE set to 1 or the exception 686 * handler will not properly re-enable them. 687 */ 688_GLOBAL(__replay_interrupt) 689 /* We are going to jump to the exception common code which 690 * will retrieve various register values from the PACA which 691 * we don't give a damn about. 692 */ 693 mflr r10 694 mfmsr r11 695 mfcr r4 696 mtspr SPRN_SPRG_GEN_SCRATCH,r13; 697 std r1,PACA_EXGEN+EX_R1(r13); 698 stw r4,PACA_EXGEN+EX_CR(r13); 699 ori r11,r11,MSR_EE 700 subi r1,r1,INT_FRAME_SIZE; 701 cmpwi cr0,r3,0x500 702 beq exc_0x500_common 703 cmpwi cr0,r3,0x900 704 beq exc_0x900_common 705 cmpwi cr0,r3,0x280 706 beq exc_0x280_common 707 blr 708 709 710/* 711 * This is called from 0x300 and 0x400 handlers after the prologs with 712 * r14 and r15 containing the fault address and error code, with the 713 * original values stashed away in the PACA 714 */ 715storage_fault_common: 716 std r14,_DAR(r1) 717 std r15,_DSISR(r1) 718 addi r3,r1,STACK_FRAME_OVERHEAD 719 mr r4,r14 720 mr r5,r15 721 ld r14,PACA_EXGEN+EX_R14(r13) 722 ld r15,PACA_EXGEN+EX_R15(r13) 723 bl .do_page_fault 724 cmpdi r3,0 725 bne- 1f 726 b .ret_from_except_lite 7271: bl .save_nvgprs 728 mr r5,r3 729 addi r3,r1,STACK_FRAME_OVERHEAD 730 ld r4,_DAR(r1) 731 bl .bad_page_fault 732 b .ret_from_except 733 734/* 735 * Alignment exception doesn't fit entirely in the 0x100 bytes so it 736 * continues here. 737 */ 738alignment_more: 739 std r14,_DAR(r1) 740 std r15,_DSISR(r1) 741 addi r3,r1,STACK_FRAME_OVERHEAD 742 ld r14,PACA_EXGEN+EX_R14(r13) 743 ld r15,PACA_EXGEN+EX_R15(r13) 744 bl .save_nvgprs 745 INTS_RESTORE_HARD 746 bl .alignment_exception 747 b .ret_from_except 748 749/* 750 * We branch here from entry_64.S for the last stage of the exception 751 * return code path. MSR:EE is expected to be off at that point 752 */ 753_GLOBAL(exception_return_book3e) 754 b 1f 755 756/* This is the return from load_up_fpu fast path which could do with 757 * less GPR restores in fact, but for now we have a single return path 758 */ 759 .globl fast_exception_return 760fast_exception_return: 761 wrteei 0 7621: mr r0,r13 763 ld r10,_MSR(r1) 764 REST_4GPRS(2, r1) 765 andi. r6,r10,MSR_PR 766 REST_2GPRS(6, r1) 767 beq 1f 768 ACCOUNT_CPU_USER_EXIT(r10, r11) 769 ld r0,GPR13(r1) 770 7711: stdcx. r0,0,r1 /* to clear the reservation */ 772 773 ld r8,_CCR(r1) 774 ld r9,_LINK(r1) 775 ld r10,_CTR(r1) 776 ld r11,_XER(r1) 777 mtcr r8 778 mtlr r9 779 mtctr r10 780 mtxer r11 781 REST_2GPRS(8, r1) 782 ld r10,GPR10(r1) 783 ld r11,GPR11(r1) 784 ld r12,GPR12(r1) 785 mtspr SPRN_SPRG_GEN_SCRATCH,r0 786 787 std r10,PACA_EXGEN+EX_R10(r13); 788 std r11,PACA_EXGEN+EX_R11(r13); 789 ld r10,_NIP(r1) 790 ld r11,_MSR(r1) 791 ld r0,GPR0(r1) 792 ld r1,GPR1(r1) 793 mtspr SPRN_SRR0,r10 794 mtspr SPRN_SRR1,r11 795 ld r10,PACA_EXGEN+EX_R10(r13) 796 ld r11,PACA_EXGEN+EX_R11(r13) 797 mfspr r13,SPRN_SPRG_GEN_SCRATCH 798 rfi 799 800/* 801 * Trampolines used when spotting a bad kernel stack pointer in 802 * the exception entry code. 803 * 804 * TODO: move some bits like SRR0 read to trampoline, pass PACA 805 * index around, etc... to handle crit & mcheck 806 */ 807BAD_STACK_TRAMPOLINE(0x000) 808BAD_STACK_TRAMPOLINE(0x100) 809BAD_STACK_TRAMPOLINE(0x200) 810BAD_STACK_TRAMPOLINE(0x260) 811BAD_STACK_TRAMPOLINE(0x280) 812BAD_STACK_TRAMPOLINE(0x2a0) 813BAD_STACK_TRAMPOLINE(0x2c0) 814BAD_STACK_TRAMPOLINE(0x2e0) 815BAD_STACK_TRAMPOLINE(0x300) 816BAD_STACK_TRAMPOLINE(0x310) 817BAD_STACK_TRAMPOLINE(0x320) 818BAD_STACK_TRAMPOLINE(0x400) 819BAD_STACK_TRAMPOLINE(0x500) 820BAD_STACK_TRAMPOLINE(0x600) 821BAD_STACK_TRAMPOLINE(0x700) 822BAD_STACK_TRAMPOLINE(0x800) 823BAD_STACK_TRAMPOLINE(0x900) 824BAD_STACK_TRAMPOLINE(0x980) 825BAD_STACK_TRAMPOLINE(0x9f0) 826BAD_STACK_TRAMPOLINE(0xa00) 827BAD_STACK_TRAMPOLINE(0xb00) 828BAD_STACK_TRAMPOLINE(0xc00) 829BAD_STACK_TRAMPOLINE(0xd00) 830BAD_STACK_TRAMPOLINE(0xd08) 831BAD_STACK_TRAMPOLINE(0xe00) 832BAD_STACK_TRAMPOLINE(0xf00) 833BAD_STACK_TRAMPOLINE(0xf20) 834 835 .globl bad_stack_book3e 836bad_stack_book3e: 837 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */ 838 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */ 839 ld r1,PACAEMERGSP(r13) 840 subi r1,r1,64+INT_FRAME_SIZE 841 std r10,_NIP(r1) 842 std r11,_MSR(r1) 843 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */ 844 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */ 845 std r10,GPR1(r1) 846 std r11,_CCR(r1) 847 mfspr r10,SPRN_DEAR 848 mfspr r11,SPRN_ESR 849 std r10,_DAR(r1) 850 std r11,_DSISR(r1) 851 std r0,GPR0(r1); /* save r0 in stackframe */ \ 852 std r2,GPR2(r1); /* save r2 in stackframe */ \ 853 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 854 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 855 std r9,GPR9(r1); /* save r9 in stackframe */ \ 856 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \ 857 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \ 858 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \ 859 std r3,GPR10(r1); /* save r10 to stackframe */ \ 860 std r4,GPR11(r1); /* save r11 to stackframe */ \ 861 std r12,GPR12(r1); /* save r12 in stackframe */ \ 862 std r5,GPR13(r1); /* save it to stackframe */ \ 863 mflr r10 864 mfctr r11 865 mfxer r12 866 std r10,_LINK(r1) 867 std r11,_CTR(r1) 868 std r12,_XER(r1) 869 SAVE_10GPRS(14,r1) 870 SAVE_8GPRS(24,r1) 871 lhz r12,PACA_TRAP_SAVE(r13) 872 std r12,_TRAP(r1) 873 addi r11,r1,INT_FRAME_SIZE 874 std r11,0(r1) 875 li r12,0 876 std r12,0(r11) 877 ld r2,PACATOC(r13) 8781: addi r3,r1,STACK_FRAME_OVERHEAD 879 bl .kernel_bad_stack 880 b 1b 881 882/* 883 * Setup the initial TLB for a core. This current implementation 884 * assume that whatever we are running off will not conflict with 885 * the new mapping at PAGE_OFFSET. 886 */ 887_GLOBAL(initial_tlb_book3e) 888 889 /* Look for the first TLB with IPROT set */ 890 mfspr r4,SPRN_TLB0CFG 891 andi. r3,r4,TLBnCFG_IPROT 892 lis r3,MAS0_TLBSEL(0)@h 893 bne found_iprot 894 895 mfspr r4,SPRN_TLB1CFG 896 andi. r3,r4,TLBnCFG_IPROT 897 lis r3,MAS0_TLBSEL(1)@h 898 bne found_iprot 899 900 mfspr r4,SPRN_TLB2CFG 901 andi. r3,r4,TLBnCFG_IPROT 902 lis r3,MAS0_TLBSEL(2)@h 903 bne found_iprot 904 905 lis r3,MAS0_TLBSEL(3)@h 906 mfspr r4,SPRN_TLB3CFG 907 /* fall through */ 908 909found_iprot: 910 andi. r5,r4,TLBnCFG_HES 911 bne have_hes 912 913 mflr r8 /* save LR */ 914/* 1. Find the index of the entry we're executing in 915 * 916 * r3 = MAS0_TLBSEL (for the iprot array) 917 * r4 = SPRN_TLBnCFG 918 */ 919 bl invstr /* Find our address */ 920invstr: mflr r6 /* Make it accessible */ 921 mfmsr r7 922 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */ 923 mfspr r7,SPRN_PID 924 slwi r7,r7,16 925 or r7,r7,r5 926 mtspr SPRN_MAS6,r7 927 tlbsx 0,r6 /* search MSR[IS], SPID=PID */ 928 929 mfspr r3,SPRN_MAS0 930 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */ 931 932 mfspr r7,SPRN_MAS1 /* Insure IPROT set */ 933 oris r7,r7,MAS1_IPROT@h 934 mtspr SPRN_MAS1,r7 935 tlbwe 936 937/* 2. Invalidate all entries except the entry we're executing in 938 * 939 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 940 * r4 = SPRN_TLBnCFG 941 * r5 = ESEL of entry we are running in 942 */ 943 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */ 944 li r6,0 /* Set Entry counter to 0 */ 9451: mr r7,r3 /* Set MAS0(TLBSEL) */ 946 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ 947 mtspr SPRN_MAS0,r7 948 tlbre 949 mfspr r7,SPRN_MAS1 950 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ 951 cmpw r5,r6 952 beq skpinv /* Dont update the current execution TLB */ 953 mtspr SPRN_MAS1,r7 954 tlbwe 955 isync 956skpinv: addi r6,r6,1 /* Increment */ 957 cmpw r6,r4 /* Are we done? */ 958 bne 1b /* If not, repeat */ 959 960 /* Invalidate all TLBs */ 961 PPC_TLBILX_ALL(0,R0) 962 sync 963 isync 964 965/* 3. Setup a temp mapping and jump to it 966 * 967 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 968 * r5 = ESEL of entry we are running in 969 */ 970 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */ 971 addi r7,r7,0x1 972 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */ 973 mtspr SPRN_MAS0,r4 974 tlbre 975 976 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */ 977 mtspr SPRN_MAS0,r4 978 979 mfspr r7,SPRN_MAS1 980 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */ 981 mtspr SPRN_MAS1,r6 982 983 tlbwe 984 985 mfmsr r6 986 xori r6,r6,MSR_IS 987 mtspr SPRN_SRR1,r6 988 bl 1f /* Find our address */ 9891: mflr r6 990 addi r6,r6,(2f - 1b) 991 mtspr SPRN_SRR0,r6 992 rfi 9932: 994 995/* 4. Clear out PIDs & Search info 996 * 997 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 998 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 999 * r5 = MAS3 1000 */ 1001 li r6,0 1002 mtspr SPRN_MAS6,r6 1003 mtspr SPRN_PID,r6 1004 1005/* 5. Invalidate mapping we started in 1006 * 1007 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1008 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1009 * r5 = MAS3 1010 */ 1011 mtspr SPRN_MAS0,r3 1012 tlbre 1013 mfspr r6,SPRN_MAS1 1014 rlwinm r6,r6,0,2,0 /* clear IPROT */ 1015 mtspr SPRN_MAS1,r6 1016 tlbwe 1017 1018 /* Invalidate TLB1 */ 1019 PPC_TLBILX_ALL(0,R0) 1020 sync 1021 isync 1022 1023/* The mapping only needs to be cache-coherent on SMP */ 1024#ifdef CONFIG_SMP 1025#define M_IF_SMP MAS2_M 1026#else 1027#define M_IF_SMP 0 1028#endif 1029 1030/* 6. Setup KERNELBASE mapping in TLB[0] 1031 * 1032 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1033 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1034 * r5 = MAS3 1035 */ 1036 rlwinm r3,r3,0,16,3 /* clear ESEL */ 1037 mtspr SPRN_MAS0,r3 1038 lis r6,(MAS1_VALID|MAS1_IPROT)@h 1039 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l 1040 mtspr SPRN_MAS1,r6 1041 1042 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP) 1043 mtspr SPRN_MAS2,r6 1044 1045 rlwinm r5,r5,0,0,25 1046 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX 1047 mtspr SPRN_MAS3,r5 1048 li r5,-1 1049 rlwinm r5,r5,0,0,25 1050 1051 tlbwe 1052 1053/* 7. Jump to KERNELBASE mapping 1054 * 1055 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1056 */ 1057 /* Now we branch the new virtual address mapped by this entry */ 1058 LOAD_REG_IMMEDIATE(r6,2f) 1059 lis r7,MSR_KERNEL@h 1060 ori r7,r7,MSR_KERNEL@l 1061 mtspr SPRN_SRR0,r6 1062 mtspr SPRN_SRR1,r7 1063 rfi /* start execution out of TLB1[0] entry */ 10642: 1065 1066/* 8. Clear out the temp mapping 1067 * 1068 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1069 */ 1070 mtspr SPRN_MAS0,r4 1071 tlbre 1072 mfspr r5,SPRN_MAS1 1073 rlwinm r5,r5,0,2,0 /* clear IPROT */ 1074 mtspr SPRN_MAS1,r5 1075 tlbwe 1076 1077 /* Invalidate TLB1 */ 1078 PPC_TLBILX_ALL(0,R0) 1079 sync 1080 isync 1081 1082 /* We translate LR and return */ 1083 tovirt(r8,r8) 1084 mtlr r8 1085 blr 1086 1087have_hes: 1088 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the 1089 * kernel linear mapping. We also set MAS8 once for all here though 1090 * that will have to be made dependent on whether we are running under 1091 * a hypervisor I suppose. 1092 */ 1093 1094 /* BEWARE, MAGIC 1095 * This code is called as an ordinary function on the boot CPU. But to 1096 * avoid duplication, this code is also used in SCOM bringup of 1097 * secondary CPUs. We read the code between the initial_tlb_code_start 1098 * and initial_tlb_code_end labels one instruction at a time and RAM it 1099 * into the new core via SCOM. That doesn't process branches, so there 1100 * must be none between those two labels. It also means if this code 1101 * ever takes any parameters, the SCOM code must also be updated to 1102 * provide them. 1103 */ 1104 .globl a2_tlbinit_code_start 1105a2_tlbinit_code_start: 1106 1107 ori r11,r3,MAS0_WQ_ALLWAYS 1108 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */ 1109 mtspr SPRN_MAS0,r11 1110 lis r3,(MAS1_VALID | MAS1_IPROT)@h 1111 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT 1112 mtspr SPRN_MAS1,r3 1113 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M) 1114 mtspr SPRN_MAS2,r3 1115 li r3,MAS3_SR | MAS3_SW | MAS3_SX 1116 mtspr SPRN_MAS7_MAS3,r3 1117 li r3,0 1118 mtspr SPRN_MAS8,r3 1119 1120 /* Write the TLB entry */ 1121 tlbwe 1122 1123 .globl a2_tlbinit_after_linear_map 1124a2_tlbinit_after_linear_map: 1125 1126 /* Now we branch the new virtual address mapped by this entry */ 1127 LOAD_REG_IMMEDIATE(r3,1f) 1128 mtctr r3 1129 bctr 1130 11311: /* We are now running at PAGE_OFFSET, clean the TLB of everything 1132 * else (including IPROTed things left by firmware) 1133 * r4 = TLBnCFG 1134 * r3 = current address (more or less) 1135 */ 1136 1137 li r5,0 1138 mtspr SPRN_MAS6,r5 1139 tlbsx 0,r3 1140 1141 rlwinm r9,r4,0,TLBnCFG_N_ENTRY 1142 rlwinm r10,r4,8,0xff 1143 addi r10,r10,-1 /* Get inner loop mask */ 1144 1145 li r3,1 1146 1147 mfspr r5,SPRN_MAS1 1148 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT)) 1149 1150 mfspr r6,SPRN_MAS2 1151 rldicr r6,r6,0,51 /* Extract EPN */ 1152 1153 mfspr r7,SPRN_MAS0 1154 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */ 1155 1156 rlwinm r8,r7,16,0xfff /* Extract ESEL */ 1157 11582: add r4,r3,r8 1159 and r4,r4,r10 1160 1161 rlwimi r7,r4,16,MAS0_ESEL_MASK 1162 1163 mtspr SPRN_MAS0,r7 1164 mtspr SPRN_MAS1,r5 1165 mtspr SPRN_MAS2,r6 1166 tlbwe 1167 1168 addi r3,r3,1 1169 and. r4,r3,r10 1170 1171 bne 3f 1172 addis r6,r6,(1<<30)@h 11733: 1174 cmpw r3,r9 1175 blt 2b 1176 1177 .globl a2_tlbinit_after_iprot_flush 1178a2_tlbinit_after_iprot_flush: 1179 1180#ifdef CONFIG_PPC_EARLY_DEBUG_WSP 1181 /* Now establish early debug mappings if applicable */ 1182 /* Restore the MAS0 we used for linear mapping load */ 1183 mtspr SPRN_MAS0,r11 1184 1185 lis r3,(MAS1_VALID | MAS1_IPROT)@h 1186 ori r3,r3,(BOOK3E_PAGESZ_4K << MAS1_TSIZE_SHIFT) 1187 mtspr SPRN_MAS1,r3 1188 LOAD_REG_IMMEDIATE(r3, WSP_UART_VIRT | MAS2_I | MAS2_G) 1189 mtspr SPRN_MAS2,r3 1190 LOAD_REG_IMMEDIATE(r3, WSP_UART_PHYS | MAS3_SR | MAS3_SW) 1191 mtspr SPRN_MAS7_MAS3,r3 1192 /* re-use the MAS8 value from the linear mapping */ 1193 tlbwe 1194#endif /* CONFIG_PPC_EARLY_DEBUG_WSP */ 1195 1196 PPC_TLBILX(0,0,R0) 1197 sync 1198 isync 1199 1200 .globl a2_tlbinit_code_end 1201a2_tlbinit_code_end: 1202 1203 /* We translate LR and return */ 1204 mflr r3 1205 tovirt(r3,r3) 1206 mtlr r3 1207 blr 1208 1209/* 1210 * Main entry (boot CPU, thread 0) 1211 * 1212 * We enter here from head_64.S, possibly after the prom_init trampoline 1213 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits 1214 * mode. Anything else is as it was left by the bootloader 1215 * 1216 * Initial requirements of this port: 1217 * 1218 * - Kernel loaded at 0 physical 1219 * - A good lump of memory mapped 0:0 by UTLB entry 0 1220 * - MSR:IS & MSR:DS set to 0 1221 * 1222 * Note that some of the above requirements will be relaxed in the future 1223 * as the kernel becomes smarter at dealing with different initial conditions 1224 * but for now you have to be careful 1225 */ 1226_GLOBAL(start_initialization_book3e) 1227 mflr r28 1228 1229 /* First, we need to setup some initial TLBs to map the kernel 1230 * text, data and bss at PAGE_OFFSET. We don't have a real mode 1231 * and always use AS 0, so we just set it up to match our link 1232 * address and never use 0 based addresses. 1233 */ 1234 bl .initial_tlb_book3e 1235 1236 /* Init global core bits */ 1237 bl .init_core_book3e 1238 1239 /* Init per-thread bits */ 1240 bl .init_thread_book3e 1241 1242 /* Return to common init code */ 1243 tovirt(r28,r28) 1244 mtlr r28 1245 blr 1246 1247 1248/* 1249 * Secondary core/processor entry 1250 * 1251 * This is entered for thread 0 of a secondary core, all other threads 1252 * are expected to be stopped. It's similar to start_initialization_book3e 1253 * except that it's generally entered from the holding loop in head_64.S 1254 * after CPUs have been gathered by Open Firmware. 1255 * 1256 * We assume we are in 32 bits mode running with whatever TLB entry was 1257 * set for us by the firmware or POR engine. 1258 */ 1259_GLOBAL(book3e_secondary_core_init_tlb_set) 1260 li r4,1 1261 b .generic_secondary_smp_init 1262 1263_GLOBAL(book3e_secondary_core_init) 1264 mflr r28 1265 1266 /* Do we need to setup initial TLB entry ? */ 1267 cmplwi r4,0 1268 bne 2f 1269 1270 /* Setup TLB for this core */ 1271 bl .initial_tlb_book3e 1272 1273 /* We can return from the above running at a different 1274 * address, so recalculate r2 (TOC) 1275 */ 1276 bl .relative_toc 1277 1278 /* Init global core bits */ 12792: bl .init_core_book3e 1280 1281 /* Init per-thread bits */ 12823: bl .init_thread_book3e 1283 1284 /* Return to common init code at proper virtual address. 1285 * 1286 * Due to various previous assumptions, we know we entered this 1287 * function at either the final PAGE_OFFSET mapping or using a 1288 * 1:1 mapping at 0, so we don't bother doing a complicated check 1289 * here, we just ensure the return address has the right top bits. 1290 * 1291 * Note that if we ever want to be smarter about where we can be 1292 * started from, we have to be careful that by the time we reach 1293 * the code below we may already be running at a different location 1294 * than the one we were called from since initial_tlb_book3e can 1295 * have moved us already. 1296 */ 1297 cmpdi cr0,r28,0 1298 blt 1f 1299 lis r3,PAGE_OFFSET@highest 1300 sldi r3,r3,32 1301 or r28,r28,r3 13021: mtlr r28 1303 blr 1304 1305_GLOBAL(book3e_secondary_thread_init) 1306 mflr r28 1307 b 3b 1308 1309_STATIC(init_core_book3e) 1310 /* Establish the interrupt vector base */ 1311 LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e) 1312 mtspr SPRN_IVPR,r3 1313 sync 1314 blr 1315 1316_STATIC(init_thread_book3e) 1317 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h 1318 mtspr SPRN_EPCR,r3 1319 1320 /* Make sure interrupts are off */ 1321 wrteei 0 1322 1323 /* disable all timers and clear out status */ 1324 li r3,0 1325 mtspr SPRN_TCR,r3 1326 mfspr r3,SPRN_TSR 1327 mtspr SPRN_TSR,r3 1328 1329 blr 1330 1331_GLOBAL(__setup_base_ivors) 1332 SET_IVOR(0, 0x020) /* Critical Input */ 1333 SET_IVOR(1, 0x000) /* Machine Check */ 1334 SET_IVOR(2, 0x060) /* Data Storage */ 1335 SET_IVOR(3, 0x080) /* Instruction Storage */ 1336 SET_IVOR(4, 0x0a0) /* External Input */ 1337 SET_IVOR(5, 0x0c0) /* Alignment */ 1338 SET_IVOR(6, 0x0e0) /* Program */ 1339 SET_IVOR(7, 0x100) /* FP Unavailable */ 1340 SET_IVOR(8, 0x120) /* System Call */ 1341 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ 1342 SET_IVOR(10, 0x160) /* Decrementer */ 1343 SET_IVOR(11, 0x180) /* Fixed Interval Timer */ 1344 SET_IVOR(12, 0x1a0) /* Watchdog Timer */ 1345 SET_IVOR(13, 0x1c0) /* Data TLB Error */ 1346 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ 1347 SET_IVOR(15, 0x040) /* Debug */ 1348 1349 sync 1350 1351 blr 1352 1353_GLOBAL(setup_perfmon_ivor) 1354 SET_IVOR(35, 0x260) /* Performance Monitor */ 1355 blr 1356 1357_GLOBAL(setup_doorbell_ivors) 1358 SET_IVOR(36, 0x280) /* Processor Doorbell */ 1359 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */ 1360 blr 1361 1362_GLOBAL(setup_ehv_ivors) 1363 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */ 1364 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */ 1365 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */ 1366 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */ 1367 blr 1368