1 #ifndef _ASM_POWERPC_PROCESSOR_H 2 #define _ASM_POWERPC_PROCESSOR_H 3 4 /* 5 * Copyright (C) 2001 PPC 64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <asm/reg.h> 14 15 #ifdef CONFIG_VSX 16 #define TS_FPRWIDTH 2 17 18 #ifdef __BIG_ENDIAN__ 19 #define TS_FPROFFSET 0 20 #define TS_VSRLOWOFFSET 1 21 #else 22 #define TS_FPROFFSET 1 23 #define TS_VSRLOWOFFSET 0 24 #endif 25 26 #else 27 #define TS_FPRWIDTH 1 28 #define TS_FPROFFSET 0 29 #endif 30 31 #ifdef CONFIG_PPC64 32 /* Default SMT priority is set to 3. Use 11- 13bits to save priority. */ 33 #define PPR_PRIORITY 3 34 #ifdef __ASSEMBLY__ 35 #define INIT_PPR (PPR_PRIORITY << 50) 36 #else 37 #define INIT_PPR ((u64)PPR_PRIORITY << 50) 38 #endif /* __ASSEMBLY__ */ 39 #endif /* CONFIG_PPC64 */ 40 41 #ifndef __ASSEMBLY__ 42 #include <linux/compiler.h> 43 #include <linux/cache.h> 44 #include <asm/ptrace.h> 45 #include <asm/types.h> 46 #include <asm/hw_breakpoint.h> 47 48 /* We do _not_ want to define new machine types at all, those must die 49 * in favor of using the device-tree 50 * -- BenH. 51 */ 52 53 /* PREP sub-platform types. Unused */ 54 #define _PREP_Motorola 0x01 /* motorola prep */ 55 #define _PREP_Firm 0x02 /* firmworks prep */ 56 #define _PREP_IBM 0x00 /* ibm prep */ 57 #define _PREP_Bull 0x03 /* bull prep */ 58 59 /* CHRP sub-platform types. These are arbitrary */ 60 #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ 61 #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ 62 #define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */ 63 #define _CHRP_briq 0x07 /* TotalImpact's briQ */ 64 65 #if defined(__KERNEL__) && defined(CONFIG_PPC32) 66 67 extern int _chrp_type; 68 69 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */ 70 71 /* 72 * Default implementation of macro that returns current 73 * instruction pointer ("program counter"). 74 */ 75 #define current_text_addr() ({ __label__ _l; _l: &&_l;}) 76 77 /* Macros for adjusting thread priority (hardware multi-threading) */ 78 #define HMT_very_low() asm volatile("or 31,31,31 # very low priority") 79 #define HMT_low() asm volatile("or 1,1,1 # low priority") 80 #define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority") 81 #define HMT_medium() asm volatile("or 2,2,2 # medium priority") 82 #define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority") 83 #define HMT_high() asm volatile("or 3,3,3 # high priority") 84 85 #ifdef __KERNEL__ 86 87 struct task_struct; 88 void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp); 89 void release_thread(struct task_struct *); 90 91 #ifdef CONFIG_PPC32 92 93 #if CONFIG_TASK_SIZE > CONFIG_KERNEL_START 94 #error User TASK_SIZE overlaps with KERNEL_START address 95 #endif 96 #define TASK_SIZE (CONFIG_TASK_SIZE) 97 98 /* This decides where the kernel will search for a free chunk of vm 99 * space during mmap's. 100 */ 101 #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) 102 #endif 103 104 #ifdef CONFIG_PPC64 105 /* 106 * 64-bit user address space can have multiple limits 107 * For now supported values are: 108 */ 109 #define TASK_SIZE_64TB (0x0000400000000000UL) 110 #define TASK_SIZE_128TB (0x0000800000000000UL) 111 #define TASK_SIZE_512TB (0x0002000000000000UL) 112 #define TASK_SIZE_1PB (0x0004000000000000UL) 113 #define TASK_SIZE_2PB (0x0008000000000000UL) 114 /* 115 * With 52 bits in the address we can support 116 * upto 4PB of range. 117 */ 118 #define TASK_SIZE_4PB (0x0010000000000000UL) 119 120 /* 121 * For now 512TB is only supported with book3s and 64K linux page size. 122 */ 123 #if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_PPC_64K_PAGES) 124 /* 125 * Max value currently used: 126 */ 127 #define TASK_SIZE_USER64 TASK_SIZE_4PB 128 #define DEFAULT_MAP_WINDOW_USER64 TASK_SIZE_128TB 129 #define TASK_CONTEXT_SIZE TASK_SIZE_512TB 130 #else 131 #define TASK_SIZE_USER64 TASK_SIZE_64TB 132 #define DEFAULT_MAP_WINDOW_USER64 TASK_SIZE_64TB 133 /* 134 * We don't need to allocate extended context ids for 4K page size, because 135 * we limit the max effective address on this config to 64TB. 136 */ 137 #define TASK_CONTEXT_SIZE TASK_SIZE_64TB 138 #endif 139 140 /* 141 * 32-bit user address space is 4GB - 1 page 142 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT 143 */ 144 #define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE)) 145 146 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ 147 TASK_SIZE_USER32 : TASK_SIZE_USER64) 148 #define TASK_SIZE TASK_SIZE_OF(current) 149 /* This decides where the kernel will search for a free chunk of vm 150 * space during mmap's. 151 */ 152 #define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4)) 153 #define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(DEFAULT_MAP_WINDOW_USER64 / 4)) 154 155 #define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \ 156 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 ) 157 #endif 158 159 /* 160 * Initial task size value for user applications. For book3s 64 we start 161 * with 128TB and conditionally enable upto 512TB 162 */ 163 #ifdef CONFIG_PPC_BOOK3S_64 164 #define DEFAULT_MAP_WINDOW ((is_32bit_task()) ? \ 165 TASK_SIZE_USER32 : DEFAULT_MAP_WINDOW_USER64) 166 #else 167 #define DEFAULT_MAP_WINDOW TASK_SIZE 168 #endif 169 170 #ifdef __powerpc64__ 171 172 #define STACK_TOP_USER64 DEFAULT_MAP_WINDOW_USER64 173 #define STACK_TOP_USER32 TASK_SIZE_USER32 174 175 #define STACK_TOP (is_32bit_task() ? \ 176 STACK_TOP_USER32 : STACK_TOP_USER64) 177 178 #define STACK_TOP_MAX TASK_SIZE_USER64 179 180 #else /* __powerpc64__ */ 181 182 #define STACK_TOP TASK_SIZE 183 #define STACK_TOP_MAX STACK_TOP 184 185 #endif /* __powerpc64__ */ 186 187 typedef struct { 188 unsigned long seg; 189 } mm_segment_t; 190 191 #define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET] 192 #define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET] 193 194 /* FP and VSX 0-31 register set */ 195 struct thread_fp_state { 196 u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16))); 197 u64 fpscr; /* Floating point status */ 198 }; 199 200 /* Complete AltiVec register set including VSCR */ 201 struct thread_vr_state { 202 vector128 vr[32] __attribute__((aligned(16))); 203 vector128 vscr __attribute__((aligned(16))); 204 }; 205 206 struct debug_reg { 207 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 208 /* 209 * The following help to manage the use of Debug Control Registers 210 * om the BookE platforms. 211 */ 212 uint32_t dbcr0; 213 uint32_t dbcr1; 214 #ifdef CONFIG_BOOKE 215 uint32_t dbcr2; 216 #endif 217 /* 218 * The stored value of the DBSR register will be the value at the 219 * last debug interrupt. This register can only be read from the 220 * user (will never be written to) and has value while helping to 221 * describe the reason for the last debug trap. Torez 222 */ 223 uint32_t dbsr; 224 /* 225 * The following will contain addresses used by debug applications 226 * to help trace and trap on particular address locations. 227 * The bits in the Debug Control Registers above help define which 228 * of the following registers will contain valid data and/or addresses. 229 */ 230 unsigned long iac1; 231 unsigned long iac2; 232 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 233 unsigned long iac3; 234 unsigned long iac4; 235 #endif 236 unsigned long dac1; 237 unsigned long dac2; 238 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 239 unsigned long dvc1; 240 unsigned long dvc2; 241 #endif 242 #endif 243 }; 244 245 struct thread_struct { 246 unsigned long ksp; /* Kernel stack pointer */ 247 248 #ifdef CONFIG_PPC64 249 unsigned long ksp_vsid; 250 #endif 251 struct pt_regs *regs; /* Pointer to saved register state */ 252 mm_segment_t addr_limit; /* for get_fs() validation */ 253 #ifdef CONFIG_BOOKE 254 /* BookE base exception scratch space; align on cacheline */ 255 unsigned long normsave[8] ____cacheline_aligned; 256 #endif 257 #ifdef CONFIG_PPC32 258 void *pgdir; /* root of page-table tree */ 259 unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */ 260 #endif 261 /* Debug Registers */ 262 struct debug_reg debug; 263 struct thread_fp_state fp_state; 264 struct thread_fp_state *fp_save_area; 265 int fpexc_mode; /* floating-point exception mode */ 266 unsigned int align_ctl; /* alignment handling control */ 267 #ifdef CONFIG_HAVE_HW_BREAKPOINT 268 struct perf_event *ptrace_bps[HBP_NUM]; 269 /* 270 * Helps identify source of single-step exception and subsequent 271 * hw-breakpoint enablement 272 */ 273 struct perf_event *last_hit_ubp; 274 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 275 struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */ 276 unsigned long trap_nr; /* last trap # on this thread */ 277 u8 load_fp; 278 #ifdef CONFIG_ALTIVEC 279 u8 load_vec; 280 struct thread_vr_state vr_state; 281 struct thread_vr_state *vr_save_area; 282 unsigned long vrsave; 283 int used_vr; /* set if process has used altivec */ 284 #endif /* CONFIG_ALTIVEC */ 285 #ifdef CONFIG_VSX 286 /* VSR status */ 287 int used_vsr; /* set if process has used VSX */ 288 #endif /* CONFIG_VSX */ 289 #ifdef CONFIG_SPE 290 unsigned long evr[32]; /* upper 32-bits of SPE regs */ 291 u64 acc; /* Accumulator */ 292 unsigned long spefscr; /* SPE & eFP status */ 293 unsigned long spefscr_last; /* SPEFSCR value on last prctl 294 call or trap return */ 295 int used_spe; /* set if process has used spe */ 296 #endif /* CONFIG_SPE */ 297 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 298 u8 load_tm; 299 u64 tm_tfhar; /* Transaction fail handler addr */ 300 u64 tm_texasr; /* Transaction exception & summary */ 301 u64 tm_tfiar; /* Transaction fail instr address reg */ 302 struct pt_regs ckpt_regs; /* Checkpointed registers */ 303 304 unsigned long tm_tar; 305 unsigned long tm_ppr; 306 unsigned long tm_dscr; 307 308 /* 309 * Checkpointed FP and VSX 0-31 register set. 310 * 311 * When a transaction is active/signalled/scheduled etc., *regs is the 312 * most recent set of/speculated GPRs with ckpt_regs being the older 313 * checkpointed regs to which we roll back if transaction aborts. 314 * 315 * These are analogous to how ckpt_regs and pt_regs work 316 */ 317 struct thread_fp_state ckfp_state; /* Checkpointed FP state */ 318 struct thread_vr_state ckvr_state; /* Checkpointed VR state */ 319 unsigned long ckvrsave; /* Checkpointed VRSAVE */ 320 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 321 #ifdef CONFIG_PPC_MEM_KEYS 322 unsigned long amr; 323 unsigned long iamr; 324 unsigned long uamor; 325 #endif 326 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 327 void* kvm_shadow_vcpu; /* KVM internal data */ 328 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */ 329 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE) 330 struct kvm_vcpu *kvm_vcpu; 331 #endif 332 #ifdef CONFIG_PPC64 333 unsigned long dscr; 334 unsigned long fscr; 335 /* 336 * This member element dscr_inherit indicates that the process 337 * has explicitly attempted and changed the DSCR register value 338 * for itself. Hence kernel wont use the default CPU DSCR value 339 * contained in the PACA structure anymore during process context 340 * switch. Once this variable is set, this behaviour will also be 341 * inherited to all the children of this process from that point 342 * onwards. 343 */ 344 int dscr_inherit; 345 unsigned long ppr; /* used to save/restore SMT priority */ 346 unsigned long tidr; 347 #endif 348 #ifdef CONFIG_PPC_BOOK3S_64 349 unsigned long tar; 350 unsigned long ebbrr; 351 unsigned long ebbhr; 352 unsigned long bescr; 353 unsigned long siar; 354 unsigned long sdar; 355 unsigned long sier; 356 unsigned long mmcr2; 357 unsigned mmcr0; 358 359 unsigned used_ebb; 360 unsigned int used_vas; 361 #endif 362 }; 363 364 #define ARCH_MIN_TASKALIGN 16 365 366 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) 367 #define INIT_SP_LIMIT \ 368 (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack) 369 370 #ifdef CONFIG_SPE 371 #define SPEFSCR_INIT \ 372 .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \ 373 .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, 374 #else 375 #define SPEFSCR_INIT 376 #endif 377 378 #ifdef CONFIG_PPC32 379 #define INIT_THREAD { \ 380 .ksp = INIT_SP, \ 381 .ksp_limit = INIT_SP_LIMIT, \ 382 .addr_limit = KERNEL_DS, \ 383 .pgdir = swapper_pg_dir, \ 384 .fpexc_mode = MSR_FE0 | MSR_FE1, \ 385 SPEFSCR_INIT \ 386 } 387 #else 388 #define INIT_THREAD { \ 389 .ksp = INIT_SP, \ 390 .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \ 391 .addr_limit = KERNEL_DS, \ 392 .fpexc_mode = 0, \ 393 .ppr = INIT_PPR, \ 394 .fscr = FSCR_TAR | FSCR_EBB \ 395 } 396 #endif 397 398 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs) 399 400 unsigned long get_wchan(struct task_struct *p); 401 402 #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) 403 #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0) 404 405 /* Get/set floating-point exception mode */ 406 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr)) 407 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val)) 408 409 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr); 410 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val); 411 412 #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr)) 413 #define SET_ENDIAN(tsk, val) set_endian((tsk), (val)) 414 415 extern int get_endian(struct task_struct *tsk, unsigned long adr); 416 extern int set_endian(struct task_struct *tsk, unsigned int val); 417 418 #define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr)) 419 #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) 420 421 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr); 422 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); 423 424 extern void load_fp_state(struct thread_fp_state *fp); 425 extern void store_fp_state(struct thread_fp_state *fp); 426 extern void load_vr_state(struct thread_vr_state *vr); 427 extern void store_vr_state(struct thread_vr_state *vr); 428 429 static inline unsigned int __unpack_fe01(unsigned long msr_bits) 430 { 431 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8); 432 } 433 434 static inline unsigned long __pack_fe01(unsigned int fpmode) 435 { 436 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1); 437 } 438 439 #ifdef CONFIG_PPC64 440 #define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0) 441 442 #define spin_begin() HMT_low() 443 444 #define spin_cpu_relax() barrier() 445 446 #define spin_cpu_yield() spin_cpu_relax() 447 448 #define spin_end() HMT_medium() 449 450 #define spin_until_cond(cond) \ 451 do { \ 452 if (unlikely(!(cond))) { \ 453 spin_begin(); \ 454 do { \ 455 spin_cpu_relax(); \ 456 } while (!(cond)); \ 457 spin_end(); \ 458 } \ 459 } while (0) 460 461 #else 462 #define cpu_relax() barrier() 463 #endif 464 465 /* Check that a certain kernel stack pointer is valid in task_struct p */ 466 int validate_sp(unsigned long sp, struct task_struct *p, 467 unsigned long nbytes); 468 469 /* 470 * Prefetch macros. 471 */ 472 #define ARCH_HAS_PREFETCH 473 #define ARCH_HAS_PREFETCHW 474 #define ARCH_HAS_SPINLOCK_PREFETCH 475 476 static inline void prefetch(const void *x) 477 { 478 if (unlikely(!x)) 479 return; 480 481 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x)); 482 } 483 484 static inline void prefetchw(const void *x) 485 { 486 if (unlikely(!x)) 487 return; 488 489 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x)); 490 } 491 492 #define spin_lock_prefetch(x) prefetchw(x) 493 494 #define HAVE_ARCH_PICK_MMAP_LAYOUT 495 496 #ifdef CONFIG_PPC64 497 static inline unsigned long get_clean_sp(unsigned long sp, int is_32) 498 { 499 if (is_32) 500 return sp & 0x0ffffffffUL; 501 return sp; 502 } 503 #else 504 static inline unsigned long get_clean_sp(unsigned long sp, int is_32) 505 { 506 return sp; 507 } 508 #endif 509 510 extern unsigned long cpuidle_disable; 511 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF}; 512 513 extern int powersave_nap; /* set if nap mode can be used in idle loop */ 514 extern unsigned long power7_idle_insn(unsigned long type); /* PNV_THREAD_NAP/etc*/ 515 extern void power7_idle_type(unsigned long type); 516 extern unsigned long power9_idle_stop(unsigned long psscr_val); 517 extern unsigned long power9_offline_stop(unsigned long psscr_val); 518 extern void power9_idle_type(unsigned long stop_psscr_val, 519 unsigned long stop_psscr_mask); 520 521 extern void flush_instruction_cache(void); 522 extern void hard_reset_now(void); 523 extern void poweroff_now(void); 524 extern int fix_alignment(struct pt_regs *); 525 extern void cvt_fd(float *from, double *to); 526 extern void cvt_df(double *from, float *to); 527 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); 528 529 #ifdef CONFIG_PPC64 530 /* 531 * We handle most unaligned accesses in hardware. On the other hand 532 * unaligned DMA can be very expensive on some ppc64 IO chips (it does 533 * powers of 2 writes until it reaches sufficient alignment). 534 * 535 * Based on this we disable the IP header alignment in network drivers. 536 */ 537 #define NET_IP_ALIGN 0 538 #endif 539 540 #endif /* __KERNEL__ */ 541 #endif /* __ASSEMBLY__ */ 542 #endif /* _ASM_POWERPC_PROCESSOR_H */ 543