1 #ifndef __ASM_POWERPC_PCI_H 2 #define __ASM_POWERPC_PCI_H 3 #ifdef __KERNEL__ 4 5 /* 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #include <linux/types.h> 13 #include <linux/slab.h> 14 #include <linux/string.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/scatterlist.h> 17 18 #include <asm/machdep.h> 19 #include <asm/io.h> 20 #include <asm/prom.h> 21 #include <asm/pci-bridge.h> 22 23 /* Return values for pci_controller_ops.probe_mode function */ 24 #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */ 25 #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */ 26 #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */ 27 28 #define PCIBIOS_MIN_IO 0x1000 29 #define PCIBIOS_MIN_MEM 0x10000000 30 31 struct pci_dev; 32 33 /* Values for the `which' argument to sys_pciconfig_iobase syscall. */ 34 #define IOBASE_BRIDGE_NUMBER 0 35 #define IOBASE_MEMORY 1 36 #define IOBASE_IO 2 37 #define IOBASE_ISA_IO 3 38 #define IOBASE_ISA_MEM 4 39 40 /* 41 * Set this to 1 if you want the kernel to re-assign all PCI 42 * bus numbers (don't do that on ppc64 yet !) 43 */ 44 #define pcibios_assign_all_busses() \ 45 (pci_has_flag(PCI_REASSIGN_ALL_BUS)) 46 47 #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ 48 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 49 { 50 if (ppc_md.pci_get_legacy_ide_irq) 51 return ppc_md.pci_get_legacy_ide_irq(dev, channel); 52 return channel ? 15 : 14; 53 } 54 55 #ifdef CONFIG_PCI 56 extern void set_pci_dma_ops(struct dma_map_ops *dma_ops); 57 extern struct dma_map_ops *get_pci_dma_ops(void); 58 #else /* CONFIG_PCI */ 59 #define set_pci_dma_ops(d) 60 #define get_pci_dma_ops() NULL 61 #endif 62 63 #ifdef CONFIG_PPC64 64 65 /* 66 * We want to avoid touching the cacheline size or MWI bit. 67 * pSeries firmware sets the cacheline size (which is not the cpu cacheline 68 * size in all cases) and hardware treats MWI the same as memory write. 69 */ 70 #define PCI_DISABLE_MWI 71 72 #endif /* CONFIG_PPC64 */ 73 74 extern int pci_domain_nr(struct pci_bus *bus); 75 76 /* Decide whether to display the domain number in /proc */ 77 extern int pci_proc_domain(struct pci_bus *bus); 78 79 struct vm_area_struct; 80 /* Map a range of PCI memory or I/O space for a device into user space */ 81 int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, 82 enum pci_mmap_state mmap_state, int write_combine); 83 84 /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */ 85 #define HAVE_PCI_MMAP 1 86 87 extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, 88 size_t count); 89 extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, 90 size_t count); 91 extern int pci_mmap_legacy_page_range(struct pci_bus *bus, 92 struct vm_area_struct *vma, 93 enum pci_mmap_state mmap_state); 94 95 #define HAVE_PCI_LEGACY 1 96 97 #ifdef CONFIG_PPC64 98 99 /* The PCI address space does not equal the physical memory address 100 * space (we have an IOMMU). The IDE and SCSI device layers use 101 * this boolean for bounce buffer decisions. 102 */ 103 #define PCI_DMA_BUS_IS_PHYS (0) 104 105 #else /* 32-bit */ 106 107 /* The PCI address space does equal the physical memory 108 * address space (no IOMMU). The IDE and SCSI device layers use 109 * this boolean for bounce buffer decisions. 110 */ 111 #define PCI_DMA_BUS_IS_PHYS (1) 112 113 #endif /* CONFIG_PPC64 */ 114 115 extern void pcibios_claim_one_bus(struct pci_bus *b); 116 117 extern void pcibios_finish_adding_to_bus(struct pci_bus *bus); 118 119 extern void pcibios_resource_survey(void); 120 121 extern struct pci_controller *init_phb_dynamic(struct device_node *dn); 122 extern int remove_phb_dynamic(struct pci_controller *phb); 123 124 extern struct pci_dev *of_create_pci_dev(struct device_node *node, 125 struct pci_bus *bus, int devfn); 126 127 extern void of_scan_pci_bridge(struct pci_dev *dev); 128 129 extern void of_scan_bus(struct device_node *node, struct pci_bus *bus); 130 extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus); 131 132 struct file; 133 extern pgprot_t pci_phys_mem_access_prot(struct file *file, 134 unsigned long pfn, 135 unsigned long size, 136 pgprot_t prot); 137 138 #define HAVE_ARCH_PCI_RESOURCE_TO_USER 139 extern void pci_resource_to_user(const struct pci_dev *dev, int bar, 140 const struct resource *rsrc, 141 resource_size_t *start, resource_size_t *end); 142 143 extern resource_size_t pcibios_io_space_offset(struct pci_controller *hose); 144 extern void pcibios_setup_bus_devices(struct pci_bus *bus); 145 extern void pcibios_setup_bus_self(struct pci_bus *bus); 146 extern void pcibios_setup_phb_io_space(struct pci_controller *hose); 147 extern void pcibios_scan_phb(struct pci_controller *hose); 148 149 #endif /* __KERNEL__ */ 150 151 extern struct pci_dev *pnv_pci_get_gpu_dev(struct pci_dev *npdev); 152 extern struct pci_dev *pnv_pci_get_npu_dev(struct pci_dev *gpdev, int index); 153 154 #endif /* __ASM_POWERPC_PCI_H */ 155