1 /* 2 * Common registers for PPC AES implementation 3 * 4 * Copyright (c) 2015 Markus Stockhausen <stockhausen@collogia.de> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the Free 8 * Software Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 * 11 */ 12 13 #define rKS r0 /* copy of en-/decryption key pointer */ 14 #define rDP r3 /* destination pointer */ 15 #define rSP r4 /* source pointer */ 16 #define rKP r5 /* pointer to en-/decryption key pointer */ 17 #define rRR r6 /* en-/decryption rounds */ 18 #define rLN r7 /* length of data to be processed */ 19 #define rIP r8 /* potiner to IV (CBC/CTR/XTS modes) */ 20 #define rKT r9 /* pointer to tweak key (XTS mode) */ 21 #define rT0 r11 /* pointers to en-/decryption tables */ 22 #define rT1 r10 23 #define rD0 r9 /* data */ 24 #define rD1 r14 25 #define rD2 r12 26 #define rD3 r15 27 #define rW0 r16 /* working registers */ 28 #define rW1 r17 29 #define rW2 r18 30 #define rW3 r19 31 #define rW4 r20 32 #define rW5 r21 33 #define rW6 r22 34 #define rW7 r23 35 #define rI0 r24 /* IV */ 36 #define rI1 r25 37 #define rI2 r26 38 #define rI3 r27 39 #define rG0 r28 /* endian reversed tweak (XTS mode) */ 40 #define rG1 r29 41 #define rG2 r30 42 #define rG3 r31 43