1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Unaligned memory access handler 4 * 5 * Copyright (C) 2001 Randolph Chung <tausq@debian.org> 6 * Copyright (C) 2022 Helge Deller <deller@gmx.de> 7 * Significantly tweaked by LaMont Jones <lamont@debian.org> 8 */ 9 10 #include <linux/sched/signal.h> 11 #include <linux/signal.h> 12 #include <linux/ratelimit.h> 13 #include <linux/uaccess.h> 14 #include <linux/sysctl.h> 15 #include <asm/unaligned.h> 16 #include <asm/hardirq.h> 17 #include <asm/traps.h> 18 19 /* #define DEBUG_UNALIGNED 1 */ 20 21 #ifdef DEBUG_UNALIGNED 22 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0) 23 #else 24 #define DPRINTF(fmt, args...) 25 #endif 26 27 #define RFMT "%#08lx" 28 29 /* 1111 1100 0000 0000 0001 0011 1100 0000 */ 30 #define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6) 31 #define OPCODE2(a,b) ((a)<<26|(b)<<1) 32 #define OPCODE3(a,b) ((a)<<26|(b)<<2) 33 #define OPCODE4(a) ((a)<<26) 34 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf) 35 #define OPCODE2_MASK OPCODE2(0x3f,1) 36 #define OPCODE3_MASK OPCODE3(0x3f,1) 37 #define OPCODE4_MASK OPCODE4(0x3f) 38 39 /* skip LDB - never unaligned (index) */ 40 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1) 41 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2) 42 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3) 43 #define OPCODE_LDDA_I OPCODE1(0x03,0,0x4) 44 #define OPCODE_LDCD_I OPCODE1(0x03,0,0x5) 45 #define OPCODE_LDWA_I OPCODE1(0x03,0,0x6) 46 #define OPCODE_LDCW_I OPCODE1(0x03,0,0x7) 47 /* skip LDB - never unaligned (short) */ 48 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1) 49 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2) 50 #define OPCODE_LDD_S OPCODE1(0x03,1,0x3) 51 #define OPCODE_LDDA_S OPCODE1(0x03,1,0x4) 52 #define OPCODE_LDCD_S OPCODE1(0x03,1,0x5) 53 #define OPCODE_LDWA_S OPCODE1(0x03,1,0x6) 54 #define OPCODE_LDCW_S OPCODE1(0x03,1,0x7) 55 /* skip STB - never unaligned */ 56 #define OPCODE_STH OPCODE1(0x03,1,0x9) 57 #define OPCODE_STW OPCODE1(0x03,1,0xa) 58 #define OPCODE_STD OPCODE1(0x03,1,0xb) 59 /* skip STBY - never unaligned */ 60 /* skip STDBY - never unaligned */ 61 #define OPCODE_STWA OPCODE1(0x03,1,0xe) 62 #define OPCODE_STDA OPCODE1(0x03,1,0xf) 63 64 #define OPCODE_FLDWX OPCODE1(0x09,0,0x0) 65 #define OPCODE_FLDWXR OPCODE1(0x09,0,0x1) 66 #define OPCODE_FSTWX OPCODE1(0x09,0,0x8) 67 #define OPCODE_FSTWXR OPCODE1(0x09,0,0x9) 68 #define OPCODE_FLDWS OPCODE1(0x09,1,0x0) 69 #define OPCODE_FLDWSR OPCODE1(0x09,1,0x1) 70 #define OPCODE_FSTWS OPCODE1(0x09,1,0x8) 71 #define OPCODE_FSTWSR OPCODE1(0x09,1,0x9) 72 #define OPCODE_FLDDX OPCODE1(0x0b,0,0x0) 73 #define OPCODE_FSTDX OPCODE1(0x0b,0,0x8) 74 #define OPCODE_FLDDS OPCODE1(0x0b,1,0x0) 75 #define OPCODE_FSTDS OPCODE1(0x0b,1,0x8) 76 77 #define OPCODE_LDD_L OPCODE2(0x14,0) 78 #define OPCODE_FLDD_L OPCODE2(0x14,1) 79 #define OPCODE_STD_L OPCODE2(0x1c,0) 80 #define OPCODE_FSTD_L OPCODE2(0x1c,1) 81 82 #define OPCODE_LDW_M OPCODE3(0x17,1) 83 #define OPCODE_FLDW_L OPCODE3(0x17,0) 84 #define OPCODE_FSTW_L OPCODE3(0x1f,0) 85 #define OPCODE_STW_M OPCODE3(0x1f,1) 86 87 #define OPCODE_LDH_L OPCODE4(0x11) 88 #define OPCODE_LDW_L OPCODE4(0x12) 89 #define OPCODE_LDWM OPCODE4(0x13) 90 #define OPCODE_STH_L OPCODE4(0x19) 91 #define OPCODE_STW_L OPCODE4(0x1A) 92 #define OPCODE_STWM OPCODE4(0x1B) 93 94 #define MAJOR_OP(i) (((i)>>26)&0x3f) 95 #define R1(i) (((i)>>21)&0x1f) 96 #define R2(i) (((i)>>16)&0x1f) 97 #define R3(i) ((i)&0x1f) 98 #define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1)) 99 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0)) 100 #define IM5_2(i) IM((i)>>16,5) 101 #define IM5_3(i) IM((i),5) 102 #define IM14(i) IM((i),14) 103 104 #define ERR_NOTHANDLED -1 105 106 int unaligned_enabled __read_mostly = 1; 107 108 static int emulate_ldh(struct pt_regs *regs, int toreg) 109 { 110 unsigned long saddr = regs->ior; 111 unsigned long val = 0, temp1; 112 ASM_EXCEPTIONTABLE_VAR(ret); 113 114 DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n", 115 regs->isr, regs->ior, toreg); 116 117 __asm__ __volatile__ ( 118 " mtsp %4, %%sr1\n" 119 "1: ldbs 0(%%sr1,%3), %2\n" 120 "2: ldbs 1(%%sr1,%3), %0\n" 121 " depw %2, 23, 24, %0\n" 122 "3: \n" 123 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b) 124 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b) 125 : "+r" (val), "+r" (ret), "=&r" (temp1) 126 : "r" (saddr), "r" (regs->isr) ); 127 128 DPRINTF("val = " RFMT "\n", val); 129 130 if (toreg) 131 regs->gr[toreg] = val; 132 133 return ret; 134 } 135 136 static int emulate_ldw(struct pt_regs *regs, int toreg, int flop) 137 { 138 unsigned long saddr = regs->ior; 139 unsigned long val = 0, temp1, temp2; 140 ASM_EXCEPTIONTABLE_VAR(ret); 141 142 DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n", 143 regs->isr, regs->ior, toreg); 144 145 __asm__ __volatile__ ( 146 " zdep %4,28,2,%2\n" /* r19=(ofs&3)*8 */ 147 " mtsp %5, %%sr1\n" 148 " depw %%r0,31,2,%4\n" 149 "1: ldw 0(%%sr1,%4),%0\n" 150 "2: ldw 4(%%sr1,%4),%3\n" 151 " subi 32,%2,%2\n" 152 " mtctl %2,11\n" 153 " vshd %0,%3,%0\n" 154 "3: \n" 155 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b) 156 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b) 157 : "+r" (val), "+r" (ret), "=&r" (temp1), "=&r" (temp2) 158 : "r" (saddr), "r" (regs->isr) ); 159 160 DPRINTF("val = " RFMT "\n", val); 161 162 if (flop) 163 ((__u32*)(regs->fr))[toreg] = val; 164 else if (toreg) 165 regs->gr[toreg] = val; 166 167 return ret; 168 } 169 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop) 170 { 171 unsigned long saddr = regs->ior; 172 __u64 val = 0; 173 ASM_EXCEPTIONTABLE_VAR(ret); 174 175 DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n", 176 regs->isr, regs->ior, toreg); 177 178 if (!IS_ENABLED(CONFIG_64BIT) && !flop) 179 return ERR_NOTHANDLED; 180 181 #ifdef CONFIG_64BIT 182 __asm__ __volatile__ ( 183 " depd,z %3,60,3,%%r19\n" /* r19=(ofs&7)*8 */ 184 " mtsp %4, %%sr1\n" 185 " depd %%r0,63,3,%3\n" 186 "1: ldd 0(%%sr1,%3),%0\n" 187 "2: ldd 8(%%sr1,%3),%%r20\n" 188 " subi 64,%%r19,%%r19\n" 189 " mtsar %%r19\n" 190 " shrpd %0,%%r20,%%sar,%0\n" 191 "3: \n" 192 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b) 193 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b) 194 : "=r" (val), "+r" (ret) 195 : "0" (val), "r" (saddr), "r" (regs->isr) 196 : "r19", "r20" ); 197 #else 198 { 199 unsigned long shift, temp1; 200 __asm__ __volatile__ ( 201 " zdep %2,29,2,%3\n" /* r19=(ofs&3)*8 */ 202 " mtsp %5, %%sr1\n" 203 " dep %%r0,31,2,%2\n" 204 "1: ldw 0(%%sr1,%2),%0\n" 205 "2: ldw 4(%%sr1,%2),%R0\n" 206 "3: ldw 8(%%sr1,%2),%4\n" 207 " subi 32,%3,%3\n" 208 " mtsar %3\n" 209 " vshd %0,%R0,%0\n" 210 " vshd %R0,%4,%R0\n" 211 "4: \n" 212 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b) 213 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b) 214 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b) 215 : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1) 216 : "r" (regs->isr) ); 217 } 218 #endif 219 220 DPRINTF("val = 0x%llx\n", val); 221 222 if (flop) 223 regs->fr[toreg] = val; 224 else if (toreg) 225 regs->gr[toreg] = val; 226 227 return ret; 228 } 229 230 static int emulate_sth(struct pt_regs *regs, int frreg) 231 { 232 unsigned long val = regs->gr[frreg], temp1; 233 ASM_EXCEPTIONTABLE_VAR(ret); 234 235 if (!frreg) 236 val = 0; 237 238 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg, 239 val, regs->isr, regs->ior); 240 241 __asm__ __volatile__ ( 242 " mtsp %4, %%sr1\n" 243 " extrw,u %2, 23, 8, %1\n" 244 "1: stb %1, 0(%%sr1, %3)\n" 245 "2: stb %2, 1(%%sr1, %3)\n" 246 "3: \n" 247 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b) 248 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b) 249 : "+r" (ret), "=&r" (temp1) 250 : "r" (val), "r" (regs->ior), "r" (regs->isr) ); 251 252 return ret; 253 } 254 255 static int emulate_stw(struct pt_regs *regs, int frreg, int flop) 256 { 257 unsigned long val; 258 ASM_EXCEPTIONTABLE_VAR(ret); 259 260 if (flop) 261 val = ((__u32*)(regs->fr))[frreg]; 262 else if (frreg) 263 val = regs->gr[frreg]; 264 else 265 val = 0; 266 267 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg, 268 val, regs->isr, regs->ior); 269 270 271 __asm__ __volatile__ ( 272 " mtsp %3, %%sr1\n" 273 " zdep %2, 28, 2, %%r19\n" 274 " dep %%r0, 31, 2, %2\n" 275 " mtsar %%r19\n" 276 " depwi,z -2, %%sar, 32, %%r19\n" 277 "1: ldw 0(%%sr1,%2),%%r20\n" 278 "2: ldw 4(%%sr1,%2),%%r21\n" 279 " vshd %%r0, %1, %%r22\n" 280 " vshd %1, %%r0, %%r1\n" 281 " and %%r20, %%r19, %%r20\n" 282 " andcm %%r21, %%r19, %%r21\n" 283 " or %%r22, %%r20, %%r20\n" 284 " or %%r1, %%r21, %%r21\n" 285 " stw %%r20,0(%%sr1,%2)\n" 286 " stw %%r21,4(%%sr1,%2)\n" 287 "3: \n" 288 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b) 289 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b) 290 : "+r" (ret) 291 : "r" (val), "r" (regs->ior), "r" (regs->isr) 292 : "r19", "r20", "r21", "r22", "r1" ); 293 294 return ret; 295 } 296 static int emulate_std(struct pt_regs *regs, int frreg, int flop) 297 { 298 __u64 val; 299 ASM_EXCEPTIONTABLE_VAR(ret); 300 301 if (flop) 302 val = regs->fr[frreg]; 303 else if (frreg) 304 val = regs->gr[frreg]; 305 else 306 val = 0; 307 308 DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg, 309 val, regs->isr, regs->ior); 310 311 if (!IS_ENABLED(CONFIG_64BIT) && !flop) 312 return ERR_NOTHANDLED; 313 314 #ifdef CONFIG_64BIT 315 __asm__ __volatile__ ( 316 " mtsp %3, %%sr1\n" 317 " depd,z %2, 60, 3, %%r19\n" 318 " depd %%r0, 63, 3, %2\n" 319 " mtsar %%r19\n" 320 " depdi,z -2, %%sar, 64, %%r19\n" 321 "1: ldd 0(%%sr1,%2),%%r20\n" 322 "2: ldd 8(%%sr1,%2),%%r21\n" 323 " shrpd %%r0, %1, %%sar, %%r22\n" 324 " shrpd %1, %%r0, %%sar, %%r1\n" 325 " and %%r20, %%r19, %%r20\n" 326 " andcm %%r21, %%r19, %%r21\n" 327 " or %%r22, %%r20, %%r20\n" 328 " or %%r1, %%r21, %%r21\n" 329 "3: std %%r20,0(%%sr1,%2)\n" 330 "4: std %%r21,8(%%sr1,%2)\n" 331 "5: \n" 332 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b) 333 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b) 334 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b) 335 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b) 336 : "+r" (ret) 337 : "r" (val), "r" (regs->ior), "r" (regs->isr) 338 : "r19", "r20", "r21", "r22", "r1" ); 339 #else 340 { 341 unsigned long valh = (val >> 32), vall = (val & 0xffffffffl); 342 __asm__ __volatile__ ( 343 " mtsp %4, %%sr1\n" 344 " zdep %2, 29, 2, %%r19\n" 345 " dep %%r0, 31, 2, %3\n" 346 " mtsar %%r19\n" 347 " zvdepi -2, 32, %%r19\n" 348 "1: ldw 0(%%sr1,%3),%%r20\n" 349 "2: ldw 8(%%sr1,%3),%%r21\n" 350 " vshd %1, %2, %%r1\n" 351 " vshd %%r0, %1, %1\n" 352 " vshd %2, %%r0, %2\n" 353 " and %%r20, %%r19, %%r20\n" 354 " andcm %%r21, %%r19, %%r21\n" 355 " or %1, %%r20, %1\n" 356 " or %2, %%r21, %2\n" 357 "3: stw %1,0(%%sr1,%3)\n" 358 "4: stw %%r1,4(%%sr1,%3)\n" 359 "5: stw %2,8(%%sr1,%3)\n" 360 "6: \n" 361 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b) 362 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b) 363 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b) 364 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b) 365 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b) 366 : "+r" (ret) 367 : "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr) 368 : "r19", "r20", "r21", "r1" ); 369 } 370 #endif 371 372 return ret; 373 } 374 375 void handle_unaligned(struct pt_regs *regs) 376 { 377 static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5); 378 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0; 379 int modify = 0; 380 int ret = ERR_NOTHANDLED; 381 382 __inc_irq_stat(irq_unaligned_count); 383 384 /* log a message with pacing */ 385 if (user_mode(regs)) { 386 if (current->thread.flags & PARISC_UAC_SIGBUS) { 387 goto force_sigbus; 388 } 389 390 if (!(current->thread.flags & PARISC_UAC_NOPRINT) && 391 __ratelimit(&ratelimit)) { 392 printk(KERN_WARNING "%s(%d): unaligned access to " RFMT 393 " at ip " RFMT " (iir " RFMT ")\n", 394 current->comm, task_pid_nr(current), regs->ior, 395 regs->iaoq[0], regs->iir); 396 #ifdef DEBUG_UNALIGNED 397 show_regs(regs); 398 #endif 399 } 400 401 if (!unaligned_enabled) 402 goto force_sigbus; 403 } 404 405 /* handle modification - OK, it's ugly, see the instruction manual */ 406 switch (MAJOR_OP(regs->iir)) 407 { 408 case 0x03: 409 case 0x09: 410 case 0x0b: 411 if (regs->iir&0x20) 412 { 413 modify = 1; 414 if (regs->iir&0x1000) /* short loads */ 415 if (regs->iir&0x200) 416 newbase += IM5_3(regs->iir); 417 else 418 newbase += IM5_2(regs->iir); 419 else if (regs->iir&0x2000) /* scaled indexed */ 420 { 421 int shift=0; 422 switch (regs->iir & OPCODE1_MASK) 423 { 424 case OPCODE_LDH_I: 425 shift= 1; break; 426 case OPCODE_LDW_I: 427 shift= 2; break; 428 case OPCODE_LDD_I: 429 case OPCODE_LDDA_I: 430 shift= 3; break; 431 } 432 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift; 433 } else /* simple indexed */ 434 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0); 435 } 436 break; 437 case 0x13: 438 case 0x1b: 439 modify = 1; 440 newbase += IM14(regs->iir); 441 break; 442 case 0x14: 443 case 0x1c: 444 if (regs->iir&8) 445 { 446 modify = 1; 447 newbase += IM14(regs->iir&~0xe); 448 } 449 break; 450 case 0x16: 451 case 0x1e: 452 modify = 1; 453 newbase += IM14(regs->iir&6); 454 break; 455 case 0x17: 456 case 0x1f: 457 if (regs->iir&4) 458 { 459 modify = 1; 460 newbase += IM14(regs->iir&~4); 461 } 462 break; 463 } 464 465 /* TODO: make this cleaner... */ 466 switch (regs->iir & OPCODE1_MASK) 467 { 468 case OPCODE_LDH_I: 469 case OPCODE_LDH_S: 470 ret = emulate_ldh(regs, R3(regs->iir)); 471 break; 472 473 case OPCODE_LDW_I: 474 case OPCODE_LDWA_I: 475 case OPCODE_LDW_S: 476 case OPCODE_LDWA_S: 477 ret = emulate_ldw(regs, R3(regs->iir), 0); 478 break; 479 480 case OPCODE_STH: 481 ret = emulate_sth(regs, R2(regs->iir)); 482 break; 483 484 case OPCODE_STW: 485 case OPCODE_STWA: 486 ret = emulate_stw(regs, R2(regs->iir), 0); 487 break; 488 489 #ifdef CONFIG_64BIT 490 case OPCODE_LDD_I: 491 case OPCODE_LDDA_I: 492 case OPCODE_LDD_S: 493 case OPCODE_LDDA_S: 494 ret = emulate_ldd(regs, R3(regs->iir), 0); 495 break; 496 497 case OPCODE_STD: 498 case OPCODE_STDA: 499 ret = emulate_std(regs, R2(regs->iir), 0); 500 break; 501 #endif 502 503 case OPCODE_FLDWX: 504 case OPCODE_FLDWS: 505 case OPCODE_FLDWXR: 506 case OPCODE_FLDWSR: 507 ret = emulate_ldw(regs, FR3(regs->iir), 1); 508 break; 509 510 case OPCODE_FLDDX: 511 case OPCODE_FLDDS: 512 ret = emulate_ldd(regs, R3(regs->iir), 1); 513 break; 514 515 case OPCODE_FSTWX: 516 case OPCODE_FSTWS: 517 case OPCODE_FSTWXR: 518 case OPCODE_FSTWSR: 519 ret = emulate_stw(regs, FR3(regs->iir), 1); 520 break; 521 522 case OPCODE_FSTDX: 523 case OPCODE_FSTDS: 524 ret = emulate_std(regs, R3(regs->iir), 1); 525 break; 526 527 case OPCODE_LDCD_I: 528 case OPCODE_LDCW_I: 529 case OPCODE_LDCD_S: 530 case OPCODE_LDCW_S: 531 ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */ 532 break; 533 } 534 switch (regs->iir & OPCODE2_MASK) 535 { 536 case OPCODE_FLDD_L: 537 ret = emulate_ldd(regs,R2(regs->iir),1); 538 break; 539 case OPCODE_FSTD_L: 540 ret = emulate_std(regs, R2(regs->iir),1); 541 break; 542 #ifdef CONFIG_64BIT 543 case OPCODE_LDD_L: 544 ret = emulate_ldd(regs, R2(regs->iir),0); 545 break; 546 case OPCODE_STD_L: 547 ret = emulate_std(regs, R2(regs->iir),0); 548 break; 549 #endif 550 } 551 switch (regs->iir & OPCODE3_MASK) 552 { 553 case OPCODE_FLDW_L: 554 ret = emulate_ldw(regs, R2(regs->iir), 1); 555 break; 556 case OPCODE_LDW_M: 557 ret = emulate_ldw(regs, R2(regs->iir), 0); 558 break; 559 560 case OPCODE_FSTW_L: 561 ret = emulate_stw(regs, R2(regs->iir),1); 562 break; 563 case OPCODE_STW_M: 564 ret = emulate_stw(regs, R2(regs->iir),0); 565 break; 566 } 567 switch (regs->iir & OPCODE4_MASK) 568 { 569 case OPCODE_LDH_L: 570 ret = emulate_ldh(regs, R2(regs->iir)); 571 break; 572 case OPCODE_LDW_L: 573 case OPCODE_LDWM: 574 ret = emulate_ldw(regs, R2(regs->iir),0); 575 break; 576 case OPCODE_STH_L: 577 ret = emulate_sth(regs, R2(regs->iir)); 578 break; 579 case OPCODE_STW_L: 580 case OPCODE_STWM: 581 ret = emulate_stw(regs, R2(regs->iir),0); 582 break; 583 } 584 585 if (ret == 0 && modify && R1(regs->iir)) 586 regs->gr[R1(regs->iir)] = newbase; 587 588 589 if (ret == ERR_NOTHANDLED) 590 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir); 591 592 DPRINTF("ret = %d\n", ret); 593 594 if (ret) 595 { 596 /* 597 * The unaligned handler failed. 598 * If we were called by __get_user() or __put_user() jump 599 * to it's exception fixup handler instead of crashing. 600 */ 601 if (!user_mode(regs) && fixup_exception(regs)) 602 return; 603 604 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret); 605 die_if_kernel("Unaligned data reference", regs, 28); 606 607 if (ret == -EFAULT) 608 { 609 force_sig_fault(SIGSEGV, SEGV_MAPERR, 610 (void __user *)regs->ior); 611 } 612 else 613 { 614 force_sigbus: 615 /* couldn't handle it ... */ 616 force_sig_fault(SIGBUS, BUS_ADRALN, 617 (void __user *)regs->ior); 618 } 619 620 return; 621 } 622 623 /* else we handled it, let life go on. */ 624 regs->gr[0]|=PSW_N; 625 } 626 627 /* 628 * NB: check_unaligned() is only used for PCXS processors right 629 * now, so we only check for PA1.1 encodings at this point. 630 */ 631 632 int 633 check_unaligned(struct pt_regs *regs) 634 { 635 unsigned long align_mask; 636 637 /* Get alignment mask */ 638 639 align_mask = 0UL; 640 switch (regs->iir & OPCODE1_MASK) { 641 642 case OPCODE_LDH_I: 643 case OPCODE_LDH_S: 644 case OPCODE_STH: 645 align_mask = 1UL; 646 break; 647 648 case OPCODE_LDW_I: 649 case OPCODE_LDWA_I: 650 case OPCODE_LDW_S: 651 case OPCODE_LDWA_S: 652 case OPCODE_STW: 653 case OPCODE_STWA: 654 align_mask = 3UL; 655 break; 656 657 default: 658 switch (regs->iir & OPCODE4_MASK) { 659 case OPCODE_LDH_L: 660 case OPCODE_STH_L: 661 align_mask = 1UL; 662 break; 663 case OPCODE_LDW_L: 664 case OPCODE_LDWM: 665 case OPCODE_STW_L: 666 case OPCODE_STWM: 667 align_mask = 3UL; 668 break; 669 } 670 break; 671 } 672 673 return (int)(regs->ior & align_mask); 674 } 675 676