1 #ifndef _PARISC_PGTABLE_H 2 #define _PARISC_PGTABLE_H 3 4 #include <asm-generic/4level-fixup.h> 5 6 #include <asm/fixmap.h> 7 8 #ifndef __ASSEMBLY__ 9 /* 10 * we simulate an x86-style page table for the linux mm code 11 */ 12 13 #include <linux/bitops.h> 14 #include <linux/spinlock.h> 15 #include <asm/processor.h> 16 #include <asm/cache.h> 17 18 struct vm_area_struct; 19 20 /* 21 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel 22 * memory. For the return value to be meaningful, ADDR must be >= 23 * PAGE_OFFSET. This operation can be relatively expensive (e.g., 24 * require a hash-, or multi-level tree-lookup or something of that 25 * sort) but it guarantees to return TRUE only if accessing the page 26 * at that address does not cause an error. Note that there may be 27 * addresses for which kern_addr_valid() returns FALSE even though an 28 * access would not cause an error (e.g., this is typically true for 29 * memory mapped I/O regions. 30 * 31 * XXX Need to implement this for parisc. 32 */ 33 #define kern_addr_valid(addr) (1) 34 35 /* Certain architectures need to do special things when PTEs 36 * within a page table are directly modified. Thus, the following 37 * hook is made available. 38 */ 39 #define set_pte(pteptr, pteval) \ 40 do{ \ 41 *(pteptr) = (pteval); \ 42 } while(0) 43 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 44 45 #endif /* !__ASSEMBLY__ */ 46 47 #define pte_ERROR(e) \ 48 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 49 #define pmd_ERROR(e) \ 50 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e)) 51 #define pgd_ERROR(e) \ 52 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e)) 53 54 /* This is the size of the initially mapped kernel memory */ 55 #define KERNEL_INITIAL_ORDER 24 /* 0 to 1<<24 = 16MB */ 56 #define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER) 57 58 #if defined(CONFIG_64BIT) && defined(CONFIG_PARISC_PAGE_SIZE_4KB) 59 #define PT_NLEVELS 3 60 #define PGD_ORDER 1 /* Number of pages per pgd */ 61 #define PMD_ORDER 1 /* Number of pages per pmd */ 62 #define PGD_ALLOC_ORDER 2 /* first pgd contains pmd */ 63 #else 64 #define PT_NLEVELS 2 65 #define PGD_ORDER 1 /* Number of pages per pgd */ 66 #define PGD_ALLOC_ORDER PGD_ORDER 67 #endif 68 69 /* Definitions for 3rd level (we use PLD here for Page Lower directory 70 * because PTE_SHIFT is used lower down to mean shift that has to be 71 * done to get usable bits out of the PTE) */ 72 #define PLD_SHIFT PAGE_SHIFT 73 #define PLD_SIZE PAGE_SIZE 74 #define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY) 75 #define PTRS_PER_PTE (1UL << BITS_PER_PTE) 76 77 /* Definitions for 2nd level */ 78 #define pgtable_cache_init() do { } while (0) 79 80 #define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE) 81 #define PMD_SIZE (1UL << PMD_SHIFT) 82 #define PMD_MASK (~(PMD_SIZE-1)) 83 #if PT_NLEVELS == 3 84 #define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY) 85 #else 86 #define BITS_PER_PMD 0 87 #endif 88 #define PTRS_PER_PMD (1UL << BITS_PER_PMD) 89 90 /* Definitions for 1st level */ 91 #define PGDIR_SHIFT (PMD_SHIFT + BITS_PER_PMD) 92 #if (PGDIR_SHIFT + PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG 93 #define BITS_PER_PGD (BITS_PER_LONG - PGDIR_SHIFT) 94 #else 95 #define BITS_PER_PGD (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) 96 #endif 97 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 98 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 99 #define PTRS_PER_PGD (1UL << BITS_PER_PGD) 100 #define USER_PTRS_PER_PGD PTRS_PER_PGD 101 102 #ifdef CONFIG_64BIT 103 #define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD) 104 #define MAX_ADDRESS (1UL << MAX_ADDRBITS) 105 #define SPACEID_SHIFT (MAX_ADDRBITS - 32) 106 #else 107 #define MAX_ADDRBITS (BITS_PER_LONG) 108 #define MAX_ADDRESS (1UL << MAX_ADDRBITS) 109 #define SPACEID_SHIFT 0 110 #endif 111 112 /* This calculates the number of initial pages we need for the initial 113 * page tables */ 114 #if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT) 115 # define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT)) 116 #else 117 # define PT_INITIAL (1) /* all initial PTEs fit into one page */ 118 #endif 119 120 /* 121 * pgd entries used up by user/kernel: 122 */ 123 124 #define FIRST_USER_ADDRESS 0 125 126 /* NB: The tlb miss handlers make certain assumptions about the order */ 127 /* of the following bits, so be careful (One example, bits 25-31 */ 128 /* are moved together in one instruction). */ 129 130 #define _PAGE_READ_BIT 31 /* (0x001) read access allowed */ 131 #define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */ 132 #define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */ 133 #define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */ 134 #define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */ 135 #define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */ 136 #define _PAGE_FILE_BIT _PAGE_DIRTY_BIT /* overload this bit */ 137 #define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */ 138 #define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */ 139 #define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */ 140 #define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */ 141 /* bit 21 was formerly the FLUSH bit but is now unused */ 142 #define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */ 143 144 /* N.B. The bits are defined in terms of a 32 bit word above, so the */ 145 /* following macro is ok for both 32 and 64 bit. */ 146 147 #define xlate_pabit(x) (31 - x) 148 149 /* this defines the shift to the usable bits in the PTE it is set so 150 * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set 151 * to zero */ 152 #define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT) 153 154 /* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */ 155 #define PFN_PTE_SHIFT 12 156 157 158 /* this is how many bits may be used by the file functions */ 159 #define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_SHIFT) 160 161 #define pte_to_pgoff(pte) (pte_val(pte) >> PTE_SHIFT) 162 #define pgoff_to_pte(off) ((pte_t) { ((off) << PTE_SHIFT) | _PAGE_FILE }) 163 164 #define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT)) 165 #define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT)) 166 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 167 #define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT)) 168 #define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT)) 169 #define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT)) 170 #define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT)) 171 #define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT)) 172 #define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT)) 173 #define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT)) 174 #define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT)) 175 #define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT)) 176 #define _PAGE_FILE (1 << xlate_pabit(_PAGE_FILE_BIT)) 177 178 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED) 179 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 180 #define _PAGE_KERNEL (_PAGE_PRESENT | _PAGE_EXEC | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED) 181 182 /* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds 183 * are page-aligned, we don't care about the PAGE_OFFSET bits, except 184 * for a few meta-information bits, so we shift the address to be 185 * able to effectively address 40/42/44-bits of physical address space 186 * depending on 4k/16k/64k PAGE_SIZE */ 187 #define _PxD_PRESENT_BIT 31 188 #define _PxD_ATTACHED_BIT 30 189 #define _PxD_VALID_BIT 29 190 191 #define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT)) 192 #define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT)) 193 #define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT)) 194 #define PxD_FLAG_MASK (0xf) 195 #define PxD_FLAG_SHIFT (4) 196 #define PxD_VALUE_SHIFT (8) /* (PAGE_SHIFT-PxD_FLAG_SHIFT) */ 197 198 #ifndef __ASSEMBLY__ 199 200 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED) 201 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_ACCESSED) 202 /* Others seem to make this executable, I don't know if that's correct 203 or not. The stack is mapped this way though so this is necessary 204 in the short term - dhd@linuxcare.com, 2000-08-08 */ 205 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_ACCESSED) 206 #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE | _PAGE_ACCESSED) 207 #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC |_PAGE_ACCESSED) 208 #define PAGE_COPY PAGE_EXECREAD 209 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC |_PAGE_ACCESSED) 210 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 211 #define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) 212 #define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE) 213 #define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_GATEWAY| _PAGE_READ) 214 215 216 /* 217 * We could have an execute only page using "gateway - promote to priv 218 * level 3", but that is kind of silly. So, the way things are defined 219 * now, we must always have read permission for pages with execute 220 * permission. For the fun of it we'll go ahead and support write only 221 * pages. 222 */ 223 224 /*xwr*/ 225 #define __P000 PAGE_NONE 226 #define __P001 PAGE_READONLY 227 #define __P010 __P000 /* copy on write */ 228 #define __P011 __P001 /* copy on write */ 229 #define __P100 PAGE_EXECREAD 230 #define __P101 PAGE_EXECREAD 231 #define __P110 __P100 /* copy on write */ 232 #define __P111 __P101 /* copy on write */ 233 234 #define __S000 PAGE_NONE 235 #define __S001 PAGE_READONLY 236 #define __S010 PAGE_WRITEONLY 237 #define __S011 PAGE_SHARED 238 #define __S100 PAGE_EXECREAD 239 #define __S101 PAGE_EXECREAD 240 #define __S110 PAGE_RWX 241 #define __S111 PAGE_RWX 242 243 244 extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */ 245 246 /* initial page tables for 0-8MB for kernel */ 247 248 extern pte_t pg0[]; 249 250 /* zero page used for uninitialized stuff */ 251 252 extern unsigned long *empty_zero_page; 253 254 /* 255 * ZERO_PAGE is a global shared page that is always zero: used 256 * for zero-mapped memory areas etc.. 257 */ 258 259 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 260 261 #define pte_none(x) (pte_val(x) == 0) 262 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT) 263 #define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0) 264 265 #define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK) 266 #define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT) 267 #define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK) 268 #define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT) 269 270 #if PT_NLEVELS == 3 271 /* The first entry of the permanent pmd is not there if it contains 272 * the gateway marker */ 273 #define pmd_none(x) (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED) 274 #else 275 #define pmd_none(x) (!pmd_val(x)) 276 #endif 277 #define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID)) 278 #define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT) 279 static inline void pmd_clear(pmd_t *pmd) { 280 #if PT_NLEVELS == 3 281 if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED) 282 /* This is the entry pointing to the permanent pmd 283 * attached to the pgd; cannot clear it */ 284 __pmd_val_set(*pmd, PxD_FLAG_ATTACHED); 285 else 286 #endif 287 __pmd_val_set(*pmd, 0); 288 } 289 290 291 292 #if PT_NLEVELS == 3 293 #define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_address(pgd))) 294 #define pgd_page(pgd) virt_to_page((void *)pgd_page_vaddr(pgd)) 295 296 /* For 64 bit we have three level tables */ 297 298 #define pgd_none(x) (!pgd_val(x)) 299 #define pgd_bad(x) (!(pgd_flag(x) & PxD_FLAG_VALID)) 300 #define pgd_present(x) (pgd_flag(x) & PxD_FLAG_PRESENT) 301 static inline void pgd_clear(pgd_t *pgd) { 302 #if PT_NLEVELS == 3 303 if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED) 304 /* This is the permanent pmd attached to the pgd; cannot 305 * free it */ 306 return; 307 #endif 308 __pgd_val_set(*pgd, 0); 309 } 310 #else 311 /* 312 * The "pgd_xxx()" functions here are trivial for a folded two-level 313 * setup: the pgd is never bad, and a pmd always exists (as it's folded 314 * into the pgd entry) 315 */ 316 static inline int pgd_none(pgd_t pgd) { return 0; } 317 static inline int pgd_bad(pgd_t pgd) { return 0; } 318 static inline int pgd_present(pgd_t pgd) { return 1; } 319 static inline void pgd_clear(pgd_t * pgdp) { } 320 #endif 321 322 /* 323 * The following only work if pte_present() is true. 324 * Undefined behaviour if not.. 325 */ 326 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 327 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 328 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } 329 static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } 330 static inline int pte_special(pte_t pte) { return 0; } 331 332 static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } 333 static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } 334 static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; } 335 static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; } 336 static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; } 337 static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; } 338 static inline pte_t pte_mkspecial(pte_t pte) { return pte; } 339 340 /* 341 * Conversion functions: convert a page and protection to a page entry, 342 * and a page entry and page directory to the page they refer to. 343 */ 344 #define __mk_pte(addr,pgprot) \ 345 ({ \ 346 pte_t __pte; \ 347 \ 348 pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \ 349 \ 350 __pte; \ 351 }) 352 353 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 354 355 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 356 { 357 pte_t pte; 358 pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot); 359 return pte; 360 } 361 362 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 363 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } 364 365 /* Permanent address of a page. On parisc we don't have highmem. */ 366 367 #define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT) 368 369 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 370 371 #define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_address(pmd))) 372 373 #define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd))) 374 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 375 376 #define pgd_index(address) ((address) >> PGDIR_SHIFT) 377 378 /* to find an entry in a page-table-directory */ 379 #define pgd_offset(mm, address) \ 380 ((mm)->pgd + ((address) >> PGDIR_SHIFT)) 381 382 /* to find an entry in a kernel page-table-directory */ 383 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 384 385 /* Find an entry in the second-level page table.. */ 386 387 #if PT_NLEVELS == 3 388 #define pmd_offset(dir,address) \ 389 ((pmd_t *) pgd_page_vaddr(*(dir)) + (((address)>>PMD_SHIFT) & (PTRS_PER_PMD-1))) 390 #else 391 #define pmd_offset(dir,addr) ((pmd_t *) dir) 392 #endif 393 394 /* Find an entry in the third-level page table.. */ 395 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) 396 #define pte_offset_kernel(pmd, address) \ 397 ((pte_t *) pmd_page_vaddr(*(pmd)) + pte_index(address)) 398 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) 399 #define pte_unmap(pte) do { } while (0) 400 401 #define pte_unmap(pte) do { } while (0) 402 #define pte_unmap_nested(pte) do { } while (0) 403 404 extern void paging_init (void); 405 406 /* Used for deferring calls to flush_dcache_page() */ 407 408 #define PG_dcache_dirty PG_arch_1 409 410 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); 411 412 /* Encode and de-code a swap entry */ 413 414 #define __swp_type(x) ((x).val & 0x1f) 415 #define __swp_offset(x) ( (((x).val >> 6) & 0x7) | \ 416 (((x).val >> 8) & ~0x7) ) 417 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | \ 418 ((offset & 0x7) << 6) | \ 419 ((offset & ~0x7) << 8) }) 420 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 421 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 422 423 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) 424 { 425 #ifdef CONFIG_SMP 426 if (!pte_young(*ptep)) 427 return 0; 428 return test_and_clear_bit(xlate_pabit(_PAGE_ACCESSED_BIT), &pte_val(*ptep)); 429 #else 430 pte_t pte = *ptep; 431 if (!pte_young(pte)) 432 return 0; 433 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte)); 434 return 1; 435 #endif 436 } 437 438 extern spinlock_t pa_dbit_lock; 439 440 struct mm_struct; 441 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 442 { 443 pte_t old_pte; 444 445 spin_lock(&pa_dbit_lock); 446 old_pte = *ptep; 447 pte_clear(mm,addr,ptep); 448 spin_unlock(&pa_dbit_lock); 449 450 return old_pte; 451 } 452 453 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 454 { 455 #ifdef CONFIG_SMP 456 unsigned long new, old; 457 458 do { 459 old = pte_val(*ptep); 460 new = pte_val(pte_wrprotect(__pte (old))); 461 } while (cmpxchg((unsigned long *) ptep, old, new) != old); 462 #else 463 pte_t old_pte = *ptep; 464 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte)); 465 #endif 466 } 467 468 #define pte_same(A,B) (pte_val(A) == pte_val(B)) 469 470 #endif /* !__ASSEMBLY__ */ 471 472 473 /* TLB page size encoding - see table 3-1 in parisc20.pdf */ 474 #define _PAGE_SIZE_ENCODING_4K 0 475 #define _PAGE_SIZE_ENCODING_16K 1 476 #define _PAGE_SIZE_ENCODING_64K 2 477 #define _PAGE_SIZE_ENCODING_256K 3 478 #define _PAGE_SIZE_ENCODING_1M 4 479 #define _PAGE_SIZE_ENCODING_4M 5 480 #define _PAGE_SIZE_ENCODING_16M 6 481 #define _PAGE_SIZE_ENCODING_64M 7 482 483 #if defined(CONFIG_PARISC_PAGE_SIZE_4KB) 484 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K 485 #elif defined(CONFIG_PARISC_PAGE_SIZE_16KB) 486 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K 487 #elif defined(CONFIG_PARISC_PAGE_SIZE_64KB) 488 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K 489 #endif 490 491 492 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ 493 remap_pfn_range(vma, vaddr, pfn, size, prot) 494 495 #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE) 496 497 /* We provide our own get_unmapped_area to provide cache coherency */ 498 499 #define HAVE_ARCH_UNMAPPED_AREA 500 501 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 502 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 503 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 504 #define __HAVE_ARCH_PTE_SAME 505 #include <asm-generic/pgtable.h> 506 507 #endif /* _PARISC_PGTABLE_H */ 508