1 /* 2 * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc. 3 * All rights reserved. 4 * Authors: Carsten Langgaard <carstenl@mips.com> 5 * Maciej W. Rozycki <macro@mips.com> 6 * 7 * Copyright (C) 2009 Lemote Inc. 8 * Author: Wu Zhangjin <wuzhangjin@gmail.com> 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/types.h> 15 #include <linux/pci.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/export.h> 19 20 #include <loongson.h> 21 22 #ifdef CONFIG_CS5536 23 #include <cs5536/cs5536_pci.h> 24 #include <cs5536/cs5536.h> 25 #endif 26 27 #define PCI_ACCESS_READ 0 28 #define PCI_ACCESS_WRITE 1 29 30 #define CFG_SPACE_REG(offset) \ 31 (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset)) 32 #define ID_SEL_BEGIN 11 33 #define MAX_DEV_NUM (31 - ID_SEL_BEGIN) 34 35 36 static int loongson_pcibios_config_access(unsigned char access_type, 37 struct pci_bus *bus, 38 unsigned int devfn, int where, 39 u32 *data) 40 { 41 u32 busnum = bus->number; 42 u32 addr, type; 43 u32 dummy; 44 void *addrp; 45 int device = PCI_SLOT(devfn); 46 int function = PCI_FUNC(devfn); 47 int reg = where & ~3; 48 49 if (busnum == 0) { 50 /* board-specific part,currently,only fuloong2f,yeeloong2f 51 * use CS5536, fuloong2e use via686b, gdium has no 52 * south bridge 53 */ 54 #ifdef CONFIG_CS5536 55 /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to 56 * access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO, 57 * PCI_MSR_DATA_HI, which is bigger than PCI_MSR_CTRL, so, it 58 * will not go this branch, but the others. so, no calling dead 59 * loop here. 60 */ 61 if ((PCI_IDSEL_CS5536 == device) && (reg < PCI_MSR_CTRL)) { 62 switch (access_type) { 63 case PCI_ACCESS_READ: 64 *data = cs5536_pci_conf_read4(function, reg); 65 break; 66 case PCI_ACCESS_WRITE: 67 cs5536_pci_conf_write4(function, reg, *data); 68 break; 69 } 70 return 0; 71 } 72 #endif 73 /* Type 0 configuration for onboard PCI bus */ 74 if (device > MAX_DEV_NUM) 75 return -1; 76 77 addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg; 78 type = 0; 79 } else { 80 /* Type 1 configuration for offboard PCI bus */ 81 addr = (busnum << 16) | (device << 11) | (function << 8) | reg; 82 type = 0x10000; 83 } 84 85 /* Clear aborts */ 86 LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \ 87 LOONGSON_PCICMD_MTABORT_CLR; 88 89 LOONGSON_PCIMAP_CFG = (addr >> 16) | type; 90 91 /* Flush Bonito register block */ 92 dummy = LOONGSON_PCIMAP_CFG; 93 mmiowb(); 94 95 addrp = CFG_SPACE_REG(addr & 0xffff); 96 if (access_type == PCI_ACCESS_WRITE) 97 writel(cpu_to_le32(*data), addrp); 98 else 99 *data = le32_to_cpu(readl(addrp)); 100 101 /* Detect Master/Target abort */ 102 if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR | 103 LOONGSON_PCICMD_MTABORT_CLR)) { 104 /* Error occurred */ 105 106 /* Clear bits */ 107 LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR | 108 LOONGSON_PCICMD_MTABORT_CLR); 109 110 return -1; 111 } 112 113 return 0; 114 115 } 116 117 118 /* 119 * We can't address 8 and 16 bit words directly. Instead we have to 120 * read/write a 32bit word and mask/modify the data we actually want. 121 */ 122 static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn, 123 int where, int size, u32 *val) 124 { 125 u32 data = 0; 126 127 if ((size == 2) && (where & 1)) 128 return PCIBIOS_BAD_REGISTER_NUMBER; 129 else if ((size == 4) && (where & 3)) 130 return PCIBIOS_BAD_REGISTER_NUMBER; 131 132 if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, 133 &data)) 134 return -1; 135 136 if (size == 1) 137 *val = (data >> ((where & 3) << 3)) & 0xff; 138 else if (size == 2) 139 *val = (data >> ((where & 3) << 3)) & 0xffff; 140 else 141 *val = data; 142 143 return PCIBIOS_SUCCESSFUL; 144 } 145 146 static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn, 147 int where, int size, u32 val) 148 { 149 u32 data = 0; 150 151 if ((size == 2) && (where & 1)) 152 return PCIBIOS_BAD_REGISTER_NUMBER; 153 else if ((size == 4) && (where & 3)) 154 return PCIBIOS_BAD_REGISTER_NUMBER; 155 156 if (size == 4) 157 data = val; 158 else { 159 if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, 160 where, &data)) 161 return -1; 162 163 if (size == 1) 164 data = (data & ~(0xff << ((where & 3) << 3))) | 165 (val << ((where & 3) << 3)); 166 else if (size == 2) 167 data = (data & ~(0xffff << ((where & 3) << 3))) | 168 (val << ((where & 3) << 3)); 169 } 170 171 if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, 172 &data)) 173 return -1; 174 175 return PCIBIOS_SUCCESSFUL; 176 } 177 178 struct pci_ops loongson_pci_ops = { 179 .read = loongson_pcibios_read, 180 .write = loongson_pcibios_write 181 }; 182 183 #ifdef CONFIG_CS5536 184 DEFINE_RAW_SPINLOCK(msr_lock); 185 186 void _rdmsr(u32 msr, u32 *hi, u32 *lo) 187 { 188 struct pci_bus bus = { 189 .number = PCI_BUS_CS5536 190 }; 191 u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0); 192 unsigned long flags; 193 194 raw_spin_lock_irqsave(&msr_lock, flags); 195 loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr); 196 loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_LO, 4, lo); 197 loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_HI, 4, hi); 198 raw_spin_unlock_irqrestore(&msr_lock, flags); 199 } 200 EXPORT_SYMBOL(_rdmsr); 201 202 void _wrmsr(u32 msr, u32 hi, u32 lo) 203 { 204 struct pci_bus bus = { 205 .number = PCI_BUS_CS5536 206 }; 207 u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0); 208 unsigned long flags; 209 210 raw_spin_lock_irqsave(&msr_lock, flags); 211 loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr); 212 loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_LO, 4, lo); 213 loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_HI, 4, hi); 214 raw_spin_unlock_irqrestore(&msr_lock, flags); 215 } 216 EXPORT_SYMBOL(_wrmsr); 217 #endif 218