1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * A small micro-assembler. It is intentionally kept simple, does only 7 * support a subset of instructions, and does not try to hide pipeline 8 * effects like branch delay slots. 9 * 10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 11 * Copyright (C) 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/types.h> 17 #include <linux/init.h> 18 19 #include <asm/inst.h> 20 #include <asm/elf.h> 21 #include <asm/bugs.h> 22 #include <asm/uasm.h> 23 24 enum fields { 25 RS = 0x001, 26 RT = 0x002, 27 RD = 0x004, 28 RE = 0x008, 29 SIMM = 0x010, 30 UIMM = 0x020, 31 BIMM = 0x040, 32 JIMM = 0x080, 33 FUNC = 0x100, 34 SET = 0x200, 35 SCIMM = 0x400 36 }; 37 38 #define OP_MASK 0x3f 39 #define OP_SH 26 40 #define RS_MASK 0x1f 41 #define RS_SH 21 42 #define RT_MASK 0x1f 43 #define RT_SH 16 44 #define RD_MASK 0x1f 45 #define RD_SH 11 46 #define RE_MASK 0x1f 47 #define RE_SH 6 48 #define IMM_MASK 0xffff 49 #define IMM_SH 0 50 #define JIMM_MASK 0x3ffffff 51 #define JIMM_SH 0 52 #define FUNC_MASK 0x3f 53 #define FUNC_SH 0 54 #define SET_MASK 0x7 55 #define SET_SH 0 56 #define SCIMM_MASK 0xfffff 57 #define SCIMM_SH 6 58 59 enum opcode { 60 insn_invalid, 61 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, 62 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 63 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, 64 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, 65 insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret, 66 insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld, 67 insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori, 68 insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, 69 insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp, 70 insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, 71 insn_dins, insn_syscall, insn_bbit0, insn_bbit1 72 }; 73 74 struct insn { 75 enum opcode opcode; 76 u32 match; 77 enum fields fields; 78 }; 79 80 /* This macro sets the non-variable bits of an instruction. */ 81 #define M(a, b, c, d, e, f) \ 82 ((a) << OP_SH \ 83 | (b) << RS_SH \ 84 | (c) << RT_SH \ 85 | (d) << RD_SH \ 86 | (e) << RE_SH \ 87 | (f) << FUNC_SH) 88 89 static struct insn insn_table[] __uasminitdata = { 90 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 91 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, 92 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, 93 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 94 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 95 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 96 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM }, 97 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM }, 98 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM }, 99 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, 100 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 101 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 102 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 103 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, 104 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, 105 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, 106 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE }, 107 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE }, 108 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, 109 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, 110 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, 111 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE }, 112 { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, 113 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, 114 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, 115 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, 116 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, 117 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, 118 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 119 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 120 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 121 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM }, 122 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 123 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, 124 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, 125 { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD }, 126 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 127 { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 128 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, 129 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 130 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 131 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 132 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, 133 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, 134 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, 135 { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE }, 136 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, 137 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 138 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, 139 { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, 140 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, 141 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, 142 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, 143 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 144 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, 145 { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, 146 { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 147 { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 148 { insn_invalid, 0, 0 } 149 }; 150 151 #undef M 152 153 static inline __uasminit u32 build_rs(u32 arg) 154 { 155 if (arg & ~RS_MASK) 156 printk(KERN_WARNING "Micro-assembler field overflow\n"); 157 158 return (arg & RS_MASK) << RS_SH; 159 } 160 161 static inline __uasminit u32 build_rt(u32 arg) 162 { 163 if (arg & ~RT_MASK) 164 printk(KERN_WARNING "Micro-assembler field overflow\n"); 165 166 return (arg & RT_MASK) << RT_SH; 167 } 168 169 static inline __uasminit u32 build_rd(u32 arg) 170 { 171 if (arg & ~RD_MASK) 172 printk(KERN_WARNING "Micro-assembler field overflow\n"); 173 174 return (arg & RD_MASK) << RD_SH; 175 } 176 177 static inline __uasminit u32 build_re(u32 arg) 178 { 179 if (arg & ~RE_MASK) 180 printk(KERN_WARNING "Micro-assembler field overflow\n"); 181 182 return (arg & RE_MASK) << RE_SH; 183 } 184 185 static inline __uasminit u32 build_simm(s32 arg) 186 { 187 if (arg > 0x7fff || arg < -0x8000) 188 printk(KERN_WARNING "Micro-assembler field overflow\n"); 189 190 return arg & 0xffff; 191 } 192 193 static inline __uasminit u32 build_uimm(u32 arg) 194 { 195 if (arg & ~IMM_MASK) 196 printk(KERN_WARNING "Micro-assembler field overflow\n"); 197 198 return arg & IMM_MASK; 199 } 200 201 static inline __uasminit u32 build_bimm(s32 arg) 202 { 203 if (arg > 0x1ffff || arg < -0x20000) 204 printk(KERN_WARNING "Micro-assembler field overflow\n"); 205 206 if (arg & 0x3) 207 printk(KERN_WARNING "Invalid micro-assembler branch target\n"); 208 209 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); 210 } 211 212 static inline __uasminit u32 build_jimm(u32 arg) 213 { 214 if (arg & ~((JIMM_MASK) << 2)) 215 printk(KERN_WARNING "Micro-assembler field overflow\n"); 216 217 return (arg >> 2) & JIMM_MASK; 218 } 219 220 static inline __uasminit u32 build_scimm(u32 arg) 221 { 222 if (arg & ~SCIMM_MASK) 223 printk(KERN_WARNING "Micro-assembler field overflow\n"); 224 225 return (arg & SCIMM_MASK) << SCIMM_SH; 226 } 227 228 static inline __uasminit u32 build_func(u32 arg) 229 { 230 if (arg & ~FUNC_MASK) 231 printk(KERN_WARNING "Micro-assembler field overflow\n"); 232 233 return arg & FUNC_MASK; 234 } 235 236 static inline __uasminit u32 build_set(u32 arg) 237 { 238 if (arg & ~SET_MASK) 239 printk(KERN_WARNING "Micro-assembler field overflow\n"); 240 241 return arg & SET_MASK; 242 } 243 244 /* 245 * The order of opcode arguments is implicitly left to right, 246 * starting with RS and ending with FUNC or IMM. 247 */ 248 static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) 249 { 250 struct insn *ip = NULL; 251 unsigned int i; 252 va_list ap; 253 u32 op; 254 255 for (i = 0; insn_table[i].opcode != insn_invalid; i++) 256 if (insn_table[i].opcode == opc) { 257 ip = &insn_table[i]; 258 break; 259 } 260 261 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) 262 panic("Unsupported Micro-assembler instruction %d", opc); 263 264 op = ip->match; 265 va_start(ap, opc); 266 if (ip->fields & RS) 267 op |= build_rs(va_arg(ap, u32)); 268 if (ip->fields & RT) 269 op |= build_rt(va_arg(ap, u32)); 270 if (ip->fields & RD) 271 op |= build_rd(va_arg(ap, u32)); 272 if (ip->fields & RE) 273 op |= build_re(va_arg(ap, u32)); 274 if (ip->fields & SIMM) 275 op |= build_simm(va_arg(ap, s32)); 276 if (ip->fields & UIMM) 277 op |= build_uimm(va_arg(ap, u32)); 278 if (ip->fields & BIMM) 279 op |= build_bimm(va_arg(ap, s32)); 280 if (ip->fields & JIMM) 281 op |= build_jimm(va_arg(ap, u32)); 282 if (ip->fields & FUNC) 283 op |= build_func(va_arg(ap, u32)); 284 if (ip->fields & SET) 285 op |= build_set(va_arg(ap, u32)); 286 if (ip->fields & SCIMM) 287 op |= build_scimm(va_arg(ap, u32)); 288 va_end(ap); 289 290 **buf = op; 291 (*buf)++; 292 } 293 294 #define I_u1u2u3(op) \ 295 Ip_u1u2u3(op) \ 296 { \ 297 build_insn(buf, insn##op, a, b, c); \ 298 } \ 299 UASM_EXPORT_SYMBOL(uasm_i##op); 300 301 #define I_u2u1u3(op) \ 302 Ip_u2u1u3(op) \ 303 { \ 304 build_insn(buf, insn##op, b, a, c); \ 305 } \ 306 UASM_EXPORT_SYMBOL(uasm_i##op); 307 308 #define I_u3u1u2(op) \ 309 Ip_u3u1u2(op) \ 310 { \ 311 build_insn(buf, insn##op, b, c, a); \ 312 } \ 313 UASM_EXPORT_SYMBOL(uasm_i##op); 314 315 #define I_u1u2s3(op) \ 316 Ip_u1u2s3(op) \ 317 { \ 318 build_insn(buf, insn##op, a, b, c); \ 319 } \ 320 UASM_EXPORT_SYMBOL(uasm_i##op); 321 322 #define I_u2s3u1(op) \ 323 Ip_u2s3u1(op) \ 324 { \ 325 build_insn(buf, insn##op, c, a, b); \ 326 } \ 327 UASM_EXPORT_SYMBOL(uasm_i##op); 328 329 #define I_u2u1s3(op) \ 330 Ip_u2u1s3(op) \ 331 { \ 332 build_insn(buf, insn##op, b, a, c); \ 333 } \ 334 UASM_EXPORT_SYMBOL(uasm_i##op); 335 336 #define I_u2u1msbu3(op) \ 337 Ip_u2u1msbu3(op) \ 338 { \ 339 build_insn(buf, insn##op, b, a, c+d-1, c); \ 340 } \ 341 UASM_EXPORT_SYMBOL(uasm_i##op); 342 343 #define I_u1u2(op) \ 344 Ip_u1u2(op) \ 345 { \ 346 build_insn(buf, insn##op, a, b); \ 347 } \ 348 UASM_EXPORT_SYMBOL(uasm_i##op); 349 350 #define I_u1s2(op) \ 351 Ip_u1s2(op) \ 352 { \ 353 build_insn(buf, insn##op, a, b); \ 354 } \ 355 UASM_EXPORT_SYMBOL(uasm_i##op); 356 357 #define I_u1(op) \ 358 Ip_u1(op) \ 359 { \ 360 build_insn(buf, insn##op, a); \ 361 } \ 362 UASM_EXPORT_SYMBOL(uasm_i##op); 363 364 #define I_0(op) \ 365 Ip_0(op) \ 366 { \ 367 build_insn(buf, insn##op); \ 368 } \ 369 UASM_EXPORT_SYMBOL(uasm_i##op); 370 371 I_u2u1s3(_addiu) 372 I_u3u1u2(_addu) 373 I_u2u1u3(_andi) 374 I_u3u1u2(_and) 375 I_u1u2s3(_beq) 376 I_u1u2s3(_beql) 377 I_u1s2(_bgez) 378 I_u1s2(_bgezl) 379 I_u1s2(_bltz) 380 I_u1s2(_bltzl) 381 I_u1u2s3(_bne) 382 I_u2s3u1(_cache) 383 I_u1u2u3(_dmfc0) 384 I_u1u2u3(_dmtc0) 385 I_u2u1s3(_daddiu) 386 I_u3u1u2(_daddu) 387 I_u2u1u3(_dsll) 388 I_u2u1u3(_dsll32) 389 I_u2u1u3(_dsra) 390 I_u2u1u3(_dsrl) 391 I_u2u1u3(_dsrl32) 392 I_u2u1u3(_drotr) 393 I_u2u1u3(_drotr32) 394 I_u3u1u2(_dsubu) 395 I_0(_eret) 396 I_u1(_j) 397 I_u1(_jal) 398 I_u1(_jr) 399 I_u2s3u1(_ld) 400 I_u2s3u1(_ll) 401 I_u2s3u1(_lld) 402 I_u1s2(_lui) 403 I_u2s3u1(_lw) 404 I_u1u2u3(_mfc0) 405 I_u1u2u3(_mtc0) 406 I_u2u1u3(_ori) 407 I_u3u1u2(_or) 408 I_u2s3u1(_pref) 409 I_0(_rfe) 410 I_u2s3u1(_sc) 411 I_u2s3u1(_scd) 412 I_u2s3u1(_sd) 413 I_u2u1u3(_sll) 414 I_u2u1u3(_sra) 415 I_u2u1u3(_srl) 416 I_u2u1u3(_rotr) 417 I_u3u1u2(_subu) 418 I_u2s3u1(_sw) 419 I_0(_tlbp) 420 I_0(_tlbr) 421 I_0(_tlbwi) 422 I_0(_tlbwr) 423 I_u3u1u2(_xor) 424 I_u2u1u3(_xori) 425 I_u2u1msbu3(_dins); 426 I_u1(_syscall); 427 I_u1u2s3(_bbit0); 428 I_u1u2s3(_bbit1); 429 430 /* Handle labels. */ 431 void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) 432 { 433 (*lab)->addr = addr; 434 (*lab)->lab = lid; 435 (*lab)++; 436 } 437 UASM_EXPORT_SYMBOL(uasm_build_label); 438 439 int __uasminit uasm_in_compat_space_p(long addr) 440 { 441 /* Is this address in 32bit compat space? */ 442 #ifdef CONFIG_64BIT 443 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); 444 #else 445 return 1; 446 #endif 447 } 448 UASM_EXPORT_SYMBOL(uasm_in_compat_space_p); 449 450 static int __uasminit uasm_rel_highest(long val) 451 { 452 #ifdef CONFIG_64BIT 453 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 454 #else 455 return 0; 456 #endif 457 } 458 459 static int __uasminit uasm_rel_higher(long val) 460 { 461 #ifdef CONFIG_64BIT 462 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 463 #else 464 return 0; 465 #endif 466 } 467 468 int __uasminit uasm_rel_hi(long val) 469 { 470 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 471 } 472 UASM_EXPORT_SYMBOL(uasm_rel_hi); 473 474 int __uasminit uasm_rel_lo(long val) 475 { 476 return ((val & 0xffff) ^ 0x8000) - 0x8000; 477 } 478 UASM_EXPORT_SYMBOL(uasm_rel_lo); 479 480 void __uasminit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr) 481 { 482 if (!uasm_in_compat_space_p(addr)) { 483 uasm_i_lui(buf, rs, uasm_rel_highest(addr)); 484 if (uasm_rel_higher(addr)) 485 uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr)); 486 if (uasm_rel_hi(addr)) { 487 uasm_i_dsll(buf, rs, rs, 16); 488 uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr)); 489 uasm_i_dsll(buf, rs, rs, 16); 490 } else 491 uasm_i_dsll32(buf, rs, rs, 0); 492 } else 493 uasm_i_lui(buf, rs, uasm_rel_hi(addr)); 494 } 495 UASM_EXPORT_SYMBOL(UASM_i_LA_mostly); 496 497 void __uasminit UASM_i_LA(u32 **buf, unsigned int rs, long addr) 498 { 499 UASM_i_LA_mostly(buf, rs, addr); 500 if (uasm_rel_lo(addr)) { 501 if (!uasm_in_compat_space_p(addr)) 502 uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr)); 503 else 504 uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr)); 505 } 506 } 507 UASM_EXPORT_SYMBOL(UASM_i_LA); 508 509 /* Handle relocations. */ 510 void __uasminit 511 uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid) 512 { 513 (*rel)->addr = addr; 514 (*rel)->type = R_MIPS_PC16; 515 (*rel)->lab = lid; 516 (*rel)++; 517 } 518 UASM_EXPORT_SYMBOL(uasm_r_mips_pc16); 519 520 static inline void __uasminit 521 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) 522 { 523 long laddr = (long)lab->addr; 524 long raddr = (long)rel->addr; 525 526 switch (rel->type) { 527 case R_MIPS_PC16: 528 *rel->addr |= build_bimm(laddr - (raddr + 4)); 529 break; 530 531 default: 532 panic("Unsupported Micro-assembler relocation %d", 533 rel->type); 534 } 535 } 536 537 void __uasminit 538 uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) 539 { 540 struct uasm_label *l; 541 542 for (; rel->lab != UASM_LABEL_INVALID; rel++) 543 for (l = lab; l->lab != UASM_LABEL_INVALID; l++) 544 if (rel->lab == l->lab) 545 __resolve_relocs(rel, l); 546 } 547 UASM_EXPORT_SYMBOL(uasm_resolve_relocs); 548 549 void __uasminit 550 uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off) 551 { 552 for (; rel->lab != UASM_LABEL_INVALID; rel++) 553 if (rel->addr >= first && rel->addr < end) 554 rel->addr += off; 555 } 556 UASM_EXPORT_SYMBOL(uasm_move_relocs); 557 558 void __uasminit 559 uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off) 560 { 561 for (; lab->lab != UASM_LABEL_INVALID; lab++) 562 if (lab->addr >= first && lab->addr < end) 563 lab->addr += off; 564 } 565 UASM_EXPORT_SYMBOL(uasm_move_labels); 566 567 void __uasminit 568 uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first, 569 u32 *end, u32 *target) 570 { 571 long off = (long)(target - first); 572 573 memcpy(target, first, (end - first) * sizeof(u32)); 574 575 uasm_move_relocs(rel, first, end, off); 576 uasm_move_labels(lab, first, end, off); 577 } 578 UASM_EXPORT_SYMBOL(uasm_copy_handler); 579 580 int __uasminit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr) 581 { 582 for (; rel->lab != UASM_LABEL_INVALID; rel++) { 583 if (rel->addr == addr 584 && (rel->type == R_MIPS_PC16 585 || rel->type == R_MIPS_26)) 586 return 1; 587 } 588 589 return 0; 590 } 591 UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay); 592 593 /* Convenience functions for labeled branches. */ 594 void __uasminit 595 uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 596 { 597 uasm_r_mips_pc16(r, *p, lid); 598 uasm_i_bltz(p, reg, 0); 599 } 600 UASM_EXPORT_SYMBOL(uasm_il_bltz); 601 602 void __uasminit 603 uasm_il_b(u32 **p, struct uasm_reloc **r, int lid) 604 { 605 uasm_r_mips_pc16(r, *p, lid); 606 uasm_i_b(p, 0); 607 } 608 UASM_EXPORT_SYMBOL(uasm_il_b); 609 610 void __uasminit 611 uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 612 { 613 uasm_r_mips_pc16(r, *p, lid); 614 uasm_i_beqz(p, reg, 0); 615 } 616 UASM_EXPORT_SYMBOL(uasm_il_beqz); 617 618 void __uasminit 619 uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 620 { 621 uasm_r_mips_pc16(r, *p, lid); 622 uasm_i_beqzl(p, reg, 0); 623 } 624 UASM_EXPORT_SYMBOL(uasm_il_beqzl); 625 626 void __uasminit 627 uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, 628 unsigned int reg2, int lid) 629 { 630 uasm_r_mips_pc16(r, *p, lid); 631 uasm_i_bne(p, reg1, reg2, 0); 632 } 633 UASM_EXPORT_SYMBOL(uasm_il_bne); 634 635 void __uasminit 636 uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 637 { 638 uasm_r_mips_pc16(r, *p, lid); 639 uasm_i_bnez(p, reg, 0); 640 } 641 UASM_EXPORT_SYMBOL(uasm_il_bnez); 642 643 void __uasminit 644 uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 645 { 646 uasm_r_mips_pc16(r, *p, lid); 647 uasm_i_bgezl(p, reg, 0); 648 } 649 UASM_EXPORT_SYMBOL(uasm_il_bgezl); 650 651 void __uasminit 652 uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 653 { 654 uasm_r_mips_pc16(r, *p, lid); 655 uasm_i_bgez(p, reg, 0); 656 } 657 UASM_EXPORT_SYMBOL(uasm_il_bgez); 658 659 void __uasminit 660 uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg, 661 unsigned int bit, int lid) 662 { 663 uasm_r_mips_pc16(r, *p, lid); 664 uasm_i_bbit0(p, reg, bit, 0); 665 } 666 UASM_EXPORT_SYMBOL(uasm_il_bbit0); 667 668 void __uasminit 669 uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg, 670 unsigned int bit, int lid) 671 { 672 uasm_r_mips_pc16(r, *p, lid); 673 uasm_i_bbit1(p, reg, bit, 0); 674 } 675 UASM_EXPORT_SYMBOL(uasm_il_bbit1); 676