1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 #ifndef __CVMX_SRXX_DEFS_H__ 29 #define __CVMX_SRXX_DEFS_H__ 30 31 #define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull) 32 #define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull) 33 #define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) 34 #define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull) 35 #define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull) 36 #define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull) 37 38 union cvmx_srxx_com_ctl { 39 uint64_t u64; 40 struct cvmx_srxx_com_ctl_s { 41 #ifdef __BIG_ENDIAN_BITFIELD 42 uint64_t reserved_8_63:56; 43 uint64_t prts:4; 44 uint64_t st_en:1; 45 uint64_t reserved_1_2:2; 46 uint64_t inf_en:1; 47 #else 48 uint64_t inf_en:1; 49 uint64_t reserved_1_2:2; 50 uint64_t st_en:1; 51 uint64_t prts:4; 52 uint64_t reserved_8_63:56; 53 #endif 54 } s; 55 struct cvmx_srxx_com_ctl_s cn38xx; 56 struct cvmx_srxx_com_ctl_s cn38xxp2; 57 struct cvmx_srxx_com_ctl_s cn58xx; 58 struct cvmx_srxx_com_ctl_s cn58xxp1; 59 }; 60 61 union cvmx_srxx_ign_rx_full { 62 uint64_t u64; 63 struct cvmx_srxx_ign_rx_full_s { 64 #ifdef __BIG_ENDIAN_BITFIELD 65 uint64_t reserved_16_63:48; 66 uint64_t ignore:16; 67 #else 68 uint64_t ignore:16; 69 uint64_t reserved_16_63:48; 70 #endif 71 } s; 72 struct cvmx_srxx_ign_rx_full_s cn38xx; 73 struct cvmx_srxx_ign_rx_full_s cn38xxp2; 74 struct cvmx_srxx_ign_rx_full_s cn58xx; 75 struct cvmx_srxx_ign_rx_full_s cn58xxp1; 76 }; 77 78 union cvmx_srxx_spi4_calx { 79 uint64_t u64; 80 struct cvmx_srxx_spi4_calx_s { 81 #ifdef __BIG_ENDIAN_BITFIELD 82 uint64_t reserved_17_63:47; 83 uint64_t oddpar:1; 84 uint64_t prt3:4; 85 uint64_t prt2:4; 86 uint64_t prt1:4; 87 uint64_t prt0:4; 88 #else 89 uint64_t prt0:4; 90 uint64_t prt1:4; 91 uint64_t prt2:4; 92 uint64_t prt3:4; 93 uint64_t oddpar:1; 94 uint64_t reserved_17_63:47; 95 #endif 96 } s; 97 struct cvmx_srxx_spi4_calx_s cn38xx; 98 struct cvmx_srxx_spi4_calx_s cn38xxp2; 99 struct cvmx_srxx_spi4_calx_s cn58xx; 100 struct cvmx_srxx_spi4_calx_s cn58xxp1; 101 }; 102 103 union cvmx_srxx_spi4_stat { 104 uint64_t u64; 105 struct cvmx_srxx_spi4_stat_s { 106 #ifdef __BIG_ENDIAN_BITFIELD 107 uint64_t reserved_16_63:48; 108 uint64_t m:8; 109 uint64_t reserved_7_7:1; 110 uint64_t len:7; 111 #else 112 uint64_t len:7; 113 uint64_t reserved_7_7:1; 114 uint64_t m:8; 115 uint64_t reserved_16_63:48; 116 #endif 117 } s; 118 struct cvmx_srxx_spi4_stat_s cn38xx; 119 struct cvmx_srxx_spi4_stat_s cn38xxp2; 120 struct cvmx_srxx_spi4_stat_s cn58xx; 121 struct cvmx_srxx_spi4_stat_s cn58xxp1; 122 }; 123 124 union cvmx_srxx_sw_tick_ctl { 125 uint64_t u64; 126 struct cvmx_srxx_sw_tick_ctl_s { 127 #ifdef __BIG_ENDIAN_BITFIELD 128 uint64_t reserved_14_63:50; 129 uint64_t eop:1; 130 uint64_t sop:1; 131 uint64_t mod:4; 132 uint64_t opc:4; 133 uint64_t adr:4; 134 #else 135 uint64_t adr:4; 136 uint64_t opc:4; 137 uint64_t mod:4; 138 uint64_t sop:1; 139 uint64_t eop:1; 140 uint64_t reserved_14_63:50; 141 #endif 142 } s; 143 struct cvmx_srxx_sw_tick_ctl_s cn38xx; 144 struct cvmx_srxx_sw_tick_ctl_s cn58xx; 145 struct cvmx_srxx_sw_tick_ctl_s cn58xxp1; 146 }; 147 148 union cvmx_srxx_sw_tick_dat { 149 uint64_t u64; 150 struct cvmx_srxx_sw_tick_dat_s { 151 #ifdef __BIG_ENDIAN_BITFIELD 152 uint64_t dat:64; 153 #else 154 uint64_t dat:64; 155 #endif 156 } s; 157 struct cvmx_srxx_sw_tick_dat_s cn38xx; 158 struct cvmx_srxx_sw_tick_dat_s cn58xx; 159 struct cvmx_srxx_sw_tick_dat_s cn58xxp1; 160 }; 161 162 #endif 163