1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 4 * Copyright (C) 2008-2009 PetaLogix 5 * Copyright (C) 2006 Atmark Techno, Inc. 6 */ 7 8 #ifndef _ASM_MICROBLAZE_PGTABLE_H 9 #define _ASM_MICROBLAZE_PGTABLE_H 10 11 #include <asm/setup.h> 12 13 #ifndef __ASSEMBLY__ 14 extern int mem_init_done; 15 #endif 16 17 #ifndef CONFIG_MMU 18 19 #define pgd_present(pgd) (1) /* pages are always present on non MMU */ 20 #define pgd_none(pgd) (0) 21 #define pgd_bad(pgd) (0) 22 #define pgd_clear(pgdp) 23 #define kern_addr_valid(addr) (1) 24 25 #define PAGE_NONE __pgprot(0) /* these mean nothing to non MMU */ 26 #define PAGE_SHARED __pgprot(0) /* these mean nothing to non MMU */ 27 #define PAGE_COPY __pgprot(0) /* these mean nothing to non MMU */ 28 #define PAGE_READONLY __pgprot(0) /* these mean nothing to non MMU */ 29 #define PAGE_KERNEL __pgprot(0) /* these mean nothing to non MMU */ 30 31 #define pgprot_noncached(x) (x) 32 #define pgprot_writecombine pgprot_noncached 33 #define pgprot_device pgprot_noncached 34 35 #define __swp_type(x) (0) 36 #define __swp_offset(x) (0) 37 #define __swp_entry(typ, off) ((swp_entry_t) { ((typ) | ((off) << 7)) }) 38 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 39 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 40 41 #define ZERO_PAGE(vaddr) ({ BUG(); NULL; }) 42 43 #define swapper_pg_dir ((pgd_t *) NULL) 44 45 #define arch_enter_lazy_cpu_mode() do {} while (0) 46 47 #define pgprot_noncached_wc(prot) prot 48 49 /* 50 * All 32bit addresses are effectively valid for vmalloc... 51 * Sort of meaningless for non-VM targets. 52 */ 53 #define VMALLOC_START 0 54 #define VMALLOC_END 0xffffffff 55 56 #else /* CONFIG_MMU */ 57 58 #include <asm-generic/pgtable-nopmd.h> 59 60 #ifdef __KERNEL__ 61 #ifndef __ASSEMBLY__ 62 63 #include <linux/sched.h> 64 #include <linux/threads.h> 65 #include <asm/processor.h> /* For TASK_SIZE */ 66 #include <asm/mmu.h> 67 #include <asm/page.h> 68 69 #define FIRST_USER_ADDRESS 0UL 70 71 extern unsigned long va_to_phys(unsigned long address); 72 extern pte_t *va_to_pte(unsigned long address); 73 74 /* 75 * The following only work if pte_present() is true. 76 * Undefined behaviour if not.. 77 */ 78 79 /* Start and end of the vmalloc area. */ 80 /* Make sure to map the vmalloc area above the pinned kernel memory area 81 of 32Mb. */ 82 #define VMALLOC_START (CONFIG_KERNEL_START + CONFIG_LOWMEM_SIZE) 83 #define VMALLOC_END ioremap_bot 84 85 #endif /* __ASSEMBLY__ */ 86 87 /* 88 * Macro to mark a page protection value as "uncacheable". 89 */ 90 91 #define _PAGE_CACHE_CTL (_PAGE_GUARDED | _PAGE_NO_CACHE | \ 92 _PAGE_WRITETHRU) 93 94 #define pgprot_noncached(prot) \ 95 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 96 _PAGE_NO_CACHE | _PAGE_GUARDED)) 97 98 #define pgprot_noncached_wc(prot) \ 99 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 100 _PAGE_NO_CACHE)) 101 102 /* 103 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash 104 * table containing PTEs, together with a set of 16 segment registers, to 105 * define the virtual to physical address mapping. 106 * 107 * We use the hash table as an extended TLB, i.e. a cache of currently 108 * active mappings. We maintain a two-level page table tree, much 109 * like that used by the i386, for the sake of the Linux memory 110 * management code. Low-level assembler code in hashtable.S 111 * (procedure hash_page) is responsible for extracting ptes from the 112 * tree and putting them into the hash table when necessary, and 113 * updating the accessed and modified bits in the page table tree. 114 */ 115 116 /* 117 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The 118 * instruction and data sides share a unified, 64-entry, semi-associative 119 * TLB which is maintained totally under software control. In addition, the 120 * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative 121 * TLB which serves as a first level to the shared TLB. These two TLBs are 122 * known as the UTLB and ITLB, respectively (see "mmu.h" for definitions). 123 */ 124 125 /* 126 * The normal case is that PTEs are 32-bits and we have a 1-page 127 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus 128 * 129 */ 130 131 /* PGDIR_SHIFT determines what a top-level page table entry can map */ 132 #define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT) 133 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 134 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 135 136 /* 137 * entries per page directory level: our page-table tree is two-level, so 138 * we don't really have any PMD directory. 139 */ 140 #define PTRS_PER_PTE (1 << PTE_SHIFT) 141 #define PTRS_PER_PMD 1 142 #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT)) 143 144 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 145 #define FIRST_USER_PGD_NR 0 146 147 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) 148 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS) 149 150 #define pte_ERROR(e) \ 151 printk(KERN_ERR "%s:%d: bad pte "PTE_FMT".\n", \ 152 __FILE__, __LINE__, pte_val(e)) 153 #define pgd_ERROR(e) \ 154 printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \ 155 __FILE__, __LINE__, pgd_val(e)) 156 157 /* 158 * Bits in a linux-style PTE. These match the bits in the 159 * (hardware-defined) PTE as closely as possible. 160 */ 161 162 /* There are several potential gotchas here. The hardware TLBLO 163 * field looks like this: 164 * 165 * 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 166 * RPN..................... 0 0 EX WR ZSEL....... W I M G 167 * 168 * Where possible we make the Linux PTE bits match up with this 169 * 170 * - bits 20 and 21 must be cleared, because we use 4k pages (4xx can 171 * support down to 1k pages), this is done in the TLBMiss exception 172 * handler. 173 * - We use only zones 0 (for kernel pages) and 1 (for user pages) 174 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB 175 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct 176 * zone. 177 * - PRESENT *must* be in the bottom two bits because swap cache 178 * entries use the top 30 bits. Because 4xx doesn't support SMP 179 * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 180 * is cleared in the TLB miss handler before the TLB entry is loaded. 181 * - All other bits of the PTE are loaded into TLBLO without 182 * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for 183 * software PTE bits. We actually use bits 21, 24, 25, and 184 * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and 185 * PRESENT. 186 */ 187 188 /* Definitions for MicroBlaze. */ 189 #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */ 190 #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */ 191 #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */ 192 #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */ 193 #define _PAGE_USER 0x010 /* matches one of the zone permission bits */ 194 #define _PAGE_RW 0x040 /* software: Writes permitted */ 195 #define _PAGE_DIRTY 0x080 /* software: dirty page */ 196 #define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */ 197 #define _PAGE_HWEXEC 0x200 /* hardware: EX permission */ 198 #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ 199 #define _PMD_PRESENT PAGE_MASK 200 201 /* 202 * Some bits are unused... 203 */ 204 #ifndef _PAGE_HASHPTE 205 #define _PAGE_HASHPTE 0 206 #endif 207 #ifndef _PTE_NONE_MASK 208 #define _PTE_NONE_MASK 0 209 #endif 210 #ifndef _PAGE_SHARED 211 #define _PAGE_SHARED 0 212 #endif 213 #ifndef _PAGE_EXEC 214 #define _PAGE_EXEC 0 215 #endif 216 217 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 218 219 /* 220 * Note: the _PAGE_COHERENT bit automatically gets set in the hardware 221 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need 222 * to have it in the Linux PTE, and in fact the bit could be reused for 223 * another purpose. -- paulus. 224 */ 225 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED) 226 #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE) 227 228 #define _PAGE_KERNEL \ 229 (_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | _PAGE_HWEXEC) 230 231 #define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED) 232 233 #define PAGE_NONE __pgprot(_PAGE_BASE) 234 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) 235 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 236 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) 237 #define PAGE_SHARED_X \ 238 __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) 239 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) 240 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 241 242 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 243 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_SHARED) 244 #define PAGE_KERNEL_CI __pgprot(_PAGE_IO) 245 246 /* 247 * We consider execute permission the same as read. 248 * Also, write permissions imply read permissions. 249 */ 250 #define __P000 PAGE_NONE 251 #define __P001 PAGE_READONLY_X 252 #define __P010 PAGE_COPY 253 #define __P011 PAGE_COPY_X 254 #define __P100 PAGE_READONLY 255 #define __P101 PAGE_READONLY_X 256 #define __P110 PAGE_COPY 257 #define __P111 PAGE_COPY_X 258 259 #define __S000 PAGE_NONE 260 #define __S001 PAGE_READONLY_X 261 #define __S010 PAGE_SHARED 262 #define __S011 PAGE_SHARED_X 263 #define __S100 PAGE_READONLY 264 #define __S101 PAGE_READONLY_X 265 #define __S110 PAGE_SHARED 266 #define __S111 PAGE_SHARED_X 267 268 #ifndef __ASSEMBLY__ 269 /* 270 * ZERO_PAGE is a global shared page that is always zero: used 271 * for zero-mapped memory areas etc.. 272 */ 273 extern unsigned long empty_zero_page[1024]; 274 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 275 276 #endif /* __ASSEMBLY__ */ 277 278 #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0) 279 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) 280 #define pte_clear(mm, addr, ptep) \ 281 do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0) 282 283 #define pmd_none(pmd) (!pmd_val(pmd)) 284 #define pmd_bad(pmd) ((pmd_val(pmd) & _PMD_PRESENT) == 0) 285 #define pmd_present(pmd) ((pmd_val(pmd) & _PMD_PRESENT) != 0) 286 #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0) 287 288 #define pte_page(x) (mem_map + (unsigned long) \ 289 ((pte_val(x) - memory_start) >> PAGE_SHIFT)) 290 #define PFN_SHIFT_OFFSET (PAGE_SHIFT) 291 292 #define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET) 293 294 #define pfn_pte(pfn, prot) \ 295 __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) | pgprot_val(prot)) 296 297 #ifndef __ASSEMBLY__ 298 /* 299 * The following only work if pte_present() is true. 300 * Undefined behaviour if not.. 301 */ 302 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; } 303 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } 304 static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } 305 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 306 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 307 308 static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; } 309 static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; } 310 311 static inline pte_t pte_rdprotect(pte_t pte) \ 312 { pte_val(pte) &= ~_PAGE_USER; return pte; } 313 static inline pte_t pte_wrprotect(pte_t pte) \ 314 { pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; } 315 static inline pte_t pte_exprotect(pte_t pte) \ 316 { pte_val(pte) &= ~_PAGE_EXEC; return pte; } 317 static inline pte_t pte_mkclean(pte_t pte) \ 318 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; } 319 static inline pte_t pte_mkold(pte_t pte) \ 320 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } 321 322 static inline pte_t pte_mkread(pte_t pte) \ 323 { pte_val(pte) |= _PAGE_USER; return pte; } 324 static inline pte_t pte_mkexec(pte_t pte) \ 325 { pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; } 326 static inline pte_t pte_mkwrite(pte_t pte) \ 327 { pte_val(pte) |= _PAGE_RW; return pte; } 328 static inline pte_t pte_mkdirty(pte_t pte) \ 329 { pte_val(pte) |= _PAGE_DIRTY; return pte; } 330 static inline pte_t pte_mkyoung(pte_t pte) \ 331 { pte_val(pte) |= _PAGE_ACCESSED; return pte; } 332 333 /* 334 * Conversion functions: convert a page and protection to a page entry, 335 * and a page entry and page directory to the page they refer to. 336 */ 337 338 static inline pte_t mk_pte_phys(phys_addr_t physpage, pgprot_t pgprot) 339 { 340 pte_t pte; 341 pte_val(pte) = physpage | pgprot_val(pgprot); 342 return pte; 343 } 344 345 #define mk_pte(page, pgprot) \ 346 ({ \ 347 pte_t pte; \ 348 pte_val(pte) = (((page - mem_map) << PAGE_SHIFT) + memory_start) | \ 349 pgprot_val(pgprot); \ 350 pte; \ 351 }) 352 353 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 354 { 355 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); 356 return pte; 357 } 358 359 /* 360 * Atomic PTE updates. 361 * 362 * pte_update clears and sets bit atomically, and returns 363 * the old pte value. 364 * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant 365 * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits. 366 */ 367 static inline unsigned long pte_update(pte_t *p, unsigned long clr, 368 unsigned long set) 369 { 370 unsigned long flags, old, tmp; 371 372 raw_local_irq_save(flags); 373 374 __asm__ __volatile__( "lw %0, %2, r0 \n" 375 "andn %1, %0, %3 \n" 376 "or %1, %1, %4 \n" 377 "sw %1, %2, r0 \n" 378 : "=&r" (old), "=&r" (tmp) 379 : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set) 380 : "cc"); 381 382 raw_local_irq_restore(flags); 383 384 return old; 385 } 386 387 /* 388 * set_pte stores a linux PTE into the linux page table. 389 */ 390 static inline void set_pte(struct mm_struct *mm, unsigned long addr, 391 pte_t *ptep, pte_t pte) 392 { 393 *ptep = pte; 394 } 395 396 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 397 pte_t *ptep, pte_t pte) 398 { 399 *ptep = pte; 400 } 401 402 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 403 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 404 unsigned long address, pte_t *ptep) 405 { 406 return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0; 407 } 408 409 static inline int ptep_test_and_clear_dirty(struct mm_struct *mm, 410 unsigned long addr, pte_t *ptep) 411 { 412 return (pte_update(ptep, \ 413 (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0; 414 } 415 416 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 417 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 418 unsigned long addr, pte_t *ptep) 419 { 420 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0)); 421 } 422 423 /*static inline void ptep_set_wrprotect(struct mm_struct *mm, 424 unsigned long addr, pte_t *ptep) 425 { 426 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0); 427 }*/ 428 429 static inline void ptep_mkdirty(struct mm_struct *mm, 430 unsigned long addr, pte_t *ptep) 431 { 432 pte_update(ptep, 0, _PAGE_DIRTY); 433 } 434 435 /*#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)*/ 436 437 /* Convert pmd entry to page */ 438 /* our pmd entry is an effective address of pte table*/ 439 /* returns effective address of the pmd entry*/ 440 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 441 { 442 return ((unsigned long) (pmd_val(pmd) & PAGE_MASK)); 443 } 444 445 /* returns struct *page of the pmd entry*/ 446 #define pmd_page(pmd) (pfn_to_page(__pa(pmd_val(pmd)) >> PAGE_SHIFT)) 447 448 /* Find an entry in the third-level page table.. */ 449 450 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 451 452 /* 453 * Encode and decode a swap entry. 454 * Note that the bits we use in a PTE for representing a swap entry 455 * must not include the _PAGE_PRESENT bit, or the _PAGE_HASHPTE bit 456 * (if used). -- paulus 457 */ 458 #define __swp_type(entry) ((entry).val & 0x3f) 459 #define __swp_offset(entry) ((entry).val >> 6) 460 #define __swp_entry(type, offset) \ 461 ((swp_entry_t) { (type) | ((offset) << 6) }) 462 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 2 }) 463 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 2 }) 464 465 extern unsigned long iopa(unsigned long addr); 466 467 /* Values for nocacheflag and cmode */ 468 /* These are not used by the APUS kernel_map, but prevents 469 * compilation errors. 470 */ 471 #define IOMAP_FULL_CACHING 0 472 #define IOMAP_NOCACHE_SER 1 473 #define IOMAP_NOCACHE_NONSER 2 474 #define IOMAP_NO_COPYBACK 3 475 476 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ 477 #define kern_addr_valid(addr) (1) 478 479 void do_page_fault(struct pt_regs *regs, unsigned long address, 480 unsigned long error_code); 481 482 void mapin_ram(void); 483 int map_page(unsigned long va, phys_addr_t pa, int flags); 484 485 extern int mem_init_done; 486 487 asmlinkage void __init mmu_init(void); 488 489 void __init *early_get_page(void); 490 491 #endif /* __ASSEMBLY__ */ 492 #endif /* __KERNEL__ */ 493 494 #endif /* CONFIG_MMU */ 495 496 #ifndef __ASSEMBLY__ 497 extern unsigned long ioremap_bot, ioremap_base; 498 499 void setup_memory(void); 500 #endif /* __ASSEMBLY__ */ 501 502 #endif /* _ASM_MICROBLAZE_PGTABLE_H */ 503