1 /* 2 * m54xxsim.h -- ColdFire 547x/548x System Integration Unit support. 3 */ 4 5 #ifndef m54xxsim_h 6 #define m54xxsim_h 7 8 #define CPU_NAME "COLDFIRE(m54xx)" 9 #define CPU_INSTR_PER_JIFFY 2 10 #define MCF_BUSCLK (MCF_CLK / 2) 11 12 #include <asm/m54xxacr.h> 13 14 #define MCFINT_VECBASE 64 15 16 /* 17 * Interrupt Controller Registers 18 */ 19 #define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */ 20 21 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 22 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 23 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 24 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 25 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 26 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 27 #define MCFINTC_IRLR 0x18 /* */ 28 #define MCFINTC_IACKL 0x19 /* */ 29 #define MCFINTC_ICR0 0x40 /* Base ICR register */ 30 31 /* 32 * UART module. 33 */ 34 #define MCFUART_BASE1 0x8600 /* Base address of UART1 */ 35 #define MCFUART_BASE2 0x8700 /* Base address of UART2 */ 36 #define MCFUART_BASE3 0x8800 /* Base address of UART3 */ 37 #define MCFUART_BASE4 0x8900 /* Base address of UART4 */ 38 39 /* 40 * Define system peripheral IRQ usage. 41 */ 42 #define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */ 43 #define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */ 44 45 /* 46 * Generic GPIO support 47 */ 48 #define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */ 49 #define MCFGPIO_IRQ_MAX -1 50 #define MCFGPIO_IRQ_VECBASE -1 51 52 /* 53 * EDGE Port support. 54 */ 55 #define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */ 56 #define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */ 57 #define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */ 58 #define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */ 59 #define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */ 60 #define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ 61 62 /* 63 * Some PSC related definitions 64 */ 65 #define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) 66 #define MCF_PAR_SDA (0x0008) 67 #define MCF_PAR_SCL (0x0004) 68 #define MCF_PAR_PSC_TXD (0x04) 69 #define MCF_PAR_PSC_RXD (0x08) 70 #define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4) 71 #define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6) 72 #define MCF_PAR_PSC_CTS_GPIO (0x00) 73 #define MCF_PAR_PSC_CTS_BCLK (0x80) 74 #define MCF_PAR_PSC_CTS_CTS (0xC0) 75 #define MCF_PAR_PSC_RTS_GPIO (0x00) 76 #define MCF_PAR_PSC_RTS_FSYNC (0x20) 77 #define MCF_PAR_PSC_RTS_RTS (0x30) 78 #define MCF_PAR_PSC_CANRX (0x40) 79 80 #endif /* m54xxsim_h */ 81