1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/mm/fault.c 4 * 5 * Copyright (C) 1995 Linus Torvalds 6 * Copyright (C) 1995-2004 Russell King 7 * Copyright (C) 2012 ARM Ltd. 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/extable.h> 12 #include <linux/signal.h> 13 #include <linux/mm.h> 14 #include <linux/hardirq.h> 15 #include <linux/init.h> 16 #include <linux/kprobes.h> 17 #include <linux/uaccess.h> 18 #include <linux/page-flags.h> 19 #include <linux/sched/signal.h> 20 #include <linux/sched/debug.h> 21 #include <linux/highmem.h> 22 #include <linux/perf_event.h> 23 #include <linux/preempt.h> 24 #include <linux/hugetlb.h> 25 26 #include <asm/acpi.h> 27 #include <asm/bug.h> 28 #include <asm/cmpxchg.h> 29 #include <asm/cpufeature.h> 30 #include <asm/exception.h> 31 #include <asm/daifflags.h> 32 #include <asm/debug-monitors.h> 33 #include <asm/esr.h> 34 #include <asm/kasan.h> 35 #include <asm/sysreg.h> 36 #include <asm/system_misc.h> 37 #include <asm/pgtable.h> 38 #include <asm/tlbflush.h> 39 #include <asm/traps.h> 40 41 struct fault_info { 42 int (*fn)(unsigned long addr, unsigned int esr, 43 struct pt_regs *regs); 44 int sig; 45 int code; 46 const char *name; 47 }; 48 49 static const struct fault_info fault_info[]; 50 static struct fault_info debug_fault_info[]; 51 52 static inline const struct fault_info *esr_to_fault_info(unsigned int esr) 53 { 54 return fault_info + (esr & ESR_ELx_FSC); 55 } 56 57 static inline const struct fault_info *esr_to_debug_fault_info(unsigned int esr) 58 { 59 return debug_fault_info + DBG_ESR_EVT(esr); 60 } 61 62 #ifdef CONFIG_KPROBES 63 static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr) 64 { 65 int ret = 0; 66 67 /* kprobe_running() needs smp_processor_id() */ 68 if (!user_mode(regs)) { 69 preempt_disable(); 70 if (kprobe_running() && kprobe_fault_handler(regs, esr)) 71 ret = 1; 72 preempt_enable(); 73 } 74 75 return ret; 76 } 77 #else 78 static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr) 79 { 80 return 0; 81 } 82 #endif 83 84 static void data_abort_decode(unsigned int esr) 85 { 86 pr_alert("Data abort info:\n"); 87 88 if (esr & ESR_ELx_ISV) { 89 pr_alert(" Access size = %u byte(s)\n", 90 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT)); 91 pr_alert(" SSE = %lu, SRT = %lu\n", 92 (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT, 93 (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT); 94 pr_alert(" SF = %lu, AR = %lu\n", 95 (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT, 96 (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT); 97 } else { 98 pr_alert(" ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK); 99 } 100 101 pr_alert(" CM = %lu, WnR = %lu\n", 102 (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT, 103 (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT); 104 } 105 106 static void mem_abort_decode(unsigned int esr) 107 { 108 pr_alert("Mem abort info:\n"); 109 110 pr_alert(" ESR = 0x%08x\n", esr); 111 pr_alert(" Exception class = %s, IL = %u bits\n", 112 esr_get_class_string(esr), 113 (esr & ESR_ELx_IL) ? 32 : 16); 114 pr_alert(" SET = %lu, FnV = %lu\n", 115 (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT, 116 (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT); 117 pr_alert(" EA = %lu, S1PTW = %lu\n", 118 (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT, 119 (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT); 120 121 if (esr_is_data_abort(esr)) 122 data_abort_decode(esr); 123 } 124 125 static inline bool is_ttbr0_addr(unsigned long addr) 126 { 127 /* entry assembly clears tags for TTBR0 addrs */ 128 return addr < TASK_SIZE; 129 } 130 131 static inline bool is_ttbr1_addr(unsigned long addr) 132 { 133 /* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */ 134 return arch_kasan_reset_tag(addr) >= VA_START; 135 } 136 137 /* 138 * Dump out the page tables associated with 'addr' in the currently active mm. 139 */ 140 static void show_pte(unsigned long addr) 141 { 142 struct mm_struct *mm; 143 pgd_t *pgdp; 144 pgd_t pgd; 145 146 if (is_ttbr0_addr(addr)) { 147 /* TTBR0 */ 148 mm = current->active_mm; 149 if (mm == &init_mm) { 150 pr_alert("[%016lx] user address but active_mm is swapper\n", 151 addr); 152 return; 153 } 154 } else if (is_ttbr1_addr(addr)) { 155 /* TTBR1 */ 156 mm = &init_mm; 157 } else { 158 pr_alert("[%016lx] address between user and kernel address ranges\n", 159 addr); 160 return; 161 } 162 163 pr_alert("%s pgtable: %luk pages, %u-bit VAs, pgdp=%016lx\n", 164 mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K, 165 mm == &init_mm ? VA_BITS : (int)vabits_user, 166 (unsigned long)virt_to_phys(mm->pgd)); 167 pgdp = pgd_offset(mm, addr); 168 pgd = READ_ONCE(*pgdp); 169 pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd)); 170 171 do { 172 pud_t *pudp, pud; 173 pmd_t *pmdp, pmd; 174 pte_t *ptep, pte; 175 176 if (pgd_none(pgd) || pgd_bad(pgd)) 177 break; 178 179 pudp = pud_offset(pgdp, addr); 180 pud = READ_ONCE(*pudp); 181 pr_cont(", pud=%016llx", pud_val(pud)); 182 if (pud_none(pud) || pud_bad(pud)) 183 break; 184 185 pmdp = pmd_offset(pudp, addr); 186 pmd = READ_ONCE(*pmdp); 187 pr_cont(", pmd=%016llx", pmd_val(pmd)); 188 if (pmd_none(pmd) || pmd_bad(pmd)) 189 break; 190 191 ptep = pte_offset_map(pmdp, addr); 192 pte = READ_ONCE(*ptep); 193 pr_cont(", pte=%016llx", pte_val(pte)); 194 pte_unmap(ptep); 195 } while(0); 196 197 pr_cont("\n"); 198 } 199 200 /* 201 * This function sets the access flags (dirty, accessed), as well as write 202 * permission, and only to a more permissive setting. 203 * 204 * It needs to cope with hardware update of the accessed/dirty state by other 205 * agents in the system and can safely skip the __sync_icache_dcache() call as, 206 * like set_pte_at(), the PTE is never changed from no-exec to exec here. 207 * 208 * Returns whether or not the PTE actually changed. 209 */ 210 int ptep_set_access_flags(struct vm_area_struct *vma, 211 unsigned long address, pte_t *ptep, 212 pte_t entry, int dirty) 213 { 214 pteval_t old_pteval, pteval; 215 pte_t pte = READ_ONCE(*ptep); 216 217 if (pte_same(pte, entry)) 218 return 0; 219 220 /* only preserve the access flags and write permission */ 221 pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY; 222 223 /* 224 * Setting the flags must be done atomically to avoid racing with the 225 * hardware update of the access/dirty state. The PTE_RDONLY bit must 226 * be set to the most permissive (lowest value) of *ptep and entry 227 * (calculated as: a & b == ~(~a | ~b)). 228 */ 229 pte_val(entry) ^= PTE_RDONLY; 230 pteval = pte_val(pte); 231 do { 232 old_pteval = pteval; 233 pteval ^= PTE_RDONLY; 234 pteval |= pte_val(entry); 235 pteval ^= PTE_RDONLY; 236 pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval); 237 } while (pteval != old_pteval); 238 239 flush_tlb_fix_spurious_fault(vma, address); 240 return 1; 241 } 242 243 static bool is_el1_instruction_abort(unsigned int esr) 244 { 245 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR; 246 } 247 248 static inline bool is_el1_permission_fault(unsigned long addr, unsigned int esr, 249 struct pt_regs *regs) 250 { 251 unsigned int ec = ESR_ELx_EC(esr); 252 unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE; 253 254 if (ec != ESR_ELx_EC_DABT_CUR && ec != ESR_ELx_EC_IABT_CUR) 255 return false; 256 257 if (fsc_type == ESR_ELx_FSC_PERM) 258 return true; 259 260 if (is_ttbr0_addr(addr) && system_uses_ttbr0_pan()) 261 return fsc_type == ESR_ELx_FSC_FAULT && 262 (regs->pstate & PSR_PAN_BIT); 263 264 return false; 265 } 266 267 static void die_kernel_fault(const char *msg, unsigned long addr, 268 unsigned int esr, struct pt_regs *regs) 269 { 270 bust_spinlocks(1); 271 272 pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg, 273 addr); 274 275 mem_abort_decode(esr); 276 277 show_pte(addr); 278 die("Oops", regs, esr); 279 bust_spinlocks(0); 280 do_exit(SIGKILL); 281 } 282 283 static void __do_kernel_fault(unsigned long addr, unsigned int esr, 284 struct pt_regs *regs) 285 { 286 const char *msg; 287 288 /* 289 * Are we prepared to handle this kernel fault? 290 * We are almost certainly not prepared to handle instruction faults. 291 */ 292 if (!is_el1_instruction_abort(esr) && fixup_exception(regs)) 293 return; 294 295 if (is_el1_permission_fault(addr, esr, regs)) { 296 if (esr & ESR_ELx_WNR) 297 msg = "write to read-only memory"; 298 else 299 msg = "read from unreadable memory"; 300 } else if (addr < PAGE_SIZE) { 301 msg = "NULL pointer dereference"; 302 } else { 303 msg = "paging request"; 304 } 305 306 die_kernel_fault(msg, addr, esr, regs); 307 } 308 309 static void set_thread_esr(unsigned long address, unsigned int esr) 310 { 311 current->thread.fault_address = address; 312 313 /* 314 * If the faulting address is in the kernel, we must sanitize the ESR. 315 * From userspace's point of view, kernel-only mappings don't exist 316 * at all, so we report them as level 0 translation faults. 317 * (This is not quite the way that "no mapping there at all" behaves: 318 * an alignment fault not caused by the memory type would take 319 * precedence over translation fault for a real access to empty 320 * space. Unfortunately we can't easily distinguish "alignment fault 321 * not caused by memory type" from "alignment fault caused by memory 322 * type", so we ignore this wrinkle and just return the translation 323 * fault.) 324 */ 325 if (!is_ttbr0_addr(current->thread.fault_address)) { 326 switch (ESR_ELx_EC(esr)) { 327 case ESR_ELx_EC_DABT_LOW: 328 /* 329 * These bits provide only information about the 330 * faulting instruction, which userspace knows already. 331 * We explicitly clear bits which are architecturally 332 * RES0 in case they are given meanings in future. 333 * We always report the ESR as if the fault was taken 334 * to EL1 and so ISV and the bits in ISS[23:14] are 335 * clear. (In fact it always will be a fault to EL1.) 336 */ 337 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL | 338 ESR_ELx_CM | ESR_ELx_WNR; 339 esr |= ESR_ELx_FSC_FAULT; 340 break; 341 case ESR_ELx_EC_IABT_LOW: 342 /* 343 * Claim a level 0 translation fault. 344 * All other bits are architecturally RES0 for faults 345 * reported with that DFSC value, so we clear them. 346 */ 347 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL; 348 esr |= ESR_ELx_FSC_FAULT; 349 break; 350 default: 351 /* 352 * This should never happen (entry.S only brings us 353 * into this code for insn and data aborts from a lower 354 * exception level). Fail safe by not providing an ESR 355 * context record at all. 356 */ 357 WARN(1, "ESR 0x%x is not DABT or IABT from EL0\n", esr); 358 esr = 0; 359 break; 360 } 361 } 362 363 current->thread.fault_code = esr; 364 } 365 366 static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs) 367 { 368 /* 369 * If we are in kernel mode at this point, we have no context to 370 * handle this fault with. 371 */ 372 if (user_mode(regs)) { 373 const struct fault_info *inf = esr_to_fault_info(esr); 374 375 set_thread_esr(addr, esr); 376 arm64_force_sig_fault(inf->sig, inf->code, (void __user *)addr, 377 inf->name); 378 } else { 379 __do_kernel_fault(addr, esr, regs); 380 } 381 } 382 383 #define VM_FAULT_BADMAP 0x010000 384 #define VM_FAULT_BADACCESS 0x020000 385 386 static vm_fault_t __do_page_fault(struct mm_struct *mm, unsigned long addr, 387 unsigned int mm_flags, unsigned long vm_flags) 388 { 389 struct vm_area_struct *vma = find_vma(mm, addr); 390 391 if (unlikely(!vma)) 392 return VM_FAULT_BADMAP; 393 394 /* 395 * Ok, we have a good vm_area for this memory access, so we can handle 396 * it. 397 */ 398 if (unlikely(vma->vm_start > addr)) { 399 if (!(vma->vm_flags & VM_GROWSDOWN)) 400 return VM_FAULT_BADMAP; 401 if (expand_stack(vma, addr)) 402 return VM_FAULT_BADMAP; 403 } 404 405 /* 406 * Check that the permissions on the VMA allow for the fault which 407 * occurred. 408 */ 409 if (!(vma->vm_flags & vm_flags)) 410 return VM_FAULT_BADACCESS; 411 return handle_mm_fault(vma, addr & PAGE_MASK, mm_flags); 412 } 413 414 static bool is_el0_instruction_abort(unsigned int esr) 415 { 416 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW; 417 } 418 419 /* 420 * Note: not valid for EL1 DC IVAC, but we never use that such that it 421 * should fault. EL0 cannot issue DC IVAC (undef). 422 */ 423 static bool is_write_abort(unsigned int esr) 424 { 425 return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM); 426 } 427 428 static int __kprobes do_page_fault(unsigned long addr, unsigned int esr, 429 struct pt_regs *regs) 430 { 431 const struct fault_info *inf; 432 struct mm_struct *mm = current->mm; 433 vm_fault_t fault, major = 0; 434 unsigned long vm_flags = VM_READ | VM_WRITE; 435 unsigned int mm_flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; 436 437 if (notify_page_fault(regs, esr)) 438 return 0; 439 440 /* 441 * If we're in an interrupt or have no user context, we must not take 442 * the fault. 443 */ 444 if (faulthandler_disabled() || !mm) 445 goto no_context; 446 447 if (user_mode(regs)) 448 mm_flags |= FAULT_FLAG_USER; 449 450 if (is_el0_instruction_abort(esr)) { 451 vm_flags = VM_EXEC; 452 mm_flags |= FAULT_FLAG_INSTRUCTION; 453 } else if (is_write_abort(esr)) { 454 vm_flags = VM_WRITE; 455 mm_flags |= FAULT_FLAG_WRITE; 456 } 457 458 if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) { 459 /* regs->orig_addr_limit may be 0 if we entered from EL0 */ 460 if (regs->orig_addr_limit == KERNEL_DS) 461 die_kernel_fault("access to user memory with fs=KERNEL_DS", 462 addr, esr, regs); 463 464 if (is_el1_instruction_abort(esr)) 465 die_kernel_fault("execution of user memory", 466 addr, esr, regs); 467 468 if (!search_exception_tables(regs->pc)) 469 die_kernel_fault("access to user memory outside uaccess routines", 470 addr, esr, regs); 471 } 472 473 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr); 474 475 /* 476 * As per x86, we may deadlock here. However, since the kernel only 477 * validly references user space from well defined areas of the code, 478 * we can bug out early if this is from code which shouldn't. 479 */ 480 if (!down_read_trylock(&mm->mmap_sem)) { 481 if (!user_mode(regs) && !search_exception_tables(regs->pc)) 482 goto no_context; 483 retry: 484 down_read(&mm->mmap_sem); 485 } else { 486 /* 487 * The above down_read_trylock() might have succeeded in which 488 * case, we'll have missed the might_sleep() from down_read(). 489 */ 490 might_sleep(); 491 #ifdef CONFIG_DEBUG_VM 492 if (!user_mode(regs) && !search_exception_tables(regs->pc)) { 493 up_read(&mm->mmap_sem); 494 goto no_context; 495 } 496 #endif 497 } 498 499 fault = __do_page_fault(mm, addr, mm_flags, vm_flags); 500 major |= fault & VM_FAULT_MAJOR; 501 502 if (fault & VM_FAULT_RETRY) { 503 /* 504 * If we need to retry but a fatal signal is pending, 505 * handle the signal first. We do not need to release 506 * the mmap_sem because it would already be released 507 * in __lock_page_or_retry in mm/filemap.c. 508 */ 509 if (fatal_signal_pending(current)) { 510 if (!user_mode(regs)) 511 goto no_context; 512 return 0; 513 } 514 515 /* 516 * Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk of 517 * starvation. 518 */ 519 if (mm_flags & FAULT_FLAG_ALLOW_RETRY) { 520 mm_flags &= ~FAULT_FLAG_ALLOW_RETRY; 521 mm_flags |= FAULT_FLAG_TRIED; 522 goto retry; 523 } 524 } 525 up_read(&mm->mmap_sem); 526 527 /* 528 * Handle the "normal" (no error) case first. 529 */ 530 if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP | 531 VM_FAULT_BADACCESS)))) { 532 /* 533 * Major/minor page fault accounting is only done 534 * once. If we go through a retry, it is extremely 535 * likely that the page will be found in page cache at 536 * that point. 537 */ 538 if (major) { 539 current->maj_flt++; 540 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, 541 addr); 542 } else { 543 current->min_flt++; 544 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, 545 addr); 546 } 547 548 return 0; 549 } 550 551 /* 552 * If we are in kernel mode at this point, we have no context to 553 * handle this fault with. 554 */ 555 if (!user_mode(regs)) 556 goto no_context; 557 558 if (fault & VM_FAULT_OOM) { 559 /* 560 * We ran out of memory, call the OOM killer, and return to 561 * userspace (which will retry the fault, or kill us if we got 562 * oom-killed). 563 */ 564 pagefault_out_of_memory(); 565 return 0; 566 } 567 568 inf = esr_to_fault_info(esr); 569 set_thread_esr(addr, esr); 570 if (fault & VM_FAULT_SIGBUS) { 571 /* 572 * We had some memory, but were unable to successfully fix up 573 * this page fault. 574 */ 575 arm64_force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)addr, 576 inf->name); 577 } else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) { 578 unsigned int lsb; 579 580 lsb = PAGE_SHIFT; 581 if (fault & VM_FAULT_HWPOISON_LARGE) 582 lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault)); 583 584 arm64_force_sig_mceerr(BUS_MCEERR_AR, (void __user *)addr, lsb, 585 inf->name); 586 } else { 587 /* 588 * Something tried to access memory that isn't in our memory 589 * map. 590 */ 591 arm64_force_sig_fault(SIGSEGV, 592 fault == VM_FAULT_BADACCESS ? SEGV_ACCERR : SEGV_MAPERR, 593 (void __user *)addr, 594 inf->name); 595 } 596 597 return 0; 598 599 no_context: 600 __do_kernel_fault(addr, esr, regs); 601 return 0; 602 } 603 604 static int __kprobes do_translation_fault(unsigned long addr, 605 unsigned int esr, 606 struct pt_regs *regs) 607 { 608 if (is_ttbr0_addr(addr)) 609 return do_page_fault(addr, esr, regs); 610 611 do_bad_area(addr, esr, regs); 612 return 0; 613 } 614 615 static int do_alignment_fault(unsigned long addr, unsigned int esr, 616 struct pt_regs *regs) 617 { 618 do_bad_area(addr, esr, regs); 619 return 0; 620 } 621 622 static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs) 623 { 624 return 1; /* "fault" */ 625 } 626 627 static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) 628 { 629 const struct fault_info *inf; 630 void __user *siaddr; 631 632 inf = esr_to_fault_info(esr); 633 634 /* 635 * Return value ignored as we rely on signal merging. 636 * Future patches will make this more robust. 637 */ 638 apei_claim_sea(regs); 639 640 if (esr & ESR_ELx_FnV) 641 siaddr = NULL; 642 else 643 siaddr = (void __user *)addr; 644 arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr); 645 646 return 0; 647 } 648 649 static const struct fault_info fault_info[] = { 650 { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" }, 651 { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" }, 652 { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" }, 653 { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" }, 654 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" }, 655 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" }, 656 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" }, 657 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" }, 658 { do_bad, SIGKILL, SI_KERNEL, "unknown 8" }, 659 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" }, 660 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" }, 661 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" }, 662 { do_bad, SIGKILL, SI_KERNEL, "unknown 12" }, 663 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" }, 664 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" }, 665 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" }, 666 { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" }, 667 { do_bad, SIGKILL, SI_KERNEL, "unknown 17" }, 668 { do_bad, SIGKILL, SI_KERNEL, "unknown 18" }, 669 { do_bad, SIGKILL, SI_KERNEL, "unknown 19" }, 670 { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" }, 671 { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" }, 672 { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" }, 673 { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" }, 674 { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented 675 { do_bad, SIGKILL, SI_KERNEL, "unknown 25" }, 676 { do_bad, SIGKILL, SI_KERNEL, "unknown 26" }, 677 { do_bad, SIGKILL, SI_KERNEL, "unknown 27" }, 678 { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 679 { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 680 { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 681 { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 682 { do_bad, SIGKILL, SI_KERNEL, "unknown 32" }, 683 { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" }, 684 { do_bad, SIGKILL, SI_KERNEL, "unknown 34" }, 685 { do_bad, SIGKILL, SI_KERNEL, "unknown 35" }, 686 { do_bad, SIGKILL, SI_KERNEL, "unknown 36" }, 687 { do_bad, SIGKILL, SI_KERNEL, "unknown 37" }, 688 { do_bad, SIGKILL, SI_KERNEL, "unknown 38" }, 689 { do_bad, SIGKILL, SI_KERNEL, "unknown 39" }, 690 { do_bad, SIGKILL, SI_KERNEL, "unknown 40" }, 691 { do_bad, SIGKILL, SI_KERNEL, "unknown 41" }, 692 { do_bad, SIGKILL, SI_KERNEL, "unknown 42" }, 693 { do_bad, SIGKILL, SI_KERNEL, "unknown 43" }, 694 { do_bad, SIGKILL, SI_KERNEL, "unknown 44" }, 695 { do_bad, SIGKILL, SI_KERNEL, "unknown 45" }, 696 { do_bad, SIGKILL, SI_KERNEL, "unknown 46" }, 697 { do_bad, SIGKILL, SI_KERNEL, "unknown 47" }, 698 { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" }, 699 { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" }, 700 { do_bad, SIGKILL, SI_KERNEL, "unknown 50" }, 701 { do_bad, SIGKILL, SI_KERNEL, "unknown 51" }, 702 { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" }, 703 { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" }, 704 { do_bad, SIGKILL, SI_KERNEL, "unknown 54" }, 705 { do_bad, SIGKILL, SI_KERNEL, "unknown 55" }, 706 { do_bad, SIGKILL, SI_KERNEL, "unknown 56" }, 707 { do_bad, SIGKILL, SI_KERNEL, "unknown 57" }, 708 { do_bad, SIGKILL, SI_KERNEL, "unknown 58" }, 709 { do_bad, SIGKILL, SI_KERNEL, "unknown 59" }, 710 { do_bad, SIGKILL, SI_KERNEL, "unknown 60" }, 711 { do_bad, SIGKILL, SI_KERNEL, "section domain fault" }, 712 { do_bad, SIGKILL, SI_KERNEL, "page domain fault" }, 713 { do_bad, SIGKILL, SI_KERNEL, "unknown 63" }, 714 }; 715 716 asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, 717 struct pt_regs *regs) 718 { 719 const struct fault_info *inf = esr_to_fault_info(esr); 720 721 if (!inf->fn(addr, esr, regs)) 722 return; 723 724 if (!user_mode(regs)) { 725 pr_alert("Unhandled fault at 0x%016lx\n", addr); 726 mem_abort_decode(esr); 727 show_pte(addr); 728 } 729 730 arm64_notify_die(inf->name, regs, 731 inf->sig, inf->code, (void __user *)addr, esr); 732 } 733 734 asmlinkage void __exception do_el0_irq_bp_hardening(void) 735 { 736 /* PC has already been checked in entry.S */ 737 arm64_apply_bp_hardening(); 738 } 739 740 asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, 741 unsigned int esr, 742 struct pt_regs *regs) 743 { 744 /* 745 * We've taken an instruction abort from userspace and not yet 746 * re-enabled IRQs. If the address is a kernel address, apply 747 * BP hardening prior to enabling IRQs and pre-emption. 748 */ 749 if (!is_ttbr0_addr(addr)) 750 arm64_apply_bp_hardening(); 751 752 local_daif_restore(DAIF_PROCCTX); 753 do_mem_abort(addr, esr, regs); 754 } 755 756 757 asmlinkage void __exception do_sp_pc_abort(unsigned long addr, 758 unsigned int esr, 759 struct pt_regs *regs) 760 { 761 if (user_mode(regs)) { 762 if (!is_ttbr0_addr(instruction_pointer(regs))) 763 arm64_apply_bp_hardening(); 764 local_daif_restore(DAIF_PROCCTX); 765 } 766 767 arm64_notify_die("SP/PC alignment exception", regs, 768 SIGBUS, BUS_ADRALN, (void __user *)addr, esr); 769 } 770 771 int __init early_brk64(unsigned long addr, unsigned int esr, 772 struct pt_regs *regs); 773 774 /* 775 * __refdata because early_brk64 is __init, but the reference to it is 776 * clobbered at arch_initcall time. 777 * See traps.c and debug-monitors.c:debug_traps_init(). 778 */ 779 static struct fault_info __refdata debug_fault_info[] = { 780 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware breakpoint" }, 781 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware single-step" }, 782 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware watchpoint" }, 783 { do_bad, SIGKILL, SI_KERNEL, "unknown 3" }, 784 { do_bad, SIGTRAP, TRAP_BRKPT, "aarch32 BKPT" }, 785 { do_bad, SIGKILL, SI_KERNEL, "aarch32 vector catch" }, 786 { early_brk64, SIGTRAP, TRAP_BRKPT, "aarch64 BRK" }, 787 { do_bad, SIGKILL, SI_KERNEL, "unknown 7" }, 788 }; 789 790 void __init hook_debug_fault_code(int nr, 791 int (*fn)(unsigned long, unsigned int, struct pt_regs *), 792 int sig, int code, const char *name) 793 { 794 BUG_ON(nr < 0 || nr >= ARRAY_SIZE(debug_fault_info)); 795 796 debug_fault_info[nr].fn = fn; 797 debug_fault_info[nr].sig = sig; 798 debug_fault_info[nr].code = code; 799 debug_fault_info[nr].name = name; 800 } 801 802 #ifdef CONFIG_ARM64_ERRATUM_1463225 803 DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); 804 805 static int __exception 806 cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) 807 { 808 if (user_mode(regs)) 809 return 0; 810 811 if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa)) 812 return 0; 813 814 /* 815 * We've taken a dummy step exception from the kernel to ensure 816 * that interrupts are re-enabled on the syscall path. Return back 817 * to cortex_a76_erratum_1463225_svc_handler() with debug exceptions 818 * masked so that we can safely restore the mdscr and get on with 819 * handling the syscall. 820 */ 821 regs->pstate |= PSR_D_BIT; 822 return 1; 823 } 824 #else 825 static int __exception 826 cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) 827 { 828 return 0; 829 } 830 #endif /* CONFIG_ARM64_ERRATUM_1463225 */ 831 832 asmlinkage void __exception do_debug_exception(unsigned long addr_if_watchpoint, 833 unsigned int esr, 834 struct pt_regs *regs) 835 { 836 const struct fault_info *inf = esr_to_debug_fault_info(esr); 837 unsigned long pc = instruction_pointer(regs); 838 839 if (cortex_a76_erratum_1463225_debug_handler(regs)) 840 return; 841 842 /* 843 * Tell lockdep we disabled irqs in entry.S. Do nothing if they were 844 * already disabled to preserve the last enabled/disabled addresses. 845 */ 846 if (interrupts_enabled(regs)) 847 trace_hardirqs_off(); 848 849 if (user_mode(regs) && !is_ttbr0_addr(pc)) 850 arm64_apply_bp_hardening(); 851 852 if (inf->fn(addr_if_watchpoint, esr, regs)) { 853 arm64_notify_die(inf->name, regs, 854 inf->sig, inf->code, (void __user *)pc, esr); 855 } 856 857 if (interrupts_enabled(regs)) 858 trace_hardirqs_on(); 859 } 860 NOKPROBE_SYMBOL(do_debug_exception); 861