1 /* 2 * Based on arch/arm/include/asm/ptrace.h 3 * 4 * Copyright (C) 1996-2003 Russell King 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef __ASM_PTRACE_H 20 #define __ASM_PTRACE_H 21 22 #include <linux/types.h> 23 24 #include <asm/hwcap.h> 25 26 /* AArch32-specific ptrace requests */ 27 #define COMPAT_PTRACE_GETREGS 12 28 #define COMPAT_PTRACE_SETREGS 13 29 #define COMPAT_PTRACE_GET_THREAD_AREA 22 30 #define COMPAT_PTRACE_SET_SYSCALL 23 31 #define COMPAT_PTRACE_GETVFPREGS 27 32 #define COMPAT_PTRACE_SETVFPREGS 28 33 #define COMPAT_PTRACE_GETHBPREGS 29 34 #define COMPAT_PTRACE_SETHBPREGS 30 35 36 /* 37 * PSR bits 38 */ 39 #define PSR_MODE_EL0t 0x00000000 40 #define PSR_MODE_EL1t 0x00000004 41 #define PSR_MODE_EL1h 0x00000005 42 #define PSR_MODE_EL2t 0x00000008 43 #define PSR_MODE_EL2h 0x00000009 44 #define PSR_MODE_EL3t 0x0000000c 45 #define PSR_MODE_EL3h 0x0000000d 46 #define PSR_MODE_MASK 0x0000000f 47 48 /* AArch32 CPSR bits */ 49 #define PSR_MODE32_BIT 0x00000010 50 #define COMPAT_PSR_MODE_USR 0x00000010 51 #define COMPAT_PSR_T_BIT 0x00000020 52 #define COMPAT_PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ 53 54 /* AArch64 SPSR bits */ 55 #define PSR_F_BIT 0x00000040 56 #define PSR_I_BIT 0x00000080 57 #define PSR_A_BIT 0x00000100 58 #define PSR_D_BIT 0x00000200 59 #define PSR_Q_BIT 0x08000000 60 #define PSR_V_BIT 0x10000000 61 #define PSR_C_BIT 0x20000000 62 #define PSR_Z_BIT 0x40000000 63 #define PSR_N_BIT 0x80000000 64 65 /* 66 * Groups of PSR bits 67 */ 68 #define PSR_f 0xff000000 /* Flags */ 69 #define PSR_s 0x00ff0000 /* Status */ 70 #define PSR_x 0x0000ff00 /* Extension */ 71 #define PSR_c 0x000000ff /* Control */ 72 73 /* 74 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a 75 * process is located in memory. 76 */ 77 #define PT_TEXT_ADDR 0x10000 78 #define PT_DATA_ADDR 0x10004 79 #define PT_TEXT_END_ADDR 0x10008 80 81 #ifndef __ASSEMBLY__ 82 83 /* 84 * User structures for general purpose, floating point and debug registers. 85 */ 86 struct user_pt_regs { 87 __u64 regs[31]; 88 __u64 sp; 89 __u64 pc; 90 __u64 pstate; 91 }; 92 93 struct user_fpsimd_state { 94 __uint128_t vregs[32]; 95 __u32 fpsr; 96 __u32 fpcr; 97 }; 98 99 struct user_hwdebug_state { 100 __u32 dbg_info; 101 struct { 102 __u64 addr; 103 __u32 ctrl; 104 } dbg_regs[16]; 105 }; 106 107 #ifdef __KERNEL__ 108 109 /* sizeof(struct user) for AArch32 */ 110 #define COMPAT_USER_SZ 296 111 /* AArch32 uses x13 as the stack pointer... */ 112 #define compat_sp regs[13] 113 /* ... and x14 as the link register. */ 114 #define compat_lr regs[14] 115 116 /* 117 * This struct defines the way the registers are stored on the stack during an 118 * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for 119 * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs. 120 */ 121 struct pt_regs { 122 union { 123 struct user_pt_regs user_regs; 124 struct { 125 u64 regs[31]; 126 u64 sp; 127 u64 pc; 128 u64 pstate; 129 }; 130 }; 131 u64 orig_x0; 132 u64 syscallno; 133 }; 134 135 #define arch_has_single_step() (1) 136 137 #ifdef CONFIG_COMPAT 138 #define compat_thumb_mode(regs) \ 139 (((regs)->pstate & COMPAT_PSR_T_BIT)) 140 #else 141 #define compat_thumb_mode(regs) (0) 142 #endif 143 144 #define user_mode(regs) \ 145 (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t) 146 147 #define compat_user_mode(regs) \ 148 (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \ 149 (PSR_MODE32_BIT | PSR_MODE_EL0t)) 150 151 #define processor_mode(regs) \ 152 ((regs)->pstate & PSR_MODE_MASK) 153 154 #define interrupts_enabled(regs) \ 155 (!((regs)->pstate & PSR_I_BIT)) 156 157 #define fast_interrupts_enabled(regs) \ 158 (!((regs)->pstate & PSR_F_BIT)) 159 160 #define user_stack_pointer(regs) \ 161 ((regs)->sp) 162 163 /* 164 * Are the current registers suitable for user mode? (used to maintain 165 * security in signal handlers) 166 */ 167 static inline int valid_user_regs(struct user_pt_regs *regs) 168 { 169 if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) { 170 regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT); 171 172 /* The T bit is reserved for AArch64 */ 173 if (!(regs->pstate & PSR_MODE32_BIT)) 174 regs->pstate &= ~COMPAT_PSR_T_BIT; 175 176 return 1; 177 } 178 179 /* 180 * Force PSR to something logical... 181 */ 182 regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \ 183 COMPAT_PSR_T_BIT | PSR_MODE32_BIT; 184 185 if (!(regs->pstate & PSR_MODE32_BIT)) { 186 regs->pstate &= ~COMPAT_PSR_T_BIT; 187 regs->pstate |= PSR_MODE_EL0t; 188 } 189 190 return 0; 191 } 192 193 #define instruction_pointer(regs) (regs)->pc 194 195 #ifdef CONFIG_SMP 196 extern unsigned long profile_pc(struct pt_regs *regs); 197 #else 198 #define profile_pc(regs) instruction_pointer(regs) 199 #endif 200 201 extern int aarch32_break_trap(struct pt_regs *regs); 202 203 #endif /* __KERNEL__ */ 204 205 #endif /* __ASSEMBLY__ */ 206 207 #endif 208