xref: /linux/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts (revision 307797159ac25fe5a2048bf5c6a5718298edca57) 
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU106
4 *
5 * (C) Copyright 2016, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16
17/ {
18	model = "ZynqMP ZCU106 RevA";
19	compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
20
21	aliases {
22		ethernet0 = &gem3;
23		i2c0 = &i2c0;
24		i2c1 = &i2c1;
25		mmc0 = &sdhci1;
26		rtc0 = &rtc;
27		serial0 = &uart0;
28		serial1 = &uart1;
29		serial2 = &dcc;
30	};
31
32	chosen {
33		bootargs = "earlycon";
34		stdout-path = "serial0:115200n8";
35	};
36
37	memory@0 {
38		device_type = "memory";
39		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44		#address-cells = <1>;
45		#size-cells = <0>;
46		autorepeat;
47		sw19 {
48			label = "sw19";
49			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
50			linux,code = <KEY_DOWN>;
51			gpio-key,wakeup;
52			autorepeat;
53		};
54	};
55
56	leds {
57		compatible = "gpio-leds";
58		heartbeat_led {
59			label = "heartbeat";
60			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
61			linux,default-trigger = "heartbeat";
62		};
63	};
64};
65
66&can1 {
67	status = "okay";
68};
69
70&dcc {
71	status = "okay";
72};
73
74/* fpd_dma clk 667MHz, lpd_dma 500MHz */
75&fpd_dma_chan1 {
76	status = "okay";
77};
78
79&fpd_dma_chan2 {
80	status = "okay";
81};
82
83&fpd_dma_chan3 {
84	status = "okay";
85};
86
87&fpd_dma_chan4 {
88	status = "okay";
89};
90
91&fpd_dma_chan5 {
92	status = "okay";
93};
94
95&fpd_dma_chan6 {
96	status = "okay";
97};
98
99&fpd_dma_chan7 {
100	status = "okay";
101};
102
103&fpd_dma_chan8 {
104	status = "okay";
105};
106
107&gem3 {
108	status = "okay";
109	phy-handle = <&phy0>;
110	phy-mode = "rgmii-id";
111	phy0: phy@c {
112		reg = <0xc>;
113		ti,rx-internal-delay = <0x8>;
114		ti,tx-internal-delay = <0xa>;
115		ti,fifo-depth = <0x1>;
116	};
117};
118
119&gpio {
120	status = "okay";
121};
122
123&i2c0 {
124	status = "okay";
125	clock-frequency = <400000>;
126
127	tca6416_u97: gpio@20 {
128		compatible = "ti,tca6416";
129		reg = <0x20>;
130		gpio-controller; /* interrupt not connected */
131		#gpio-cells = <2>;
132		/*
133		 * IRQ not connected
134		 * Lines:
135		 * 0 - SFP_SI5328_INT_ALM
136		 * 1 - HDMI_SI5328_INT_ALM
137		 * 5 - IIC_MUX_RESET_B
138		 * 6 - GEM3_EXP_RESET_B
139		 * 10 - FMC_HPC0_PRSNT_M2C_B
140		 * 11 - FMC_HPC1_PRSNT_M2C_B
141		 * 2-4, 7, 12-17 - not connected
142		 */
143	};
144
145	tca6416_u61: gpio@21 {
146		compatible = "ti,tca6416";
147		reg = <0x21>;
148		gpio-controller;
149		#gpio-cells = <2>;
150		/*
151		 * IRQ not connected
152		 * Lines:
153		 * 0 - VCCPSPLL_EN
154		 * 1 - MGTRAVCC_EN
155		 * 2 - MGTRAVTT_EN
156		 * 3 - VCCPSDDRPLL_EN
157		 * 4 - MIO26_PMU_INPUT_LS
158		 * 5 - PL_PMBUS_ALERT
159		 * 6 - PS_PMBUS_ALERT
160		 * 7 - MAXIM_PMBUS_ALERT
161		 * 10 - PL_DDR4_VTERM_EN
162		 * 11 - PL_DDR4_VPP_2V5_EN
163		 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
164		 * 13 - PS_DIMM_SUSPEND_EN
165		 * 14 - PS_DDR4_VTERM_EN
166		 * 15 - PS_DDR4_VPP_2V5_EN
167		 * 16 - 17 - not connected
168		 */
169	};
170
171	i2c-mux@75 { /* u60 */
172		compatible = "nxp,pca9544";
173		#address-cells = <1>;
174		#size-cells = <0>;
175		reg = <0x75>;
176		i2c@0 {
177			#address-cells = <1>;
178			#size-cells = <0>;
179			reg = <0>;
180			/* PS_PMBUS */
181			ina226@40 { /* u76 */
182				compatible = "ti,ina226";
183				reg = <0x40>;
184				shunt-resistor = <5000>;
185			};
186			ina226@41 { /* u77 */
187				compatible = "ti,ina226";
188				reg = <0x41>;
189				shunt-resistor = <5000>;
190			};
191			ina226@42 { /* u78 */
192				compatible = "ti,ina226";
193				reg = <0x42>;
194				shunt-resistor = <5000>;
195			};
196			ina226@43 { /* u87 */
197				compatible = "ti,ina226";
198				reg = <0x43>;
199				shunt-resistor = <5000>;
200			};
201			ina226@44 { /* u85 */
202				compatible = "ti,ina226";
203				reg = <0x44>;
204				shunt-resistor = <5000>;
205			};
206			ina226@45 { /* u86 */
207				compatible = "ti,ina226";
208				reg = <0x45>;
209				shunt-resistor = <5000>;
210			};
211			ina226@46 { /* u93 */
212				compatible = "ti,ina226";
213				reg = <0x46>;
214				shunt-resistor = <5000>;
215			};
216			ina226@47 { /* u88 */
217				compatible = "ti,ina226";
218				reg = <0x47>;
219				shunt-resistor = <5000>;
220			};
221			ina226@4a { /* u15 */
222				compatible = "ti,ina226";
223				reg = <0x4a>;
224				shunt-resistor = <5000>;
225			};
226			ina226@4b { /* u92 */
227				compatible = "ti,ina226";
228				reg = <0x4b>;
229				shunt-resistor = <5000>;
230			};
231		};
232		i2c@1 {
233			#address-cells = <1>;
234			#size-cells = <0>;
235			reg = <1>;
236			/* PL_PMBUS */
237			ina226@40 { /* u79 */
238				compatible = "ti,ina226";
239				reg = <0x40>;
240				shunt-resistor = <2000>;
241			};
242			ina226@41 { /* u81 */
243				compatible = "ti,ina226";
244				reg = <0x41>;
245				shunt-resistor = <5000>;
246			};
247			ina226@42 { /* u80 */
248				compatible = "ti,ina226";
249				reg = <0x42>;
250				shunt-resistor = <5000>;
251			};
252			ina226@43 { /* u84 */
253				compatible = "ti,ina226";
254				reg = <0x43>;
255				shunt-resistor = <5000>;
256			};
257			ina226@44 { /* u16 */
258				compatible = "ti,ina226";
259				reg = <0x44>;
260				shunt-resistor = <5000>;
261			};
262			ina226@45 { /* u65 */
263				compatible = "ti,ina226";
264				reg = <0x45>;
265				shunt-resistor = <5000>;
266			};
267			ina226@46 { /* u74 */
268				compatible = "ti,ina226";
269				reg = <0x46>;
270				shunt-resistor = <5000>;
271			};
272			ina226@47 { /* u75 */
273				compatible = "ti,ina226";
274				reg = <0x47>;
275				shunt-resistor = <5000>;
276			};
277		};
278		i2c@2 {
279			#address-cells = <1>;
280			#size-cells = <0>;
281			reg = <2>;
282			/* MAXIM_PMBUS - 00 */
283			max15301@a { /* u46 */
284				compatible = "maxim,max15301";
285				reg = <0xa>;
286			};
287			max15303@b { /* u4 */
288				compatible = "maxim,max15303";
289				reg = <0xb>;
290			};
291			max15303@10 { /* u13 */
292				compatible = "maxim,max15303";
293				reg = <0x10>;
294			};
295			max15301@13 { /* u47 */
296				compatible = "maxim,max15301";
297				reg = <0x13>;
298			};
299			max15303@14 { /* u7 */
300				compatible = "maxim,max15303";
301				reg = <0x14>;
302			};
303			max15303@15 { /* u6 */
304				compatible = "maxim,max15303";
305				reg = <0x15>;
306			};
307			max15303@16 { /* u10 */
308				compatible = "maxim,max15303";
309				reg = <0x16>;
310			};
311			max15303@17 { /* u9 */
312				compatible = "maxim,max15303";
313				reg = <0x17>;
314			};
315			max15301@18 { /* u63 */
316				compatible = "maxim,max15301";
317				reg = <0x18>;
318			};
319			max15303@1a { /* u49 */
320				compatible = "maxim,max15303";
321				reg = <0x1a>;
322			};
323			max15303@1b { /* u8 */
324				compatible = "maxim,max15303";
325				reg = <0x1b>;
326			};
327			max15303@1d { /* u18 */
328				compatible = "maxim,max15303";
329				reg = <0x1d>;
330			};
331
332			max20751@72 { /* u95 */
333				compatible = "maxim,max20751";
334				reg = <0x72>;
335			};
336			max20751@73 { /* u96 */
337				compatible = "maxim,max20751";
338				reg = <0x73>;
339			};
340		};
341		/* Bus 3 is not connected */
342	};
343};
344
345&i2c1 {
346	status = "okay";
347	clock-frequency = <400000>;
348
349	/* PL i2c via PCA9306 - u45 */
350	i2c-mux@74 { /* u34 */
351		compatible = "nxp,pca9548";
352		#address-cells = <1>;
353		#size-cells = <0>;
354		reg = <0x74>;
355		i2c@0 {
356			#address-cells = <1>;
357			#size-cells = <0>;
358			reg = <0>;
359			/*
360			 * IIC_EEPROM 1kB memory which uses 256B blocks
361			 * where every block has different address.
362			 *    0 - 256B address 0x54
363			 * 256B - 512B address 0x55
364			 * 512B - 768B address 0x56
365			 * 768B - 1024B address 0x57
366			 */
367			eeprom: eeprom@54 { /* u23 */
368				compatible = "atmel,24c08";
369				reg = <0x54>;
370			};
371		};
372		i2c@1 {
373			#address-cells = <1>;
374			#size-cells = <0>;
375			reg = <1>;
376			si5341: clock-generator@36 { /* SI5341 - u69 */
377				reg = <0x36>;
378			};
379
380		};
381		i2c@2 {
382			#address-cells = <1>;
383			#size-cells = <0>;
384			reg = <2>;
385			si570_1: clock-generator@5d { /* USER SI570 - u42 */
386				#clock-cells = <0>;
387				compatible = "silabs,si570";
388				reg = <0x5d>;
389				temperature-stability = <50>;
390				factory-fout = <300000000>;
391				clock-frequency = <300000000>;
392			};
393		};
394		i2c@3 {
395			#address-cells = <1>;
396			#size-cells = <0>;
397			reg = <3>;
398			si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
399				#clock-cells = <0>;
400				compatible = "silabs,si570";
401				reg = <0x5d>;
402				temperature-stability = <50>; /* copy from zc702 */
403				factory-fout = <156250000>;
404				clock-frequency = <148500000>;
405			};
406		};
407		i2c@4 {
408			#address-cells = <1>;
409			#size-cells = <0>;
410			reg = <4>;
411			si5328: clock-generator@69 {/* SI5328 - u20 */
412				reg = <0x69>;
413			};
414		};
415		i2c@5 {
416			#address-cells = <1>;
417			#size-cells = <0>;
418			reg = <5>; /* FAN controller */
419			temp@4c {/* lm96163 - u128 */
420				compatible = "national,lm96163";
421				reg = <0x4c>;
422			};
423		};
424		/* 6 - 7 unconnected */
425	};
426
427	i2c-mux@75 {
428		compatible = "nxp,pca9548"; /* u135 */
429		#address-cells = <1>;
430		#size-cells = <0>;
431		reg = <0x75>;
432
433		i2c@0 {
434			#address-cells = <1>;
435			#size-cells = <0>;
436			reg = <0>;
437			/* HPC0_IIC */
438		};
439		i2c@1 {
440			#address-cells = <1>;
441			#size-cells = <0>;
442			reg = <1>;
443			/* HPC1_IIC */
444		};
445		i2c@2 {
446			#address-cells = <1>;
447			#size-cells = <0>;
448			reg = <2>;
449			/* SYSMON */
450		};
451		i2c@3 {
452			#address-cells = <1>;
453			#size-cells = <0>;
454			reg = <3>;
455			/* DDR4 SODIMM */
456		};
457		i2c@4 {
458			#address-cells = <1>;
459			#size-cells = <0>;
460			reg = <4>;
461			/* SEP 3 */
462		};
463		i2c@5 {
464			#address-cells = <1>;
465			#size-cells = <0>;
466			reg = <5>;
467			/* SEP 2 */
468		};
469		i2c@6 {
470			#address-cells = <1>;
471			#size-cells = <0>;
472			reg = <6>;
473			/* SEP 1 */
474		};
475		i2c@7 {
476			#address-cells = <1>;
477			#size-cells = <0>;
478			reg = <7>;
479			/* SEP 0 */
480		};
481	};
482};
483
484&rtc {
485	status = "okay";
486};
487
488&sata {
489	status = "okay";
490	/* SATA OOB timing settings */
491	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
492	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
493	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
494	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
495	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
496	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
497	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
498	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
499};
500
501/* SD1 with level shifter */
502&sdhci1 {
503	status = "okay";
504	no-1-8-v;
505};
506
507&uart0 {
508	status = "okay";
509};
510
511&uart1 {
512	status = "okay";
513};
514
515/* ULPI SMSC USB3320 */
516&usb0 {
517	status = "okay";
518};
519
520&watchdog0 {
521	status = "okay";
522};
523