1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x0 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clock-controller { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 mcu_conf: syscon@40f00000 { 38 compatible = "syscon", "simple-mfd"; 39 reg = <0x0 0x40f00000 0x0 0x20000>; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges = <0x0 0x0 0x40f00000 0x20000>; 43 44 phy_gmii_sel: phy@4040 { 45 compatible = "ti,am654-phy-gmii-sel"; 46 reg = <0x4040 0x4>; 47 #phy-cells = <1>; 48 }; 49 }; 50 51 chipid@43000014 { 52 compatible = "ti,am654-chipid"; 53 reg = <0x0 0x43000014 0x0 0x4>; 54 }; 55 56 wkup_pmx0: pinctrl@4301c000 { 57 compatible = "pinctrl-single"; 58 /* Proxy 0 addressing */ 59 reg = <0x00 0x4301c000 0x00 0x178>; 60 #pinctrl-cells = <1>; 61 pinctrl-single,register-width = <32>; 62 pinctrl-single,function-mask = <0xffffffff>; 63 }; 64 65 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 66 mcu_timerio_input: pinctrl@40f04200 { 67 compatible = "pinctrl-single"; 68 reg = <0x00 0x40f04200 0x00 0x28>; 69 #pinctrl-cells = <1>; 70 pinctrl-single,register-width = <32>; 71 pinctrl-single,function-mask = <0x0000000f>; 72 /* Non-MPU Firmware usage */ 73 status = "reserved"; 74 }; 75 76 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 77 mcu_timerio_output: pinctrl@40f04280 { 78 compatible = "pinctrl-single"; 79 reg = <0x00 0x40f04280 0x00 0x28>; 80 #pinctrl-cells = <1>; 81 pinctrl-single,register-width = <32>; 82 pinctrl-single,function-mask = <0x0000000f>; 83 /* Non-MPU Firmware usage */ 84 status = "reserved"; 85 }; 86 87 mcu_ram: sram@41c00000 { 88 compatible = "mmio-sram"; 89 reg = <0x00 0x41c00000 0x00 0x100000>; 90 ranges = <0x0 0x00 0x41c00000 0x100000>; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 }; 94 95 mcu_timer0: timer@40400000 { 96 compatible = "ti,am654-timer"; 97 reg = <0x00 0x40400000 0x00 0x400>; 98 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 99 clocks = <&k3_clks 35 1>; 100 clock-names = "fck"; 101 assigned-clocks = <&k3_clks 35 1>; 102 assigned-clock-parents = <&k3_clks 35 2>; 103 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 104 ti,timer-pwm; 105 /* Non-MPU Firmware usage */ 106 status = "reserved"; 107 }; 108 109 mcu_timer1: timer@40410000 { 110 compatible = "ti,am654-timer"; 111 reg = <0x00 0x40410000 0x00 0x400>; 112 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 113 clocks = <&k3_clks 71 1>; 114 clock-names = "fck"; 115 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>; 116 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>; 117 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 118 ti,timer-pwm; 119 /* Non-MPU Firmware usage */ 120 status = "reserved"; 121 }; 122 123 mcu_timer2: timer@40420000 { 124 compatible = "ti,am654-timer"; 125 reg = <0x00 0x40420000 0x00 0x400>; 126 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 127 clocks = <&k3_clks 72 1>; 128 clock-names = "fck"; 129 assigned-clocks = <&k3_clks 72 1>; 130 assigned-clock-parents = <&k3_clks 72 2>; 131 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 132 ti,timer-pwm; 133 /* Non-MPU Firmware usage */ 134 status = "reserved"; 135 }; 136 137 mcu_timer3: timer@40430000 { 138 compatible = "ti,am654-timer"; 139 reg = <0x00 0x40430000 0x00 0x400>; 140 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&k3_clks 73 1>; 142 clock-names = "fck"; 143 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>; 144 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>; 145 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 146 ti,timer-pwm; 147 /* Non-MPU Firmware usage */ 148 status = "reserved"; 149 }; 150 151 mcu_timer4: timer@40440000 { 152 compatible = "ti,am654-timer"; 153 reg = <0x00 0x40440000 0x00 0x400>; 154 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&k3_clks 74 1>; 156 clock-names = "fck"; 157 assigned-clocks = <&k3_clks 74 1>; 158 assigned-clock-parents = <&k3_clks 74 2>; 159 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 160 ti,timer-pwm; 161 /* Non-MPU Firmware usage */ 162 status = "reserved"; 163 }; 164 165 mcu_timer5: timer@40450000 { 166 compatible = "ti,am654-timer"; 167 reg = <0x00 0x40450000 0x00 0x400>; 168 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&k3_clks 75 1>; 170 clock-names = "fck"; 171 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>; 172 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>; 173 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 174 ti,timer-pwm; 175 /* Non-MPU Firmware usage */ 176 status = "reserved"; 177 }; 178 179 mcu_timer6: timer@40460000 { 180 compatible = "ti,am654-timer"; 181 reg = <0x00 0x40460000 0x00 0x400>; 182 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&k3_clks 76 1>; 184 clock-names = "fck"; 185 assigned-clocks = <&k3_clks 76 1>; 186 assigned-clock-parents = <&k3_clks 76 2>; 187 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; 188 ti,timer-pwm; 189 /* Non-MPU Firmware usage */ 190 status = "reserved"; 191 }; 192 193 mcu_timer7: timer@40470000 { 194 compatible = "ti,am654-timer"; 195 reg = <0x00 0x40470000 0x00 0x400>; 196 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&k3_clks 77 1>; 198 clock-names = "fck"; 199 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>; 200 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>; 201 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 202 ti,timer-pwm; 203 /* Non-MPU Firmware usage */ 204 status = "reserved"; 205 }; 206 207 mcu_timer8: timer@40480000 { 208 compatible = "ti,am654-timer"; 209 reg = <0x00 0x40480000 0x00 0x400>; 210 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&k3_clks 78 1>; 212 clock-names = "fck"; 213 assigned-clocks = <&k3_clks 78 1>; 214 assigned-clock-parents = <&k3_clks 78 2>; 215 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 216 ti,timer-pwm; 217 /* Non-MPU Firmware usage */ 218 status = "reserved"; 219 }; 220 221 mcu_timer9: timer@40490000 { 222 compatible = "ti,am654-timer"; 223 reg = <0x00 0x40490000 0x00 0x400>; 224 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&k3_clks 79 1>; 226 clock-names = "fck"; 227 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>; 228 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>; 229 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 230 ti,timer-pwm; 231 /* Non-MPU Firmware usage */ 232 status = "reserved"; 233 }; 234 wkup_uart0: serial@42300000 { 235 compatible = "ti,j721e-uart", "ti,am654-uart"; 236 reg = <0x00 0x42300000 0x00 0x100>; 237 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 238 clock-frequency = <48000000>; 239 current-speed = <115200>; 240 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 241 clocks = <&k3_clks 287 0>; 242 clock-names = "fclk"; 243 status = "disabled"; 244 }; 245 246 mcu_uart0: serial@40a00000 { 247 compatible = "ti,j721e-uart", "ti,am654-uart"; 248 reg = <0x00 0x40a00000 0x00 0x100>; 249 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 250 clock-frequency = <96000000>; 251 current-speed = <115200>; 252 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 253 clocks = <&k3_clks 149 0>; 254 clock-names = "fclk"; 255 status = "disabled"; 256 }; 257 258 wkup_gpio_intr: interrupt-controller@42200000 { 259 compatible = "ti,sci-intr"; 260 reg = <0x00 0x42200000 0x00 0x400>; 261 ti,intr-trigger-type = <1>; 262 interrupt-controller; 263 interrupt-parent = <&gic500>; 264 #interrupt-cells = <1>; 265 ti,sci = <&dmsc>; 266 ti,sci-dev-id = <137>; 267 ti,interrupt-ranges = <16 960 16>; 268 }; 269 270 wkup_gpio0: gpio@42110000 { 271 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 272 reg = <0x0 0x42110000 0x0 0x100>; 273 gpio-controller; 274 #gpio-cells = <2>; 275 interrupt-parent = <&wkup_gpio_intr>; 276 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 277 interrupt-controller; 278 #interrupt-cells = <2>; 279 ti,ngpio = <84>; 280 ti,davinci-gpio-unbanked = <0>; 281 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 282 clocks = <&k3_clks 113 0>; 283 clock-names = "gpio"; 284 status = "disabled"; 285 }; 286 287 wkup_gpio1: gpio@42100000 { 288 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 289 reg = <0x0 0x42100000 0x0 0x100>; 290 gpio-controller; 291 #gpio-cells = <2>; 292 interrupt-parent = <&wkup_gpio_intr>; 293 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 294 interrupt-controller; 295 #interrupt-cells = <2>; 296 ti,ngpio = <84>; 297 ti,davinci-gpio-unbanked = <0>; 298 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 299 clocks = <&k3_clks 114 0>; 300 clock-names = "gpio"; 301 status = "disabled"; 302 }; 303 304 mcu_i2c0: i2c@40b00000 { 305 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 306 reg = <0x0 0x40b00000 0x0 0x100>; 307 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 clock-names = "fck"; 311 clocks = <&k3_clks 194 0>; 312 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 313 status = "disabled"; 314 }; 315 316 mcu_i2c1: i2c@40b10000 { 317 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 318 reg = <0x0 0x40b10000 0x0 0x100>; 319 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 clock-names = "fck"; 323 clocks = <&k3_clks 195 0>; 324 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 325 status = "disabled"; 326 }; 327 328 wkup_i2c0: i2c@42120000 { 329 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 330 reg = <0x0 0x42120000 0x0 0x100>; 331 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 clock-names = "fck"; 335 clocks = <&k3_clks 197 0>; 336 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 337 status = "disabled"; 338 }; 339 340 fss: bus@47000000 { 341 compatible = "simple-bus"; 342 reg = <0x0 0x47000000 0x0 0x100>; 343 #address-cells = <2>; 344 #size-cells = <2>; 345 ranges; 346 347 hbmc_mux: mux-controller@47000004 { 348 compatible = "reg-mux"; 349 reg = <0x00 0x47000004 0x00 0x2>; 350 #mux-control-cells = <1>; 351 mux-reg-masks = <0x4 0x2>; /* HBMC select */ 352 }; 353 354 hbmc: hyperbus@47034000 { 355 compatible = "ti,am654-hbmc"; 356 reg = <0x00 0x47034000 0x00 0x100>, 357 <0x05 0x00000000 0x01 0x0000000>; 358 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 359 clocks = <&k3_clks 102 0>; 360 assigned-clocks = <&k3_clks 102 5>; 361 assigned-clock-rates = <333333333>; 362 #address-cells = <2>; 363 #size-cells = <1>; 364 mux-controls = <&hbmc_mux 0>; 365 status = "disabled"; 366 }; 367 368 ospi0: spi@47040000 { 369 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 370 reg = <0x0 0x47040000 0x0 0x100>, 371 <0x5 0x00000000 0x1 0x0000000>; 372 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 373 cdns,fifo-depth = <256>; 374 cdns,fifo-width = <4>; 375 cdns,trigger-address = <0x0>; 376 clocks = <&k3_clks 103 0>; 377 assigned-clocks = <&k3_clks 103 0>; 378 assigned-clock-parents = <&k3_clks 103 2>; 379 assigned-clock-rates = <166666666>; 380 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 status = "disabled"; 384 }; 385 386 ospi1: spi@47050000 { 387 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 388 reg = <0x0 0x47050000 0x0 0x100>, 389 <0x7 0x00000000 0x1 0x00000000>; 390 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 391 cdns,fifo-depth = <256>; 392 cdns,fifo-width = <4>; 393 cdns,trigger-address = <0x0>; 394 clocks = <&k3_clks 104 0>; 395 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 status = "disabled"; 399 }; 400 }; 401 402 tscadc0: tscadc@40200000 { 403 compatible = "ti,am3359-tscadc"; 404 reg = <0x0 0x40200000 0x0 0x1000>; 405 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 406 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 407 clocks = <&k3_clks 0 1>; 408 assigned-clocks = <&k3_clks 0 3>; 409 assigned-clock-rates = <60000000>; 410 clock-names = "fck"; 411 dmas = <&main_udmap 0x7400>, 412 <&main_udmap 0x7401>; 413 dma-names = "fifo0", "fifo1"; 414 status = "disabled"; 415 416 adc { 417 #io-channel-cells = <1>; 418 compatible = "ti,am3359-adc"; 419 }; 420 }; 421 422 tscadc1: tscadc@40210000 { 423 compatible = "ti,am3359-tscadc"; 424 reg = <0x0 0x40210000 0x0 0x1000>; 425 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 426 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 427 clocks = <&k3_clks 1 1>; 428 assigned-clocks = <&k3_clks 1 3>; 429 assigned-clock-rates = <60000000>; 430 clock-names = "fck"; 431 dmas = <&main_udmap 0x7402>, 432 <&main_udmap 0x7403>; 433 dma-names = "fifo0", "fifo1"; 434 status = "disabled"; 435 436 adc { 437 #io-channel-cells = <1>; 438 compatible = "ti,am3359-adc"; 439 }; 440 }; 441 442 mcu_navss: bus@28380000 { 443 compatible = "simple-bus"; 444 #address-cells = <2>; 445 #size-cells = <2>; 446 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 447 dma-coherent; 448 dma-ranges; 449 450 ti,sci-dev-id = <232>; 451 452 mcu_ringacc: ringacc@2b800000 { 453 compatible = "ti,am654-navss-ringacc"; 454 reg = <0x0 0x2b800000 0x0 0x400000>, 455 <0x0 0x2b000000 0x0 0x400000>, 456 <0x0 0x28590000 0x0 0x100>, 457 <0x0 0x2a500000 0x0 0x40000>, 458 <0x0 0x28440000 0x0 0x40000>; 459 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 460 ti,num-rings = <286>; 461 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 462 ti,sci = <&dmsc>; 463 ti,sci-dev-id = <235>; 464 msi-parent = <&main_udmass_inta>; 465 }; 466 467 mcu_udmap: dma-controller@285c0000 { 468 compatible = "ti,j721e-navss-mcu-udmap"; 469 reg = <0x0 0x285c0000 0x0 0x100>, 470 <0x0 0x2a800000 0x0 0x40000>, 471 <0x0 0x2aa00000 0x0 0x40000>; 472 reg-names = "gcfg", "rchanrt", "tchanrt"; 473 msi-parent = <&main_udmass_inta>; 474 #dma-cells = <1>; 475 476 ti,sci = <&dmsc>; 477 ti,sci-dev-id = <236>; 478 ti,ringacc = <&mcu_ringacc>; 479 480 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 481 <0x0f>; /* TX_HCHAN */ 482 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 483 <0x0b>; /* RX_HCHAN */ 484 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 485 }; 486 }; 487 488 secure_proxy_mcu: mailbox@2a480000 { 489 compatible = "ti,am654-secure-proxy"; 490 #mbox-cells = <1>; 491 reg-names = "target_data", "rt", "scfg"; 492 reg = <0x0 0x2a480000 0x0 0x80000>, 493 <0x0 0x2a380000 0x0 0x80000>, 494 <0x0 0x2a400000 0x0 0x80000>; 495 /* 496 * Marked Disabled: 497 * Node is incomplete as it is meant for bootloaders and 498 * firmware on non-MPU processors 499 */ 500 status = "disabled"; 501 }; 502 503 mcu_cpsw: ethernet@46000000 { 504 compatible = "ti,j721e-cpsw-nuss"; 505 #address-cells = <2>; 506 #size-cells = <2>; 507 reg = <0x0 0x46000000 0x0 0x200000>; 508 reg-names = "cpsw_nuss"; 509 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 510 dma-coherent; 511 clocks = <&k3_clks 18 22>; 512 clock-names = "fck"; 513 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 514 515 dmas = <&mcu_udmap 0xf000>, 516 <&mcu_udmap 0xf001>, 517 <&mcu_udmap 0xf002>, 518 <&mcu_udmap 0xf003>, 519 <&mcu_udmap 0xf004>, 520 <&mcu_udmap 0xf005>, 521 <&mcu_udmap 0xf006>, 522 <&mcu_udmap 0xf007>, 523 <&mcu_udmap 0x7000>; 524 dma-names = "tx0", "tx1", "tx2", "tx3", 525 "tx4", "tx5", "tx6", "tx7", 526 "rx"; 527 528 ethernet-ports { 529 #address-cells = <1>; 530 #size-cells = <0>; 531 532 cpsw_port1: port@1 { 533 reg = <1>; 534 ti,mac-only; 535 label = "port1"; 536 ti,syscon-efuse = <&mcu_conf 0x200>; 537 phys = <&phy_gmii_sel 1>; 538 }; 539 }; 540 541 davinci_mdio: mdio@f00 { 542 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 543 reg = <0x0 0xf00 0x0 0x100>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 clocks = <&k3_clks 18 22>; 547 clock-names = "fck"; 548 bus_freq = <1000000>; 549 }; 550 551 cpts@3d000 { 552 compatible = "ti,am65-cpts"; 553 reg = <0x0 0x3d000 0x0 0x400>; 554 clocks = <&k3_clks 18 2>; 555 clock-names = "cpts"; 556 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 557 interrupt-names = "cpts"; 558 ti,cpts-ext-ts-inputs = <4>; 559 ti,cpts-periodic-outputs = <2>; 560 }; 561 }; 562 563 mcu_r5fss0: r5fss@41000000 { 564 compatible = "ti,j721e-r5fss"; 565 ti,cluster-mode = <1>; 566 #address-cells = <1>; 567 #size-cells = <1>; 568 ranges = <0x41000000 0x00 0x41000000 0x20000>, 569 <0x41400000 0x00 0x41400000 0x20000>; 570 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 571 572 mcu_r5fss0_core0: r5f@41000000 { 573 compatible = "ti,j721e-r5f"; 574 reg = <0x41000000 0x00008000>, 575 <0x41010000 0x00008000>; 576 reg-names = "atcm", "btcm"; 577 ti,sci = <&dmsc>; 578 ti,sci-dev-id = <250>; 579 ti,sci-proc-ids = <0x01 0xff>; 580 resets = <&k3_reset 250 1>; 581 firmware-name = "j7-mcu-r5f0_0-fw"; 582 ti,atcm-enable = <1>; 583 ti,btcm-enable = <1>; 584 ti,loczrama = <1>; 585 }; 586 587 mcu_r5fss0_core1: r5f@41400000 { 588 compatible = "ti,j721e-r5f"; 589 reg = <0x41400000 0x00008000>, 590 <0x41410000 0x00008000>; 591 reg-names = "atcm", "btcm"; 592 ti,sci = <&dmsc>; 593 ti,sci-dev-id = <251>; 594 ti,sci-proc-ids = <0x02 0xff>; 595 resets = <&k3_reset 251 1>; 596 firmware-name = "j7-mcu-r5f0_1-fw"; 597 ti,atcm-enable = <1>; 598 ti,btcm-enable = <1>; 599 ti,loczrama = <1>; 600 }; 601 }; 602 603 mcu_mcan0: can@40528000 { 604 compatible = "bosch,m_can"; 605 reg = <0x00 0x40528000 0x00 0x200>, 606 <0x00 0x40500000 0x00 0x8000>; 607 reg-names = "m_can", "message_ram"; 608 power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; 609 clocks = <&k3_clks 172 0>, <&k3_clks 172 1>; 610 clock-names = "hclk", "cclk"; 611 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 613 interrupt-names = "int0", "int1"; 614 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 615 status = "disabled"; 616 }; 617 618 mcu_mcan1: can@40568000 { 619 compatible = "bosch,m_can"; 620 reg = <0x00 0x40568000 0x00 0x200>, 621 <0x00 0x40540000 0x00 0x8000>; 622 reg-names = "m_can", "message_ram"; 623 power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; 624 clocks = <&k3_clks 173 0>, <&k3_clks 173 1>; 625 clock-names = "hclk", "cclk"; 626 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 628 interrupt-names = "int0", "int1"; 629 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 630 status = "disabled"; 631 }; 632 633 mcu_spi0: spi@40300000 { 634 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 635 reg = <0x00 0x040300000 0x00 0x400>; 636 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 640 clocks = <&k3_clks 274 0>; 641 status = "disabled"; 642 }; 643 644 mcu_spi1: spi@40310000 { 645 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 646 reg = <0x00 0x040310000 0x00 0x400>; 647 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 648 #address-cells = <1>; 649 #size-cells = <0>; 650 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 651 clocks = <&k3_clks 275 0>; 652 status = "disabled"; 653 }; 654 655 mcu_spi2: spi@40320000 { 656 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 657 reg = <0x00 0x040320000 0x00 0x400>; 658 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 662 clocks = <&k3_clks 276 0>; 663 status = "disabled"; 664 }; 665 666 wkup_vtm0: temperature-sensor@42040000 { 667 compatible = "ti,j721e-vtm"; 668 reg = <0x00 0x42040000 0x00 0x350>, 669 <0x00 0x42050000 0x00 0x350>, 670 <0x00 0x43000300 0x00 0x10>; 671 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 672 #thermal-sensor-cells = <1>; 673 }; 674 675 mcu_esm: esm@40800000 { 676 compatible = "ti,j721e-esm"; 677 reg = <0x00 0x40800000 0x00 0x1000>; 678 ti,esm-pins = <95>; 679 bootph-pre-ram; 680 }; 681}; 682