1/* 2 * Spreadtrum SC9836 SoC DTS file 3 * 4 * Copyright (C) 2014, Spreadtrum Communications Inc. 5 * 6 * This file is licensed under a dual GPLv2 or X11 license. 7 */ 8 9#include "sharkl64.dtsi" 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 compatible = "sprd,sc9836"; 14 15 cpus { 16 #address-cells = <2>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a53", "arm,armv8"; 22 reg = <0x0 0x0>; 23 enable-method = "psci"; 24 }; 25 26 cpu@1 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a53", "arm,armv8"; 29 reg = <0x0 0x1>; 30 enable-method = "psci"; 31 }; 32 33 cpu@2 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53", "arm,armv8"; 36 reg = <0x0 0x2>; 37 enable-method = "psci"; 38 }; 39 40 cpu@3 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53", "arm,armv8"; 43 reg = <0x0 0x3>; 44 enable-method = "psci"; 45 }; 46 }; 47 48 etf@10003000 { 49 compatible = "arm,coresight-tmc", "arm,primecell"; 50 reg = <0 0x10003000 0 0x1000>; 51 clocks = <&clk26mhz>; 52 clock-names = "apb_pclk"; 53 port { 54 etf_in: endpoint { 55 slave-mode; 56 remote-endpoint = <&funnel_out_port0>; 57 }; 58 }; 59 }; 60 61 funnel@10001000 { 62 compatible = "arm,coresight-funnel", "arm,primecell"; 63 reg = <0 0x10001000 0 0x1000>; 64 clocks = <&clk26mhz>; 65 clock-names = "apb_pclk"; 66 ports { 67 #address-cells = <1>; 68 #size-cells = <0>; 69 70 /* funnel output port */ 71 port@0 { 72 reg = <0>; 73 funnel_out_port0: endpoint { 74 remote-endpoint = <&etf_in>; 75 }; 76 }; 77 78 /* funnel input port 0~3 is reserved for ETMs */ 79 port@1 { 80 reg = <4>; 81 funnel_in_port4: endpoint { 82 slave-mode; 83 remote-endpoint = <&stm_out>; 84 }; 85 }; 86 }; 87 }; 88 89 stm@10006000 { 90 compatible = "arm,coresight-stm", "arm,primecell"; 91 reg = <0 0x10006000 0 0x1000>, 92 <0 0x01000000 0 0x180000>; 93 reg-names = "stm-base", "stm-stimulus-base"; 94 clocks = <&clk26mhz>; 95 clock-names = "apb_pclk"; 96 port { 97 stm_out: endpoint { 98 remote-endpoint = <&funnel_in_port4>; 99 }; 100 }; 101 }; 102 103 gic: interrupt-controller@12001000 { 104 compatible = "arm,gic-400"; 105 reg = <0 0x12001000 0 0x1000>, 106 <0 0x12002000 0 0x2000>, 107 <0 0x12004000 0 0x2000>, 108 <0 0x12006000 0 0x2000>; 109 #interrupt-cells = <3>; 110 interrupt-controller; 111 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 112 }; 113 114 psci { 115 compatible = "arm,psci"; 116 method = "smc"; 117 cpu_on = <0xc4000003>; 118 cpu_off = <0x84000002>; 119 cpu_suspend = <0xc4000001>; 120 }; 121 122 timer { 123 compatible = "arm,armv8-timer"; 124 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 125 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 126 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 128 }; 129}; 130