1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Gru-scarlet board device tree source 4 * 5 * Copyright 2018 Google, Inc 6 */ 7 8#include "rk3399-gru.dtsi" 9 10/{ 11 chassis-type = "tablet"; 12 13 /* Power tree */ 14 15 /* ppvar_sys children, sorted by name */ 16 pp1250_s3: pp1250-s3 { 17 compatible = "regulator-fixed"; 18 regulator-name = "pp1250_s3"; 19 20 /* EC turns on w/ pp1250_s3_en; always on for AP */ 21 regulator-always-on; 22 regulator-boot-on; 23 regulator-min-microvolt = <1250000>; 24 regulator-max-microvolt = <1250000>; 25 26 vin-supply = <&ppvar_sys>; 27 }; 28 29 pp1250_cam: pp1250-dvdd { 30 compatible = "regulator-fixed"; 31 regulator-name = "pp1250_dvdd"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pp1250_cam_en>; 34 35 enable-active-high; 36 gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; 37 38 /* 740us delay from gpio output high to pp1250 stable, 39 * rounding up to 1ms for safety. 40 */ 41 startup-delay-us = <1000>; 42 vin-supply = <&pp1250_s3>; 43 }; 44 45 pp900_s0: pp900-s0 { 46 compatible = "regulator-fixed"; 47 regulator-name = "pp900_s0"; 48 49 /* EC turns on w/ pp900_s0_en; always on for AP */ 50 regulator-always-on; 51 regulator-boot-on; 52 regulator-min-microvolt = <900000>; 53 regulator-max-microvolt = <900000>; 54 55 vin-supply = <&ppvar_sys>; 56 }; 57 58 ppvarn_lcd: ppvarn-lcd { 59 compatible = "regulator-fixed"; 60 regulator-name = "ppvarn_lcd"; 61 pinctrl-names = "default"; 62 pinctrl-0 = <&ppvarn_lcd_en>; 63 64 enable-active-high; 65 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; 66 vin-supply = <&ppvar_sys>; 67 }; 68 69 ppvarp_lcd: ppvarp-lcd { 70 compatible = "regulator-fixed"; 71 regulator-name = "ppvarp_lcd"; 72 pinctrl-names = "default"; 73 pinctrl-0 = <&ppvarp_lcd_en>; 74 75 enable-active-high; 76 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 77 vin-supply = <&ppvar_sys>; 78 }; 79 80 /* pp1800 children, sorted by name */ 81 pp900_s3: pp900-s3 { 82 compatible = "regulator-fixed"; 83 regulator-name = "pp900_s3"; 84 85 /* EC turns on w/ pp900_s3_en; always on for AP */ 86 regulator-always-on; 87 regulator-boot-on; 88 regulator-min-microvolt = <900000>; 89 regulator-max-microvolt = <900000>; 90 91 vin-supply = <&pp1800>; 92 }; 93 94 /* EC turns on pp1800_s3_en */ 95 pp1800_s3: pp1800 { 96 }; 97 98 /* pp3300 children, sorted by name */ 99 pp2800_cam: pp2800-avdd { 100 compatible = "regulator-fixed"; 101 regulator-name = "pp2800_avdd"; 102 pinctrl-names = "default"; 103 pinctrl-0 = <&pp2800_cam_en>; 104 105 enable-active-high; 106 gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; 107 startup-delay-us = <100>; 108 vin-supply = <&pp3300>; 109 }; 110 111 /* EC turns on pp3300_s0_en */ 112 pp3300_s0: pp3300 { 113 }; 114 115 /* EC turns on pp3300_s3_en */ 116 pp3300_s3: pp3300 { 117 }; 118 119 /* 120 * See b/66922012 121 * 122 * This is a hack to make sure the Bluetooth part of the QCA6174A 123 * is reset at boot by toggling BT_EN. At boot BT_EN is first set 124 * to low when the bt_3v3 regulator is registered (in disabled 125 * state). The fake regulator is configured as a supply of the 126 * wlan_3v3 regulator below. When wlan_3v3 is enabled early in 127 * the boot process it also enables its supply regulator bt_3v3, 128 * which changes BT_EN to high. 129 */ 130 bt_3v3: bt-3v3 { 131 compatible = "regulator-fixed"; 132 regulator-name = "bt_3v3"; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&bt_en_1v8_l>; 135 136 enable-active-high; 137 gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; 138 vin-supply = <&pp3300_s3>; 139 }; 140 141 wlan_3v3: wlan-3v3 { 142 compatible = "regulator-fixed"; 143 regulator-name = "wlan_3v3"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&wlan_pd_1v8_l>; 146 147 /* 148 * The WL_EN pin is driven low when the regulator is 149 * registered, and transitions to high when the PCIe bus 150 * is powered up. 151 */ 152 enable-active-high; 153 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; 154 155 /* 156 * Require minimum 10ms from power-on (e.g., PD#) to init PCIe. 157 * TODO (b/64444991): how long to assert PD#? 158 */ 159 regulator-enable-ramp-delay = <10000>; 160 /* See bt_3v3 hack above */ 161 vin-supply = <&bt_3v3>; 162 }; 163 164 backlight: backlight { 165 compatible = "pwm-backlight"; 166 enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; 167 pinctrl-names = "default"; 168 pinctrl-0 = <&bl_en>; 169 pwms = <&pwm1 0 1000000 0>; 170 pwm-delay-us = <10000>; 171 }; 172 173 dmic: dmic { 174 compatible = "dmic-codec"; 175 dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&dmic_en>; 178 wakeup-delay-ms = <250>; 179 }; 180 181 gpio_keys: gpio-keys { 182 compatible = "gpio-keys"; 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pen_eject_odl>; 185 186 switch-pen-insert { 187 label = "Pen Insert"; 188 /* Insert = low, eject = high */ 189 gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 190 linux,code = <SW_PEN_INSERTED>; 191 linux,input-type = <EV_SW>; 192 wakeup-source; 193 }; 194 }; 195}; 196 197/* pp900_s0 aliases */ 198pp900_ddrpll_ap: &pp900_s0 { 199}; 200pp900_pcie: &pp900_s0 { 201}; 202pp900_usb: &pp900_s0 { 203}; 204 205/* pp900_s3 aliases */ 206pp900_emmcpll: &pp900_s3 { 207}; 208 209/* EC turns on; alias for pp1800_s0 */ 210pp1800_pcie: &pp1800_s0 { 211}; 212 213/* On scarlet PPVAR(big_cpu, lit_cpu, gpu) need to adjust voltage ranges */ 214&ppvar_bigcpu { 215 ctrl-voltage-range = <800074 1299226>; 216 regulator-min-microvolt = <800074>; 217 regulator-max-microvolt = <1299226>; 218}; 219 220&ppvar_bigcpu_pwm { 221 /* On scarlet ppvar big cpu use pwm3 */ 222 pwms = <&pwm3 0 3337 0>; 223 regulator-min-microvolt = <800074>; 224 regulator-max-microvolt = <1299226>; 225}; 226 227&ppvar_litcpu { 228 ctrl-voltage-range = <802122 1199620>; 229 regulator-min-microvolt = <802122>; 230 regulator-max-microvolt = <1199620>; 231}; 232 233&ppvar_litcpu_pwm { 234 regulator-min-microvolt = <802122>; 235 regulator-max-microvolt = <1199620>; 236}; 237 238&ppvar_gpu { 239 ctrl-voltage-range = <799600 1099600>; 240 regulator-min-microvolt = <799600>; 241 regulator-max-microvolt = <1099600>; 242}; 243 244&ppvar_gpu_pwm { 245 regulator-min-microvolt = <799600>; 246 regulator-max-microvolt = <1099600>; 247}; 248 249&ppvar_sd_card_io { 250 states = <1800000 0x0>, <3300000 0x1>; 251 regulator-max-microvolt = <3300000>; 252}; 253 254&pp3000_sd_slot { 255 vin-supply = <&pp3300>; 256}; 257 258ap_i2c_dig: &i2c2 { 259 status = "okay"; 260 261 clock-frequency = <400000>; 262 263 /* These are relatively safe rise/fall times. */ 264 i2c-scl-falling-time-ns = <50>; 265 i2c-scl-rising-time-ns = <300>; 266 267 digitizer: digitizer@9 { 268 compatible = "hid-over-i2c"; 269 reg = <0x9>; 270 interrupt-parent = <&gpio1>; 271 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 272 hid-descr-addr = <0x1>; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&pen_int_odl &pen_reset_l>; 275 }; 276}; 277 278&ap_i2c_ts { 279 touchscreen: touchscreen@10 { 280 compatible = "elan,ekth3500"; 281 reg = <0x10>; 282 interrupt-parent = <&gpio1>; 283 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&touch_int_l &touch_reset_l>; 286 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; 287 }; 288}; 289 290camera: &i2c7 { 291 status = "okay"; 292 293 clock-frequency = <400000>; 294 295 /* These are relatively safe rise/fall times; TODO: measure */ 296 i2c-scl-falling-time-ns = <50>; 297 i2c-scl-rising-time-ns = <300>; 298 299 /* 24M mclk is shared between world and user cameras */ 300 pinctrl-0 = <&i2c7_xfer &test_clkout1>; 301 302 /* Rear-facing camera */ 303 wcam: camera@36 { 304 compatible = "ovti,ov5695"; 305 reg = <0x36>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&wcam_rst>; 308 309 clocks = <&cru SCLK_TESTCLKOUT1>; 310 clock-names = "xvclk"; 311 312 avdd-supply = <&pp2800_cam>; 313 dvdd-supply = <&pp1250_cam>; 314 dovdd-supply = <&pp1800_s0>; 315 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; 316 317 port { 318 wcam_out: endpoint { 319 remote-endpoint = <&mipi_in_wcam>; 320 data-lanes = <1 2>; 321 }; 322 }; 323 }; 324 325 /* Front-facing camera */ 326 ucam: camera@3c { 327 compatible = "ovti,ov2685"; 328 reg = <0x3c>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&ucam_rst>; 331 332 clocks = <&cru SCLK_TESTCLKOUT1>; 333 clock-names = "xvclk"; 334 335 avdd-supply = <&pp2800_cam>; 336 dovdd-supply = <&pp1800_s0>; 337 dvdd-supply = <&pp1800_s0>; 338 reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; 339 340 port { 341 ucam_out: endpoint { 342 remote-endpoint = <&mipi_in_ucam>; 343 data-lanes = <1>; 344 }; 345 }; 346 }; 347}; 348 349&cdn_dp { 350 extcon = <&usbc_extcon0>; 351 phys = <&tcphy0_dp>; 352}; 353 354&cpu_alert0 { 355 temperature = <66000>; 356}; 357 358&cpu_alert1 { 359 temperature = <71000>; 360}; 361 362&cros_ec { 363 interrupt-parent = <&gpio1>; 364 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 365}; 366 367&cru { 368 assigned-clocks = 369 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 370 <&cru PLL_NPLL>, 371 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 372 <&cru PCLK_PERIHP>, 373 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 374 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 375 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 376 <&cru ACLK_VIO>, 377 <&cru ACLK_GIC_PRE>, 378 <&cru PCLK_DDR>, 379 <&cru ACLK_HDCP>, 380 <&cru ACLK_VDU>; 381 assigned-clock-rates = 382 <600000000>, <1600000000>, 383 <1000000000>, 384 <150000000>, <75000000>, 385 <37500000>, 386 <100000000>, <100000000>, 387 <50000000>, <800000000>, 388 <100000000>, <50000000>, 389 <400000000>, 390 <200000000>, 391 <200000000>, 392 <400000000>, 393 <400000000>; 394}; 395 396/* The center supply is fixed to .9V on scarlet */ 397&dmc { 398 center-supply = <&pp900_s0>; 399}; 400 401/* We don't need .925 V for 928 MHz on scarlet */ 402&dmc_opp_table { 403 opp03 { 404 opp-microvolt = <900000>; 405 }; 406}; 407 408&gpio0 { 409 gpio-line-names = /* GPIO0 A 0-7 */ 410 "CLK_32K_AP", 411 "EC_IN_RW_OD", 412 "SPK_PA_EN", 413 "WLAN_PERST_1V8_L", 414 "WLAN_PD_1V8_L", 415 "WLAN_RF_KILL_1V8_L", 416 "BIGCPU_DVS_PWM", 417 "SD_CD_L_JTAG_EN", 418 419 /* GPIO0 B 0-5 */ 420 "BT_EN_BT_RF_KILL_1V8_L", 421 "PMUIO2_33_18_L_PP3300_S0_EN", 422 "TOUCH_RESET_L", 423 "AP_EC_WARM_RESET_REQ", 424 "PEN_RESET_L", 425 /* 426 * AP_FLASH_WP_L is crossystem ABI. Schematics call 427 * it AP_FLASH_WP_R_ODL. 428 */ 429 "AP_FLASH_WP_L"; 430}; 431 432&gpio1 { 433 gpio-line-names = /* GPIO1 A 0-7 */ 434 "PEN_INT_ODL", 435 "PEN_EJECT_ODL", 436 "BT_HOST_WAKE_1V8_L", 437 "WLAN_HOST_WAKE_1V8_L", 438 "TOUCH_INT_ODL", 439 "AP_EC_S3_S0_L", 440 "AP_EC_OVERTEMP", 441 "AP_SPI_FLASH_MISO", 442 443 /* GPIO1 B 0-7 */ 444 "AP_SPI_FLASH_MOSI_R", 445 "AP_SPI_FLASH_CLK_R", 446 "AP_SPI_FLASH_CS_L_R", 447 "SD_CARD_DET_ODL", 448 "", 449 "AP_EXPANSION_IO1", 450 "AP_EXPANSION_IO2", 451 "AP_I2C_DISP_SDA", 452 453 /* GPIO1 C 0-7 */ 454 "AP_I2C_DISP_SCL", 455 "H1_INT_ODL", 456 "EC_AP_INT_ODL", 457 "LITCPU_DVS_PWM", 458 "AP_I2C_AUDIO_SDA", 459 "AP_I2C_AUDIO_SCL", 460 "AP_EXPANSION_IO3", 461 "HEADSET_INT_ODL", 462 463 /* GPIO1 D0 */ 464 "AP_EXPANSION_IO4"; 465}; 466 467&gpio2 { 468 gpio-line-names = /* GPIO2 A 0-7 */ 469 "AP_I2C_PEN_SDA", 470 "AP_I2C_PEN_SCL", 471 "SD_IO_PWR_EN", 472 "UCAM_RST_L", 473 "PP1250_CAM_EN", 474 "WCAM_RST_L", 475 "AP_EXPANSION_IO5", 476 "AP_I2C_CAM_SDA", 477 478 /* GPIO2 B 0-7 */ 479 "AP_I2C_CAM_SCL", 480 "AP_H1_SPI_MISO", 481 "AP_H1_SPI_MOSI", 482 "AP_H1_SPI_CLK", 483 "AP_H1_SPI_CS_L", 484 "", 485 "", 486 "", 487 488 /* GPIO2 C 0-7 */ 489 "UART_EXPANSION_TX_AP_RX", 490 "UART_AP_TX_EXPANSION_RX", 491 "UART_EXPANSION_RTS_AP_CTS", 492 "UART_AP_RTS_EXPANSION_CTS", 493 "AP_SPI_EC_MISO", 494 "AP_SPI_EC_MOSI", 495 "AP_SPI_EC_CLK", 496 "AP_SPI_EC_CS_L", 497 498 /* GPIO2 D 0-4 */ 499 "PP2800_CAM_EN", 500 "CLK_24M_CAM", 501 "WLAN_PCIE_CLKREQ_1V8_L", 502 "", 503 "SD_PWR_3000_1800_L"; 504}; 505 506&gpio3 { 507 gpio-line-names = /* GPIO3 A 0-7 */ 508 "", 509 "", 510 "", 511 "", 512 "", 513 "", 514 "", 515 "", 516 517 /* GPIO3 B 0-7 */ 518 "", 519 "", 520 "", 521 "", 522 "", 523 "", 524 "", 525 "", 526 527 /* GPIO3 C 0-7 */ 528 "", 529 "", 530 "", 531 "", 532 "", 533 "", 534 "", 535 "", 536 537 /* GPIO3 D 0-7 */ 538 "I2S0_SCLK", 539 "I2S0_LRCK_RX", 540 "I2S0_LRCK_TX", 541 "I2S0_SDI_0", 542 "STRAP_LCDBIAS_L", 543 "STRAP_FEATURE_1", 544 "STRAP_FEATURE_2", 545 "I2S0_SDO_0"; 546}; 547 548&gpio4 { 549 gpio-line-names = /* GPIO4 A 0-7 */ 550 "I2S_MCLK", 551 "AP_I2C_EXPANSION_SDA", 552 "AP_I2C_EXPANSION_SCL", 553 "DMIC_EN", 554 "", 555 "", 556 "", 557 "", 558 559 /* GPIO4 B 0-7 */ 560 "", 561 "", 562 "", 563 "", 564 "", 565 "", 566 "", 567 "", 568 569 /* GPIO4 C 0-7 */ 570 "AP_I2C_TS_SDA", 571 "AP_I2C_TS_SCL", 572 "GPU_DVS_PWM", 573 "UART_DBG_TX_AP_RX", 574 "UART_AP_TX_DBG_RX", 575 "BL_EN", 576 "BL_PWM", 577 "", 578 579 /* GPIO4 D 0-5 */ 580 "", 581 "DISPLAY_RST_L", 582 "", 583 "PPVARP_LCD_EN", 584 "PPVARN_LCD_EN", 585 "SD_SLOT_PWR_EN"; 586}; 587 588&i2c_tunnel { 589 google,remote-bus = <0>; 590}; 591 592&io_domains { 593 bt656-supply = <&pp1800_s0>; /* APIO2_VDD; 2a 2b */ 594 audio-supply = <&pp1800_s0>; /* APIO5_VDD; 3d 4a */ 595 gpio1830-supply = <&pp1800_s0>; /* APIO4_VDD; 4c 4d */ 596}; 597 598&isp0 { 599 status = "okay"; 600 601 ports { 602 port@0 { 603 mipi_in_wcam: endpoint@0 { 604 reg = <0>; 605 remote-endpoint = <&wcam_out>; 606 data-lanes = <1 2>; 607 }; 608 609 mipi_in_ucam: endpoint@1 { 610 reg = <1>; 611 remote-endpoint = <&ucam_out>; 612 data-lanes = <1>; 613 }; 614 }; 615 }; 616}; 617 618&isp0_mmu { 619 status = "okay"; 620}; 621 622&max98357a { 623 sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; 624}; 625 626&mipi_dphy_rx0 { 627 status = "okay"; 628}; 629 630&mipi_dsi { 631 status = "okay"; 632 clock-master; 633 634 ports { 635 mipi_out: port@1 { 636 reg = <1>; 637 638 mipi_out_panel: endpoint { 639 remote-endpoint = <&mipi_in_panel>; 640 }; 641 }; 642 }; 643 644 mipi_panel: panel@0 { 645 /* 2 different panels are used, compatibles are in dts files */ 646 reg = <0>; 647 backlight = <&backlight>; 648 enable-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; 649 pinctrl-names = "default"; 650 pinctrl-0 = <&display_rst_l>; 651 652 ports { 653 #address-cells = <1>; 654 #size-cells = <0>; 655 656 port@0 { 657 reg = <0>; 658 659 mipi_in_panel: endpoint { 660 remote-endpoint = <&mipi_out_panel>; 661 }; 662 }; 663 664 port@1 { 665 reg = <1>; 666 667 mipi1_in_panel: endpoint@1 { 668 remote-endpoint = <&mipi1_out_panel>; 669 }; 670 }; 671 }; 672 }; 673}; 674 675&mipi_dsi1 { 676 status = "okay"; 677 678 ports { 679 mipi1_out: port@1 { 680 reg = <1>; 681 682 mipi1_out_panel: endpoint { 683 remote-endpoint = <&mipi1_in_panel>; 684 }; 685 }; 686 }; 687}; 688 689&pcie0 { 690 ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; 691 692 /* PERST# asserted in S3 */ 693 pcie-reset-suspend = <1>; 694 695 vpcie3v3-supply = <&wlan_3v3>; 696 vpcie1v8-supply = <&pp1800_pcie>; 697}; 698 699&sdmmc { 700 cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 701}; 702 703&sound { 704 rockchip,codec = <&max98357a &dmic &codec &cdn_dp>; 705}; 706 707&spi2 { 708 status = "okay"; 709 710 cr50@0 { 711 compatible = "google,cr50"; 712 reg = <0>; 713 interrupt-parent = <&gpio1>; 714 interrupts = <17 IRQ_TYPE_EDGE_RISING>; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&h1_int_od_l>; 717 spi-max-frequency = <800000>; 718 }; 719}; 720 721&usb_host0_ohci { 722 #address-cells = <1>; 723 #size-cells = <0>; 724 725 qca_bt: bluetooth@1 { 726 compatible = "usbcf3,e300", "usb4ca,301a"; 727 reg = <1>; 728 pinctrl-names = "default"; 729 pinctrl-0 = <&bt_host_wake_l>; 730 interrupt-parent = <&gpio1>; 731 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 732 interrupt-names = "wakeup"; 733 }; 734}; 735 736/* PINCTRL OVERRIDES */ 737&ap_fw_wp { 738 rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 739}; 740 741&bl_en { 742 rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 743}; 744 745&bt_host_wake_l { 746 rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 747}; 748 749&ec_ap_int_l { 750 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; 751}; 752 753&headset_int_l { 754 rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; 755}; 756 757&i2s0_8ch_bus { 758 rockchip,pins = 759 <3 RK_PD0 1 &pcfg_pull_none_6ma>, 760 <3 RK_PD1 1 &pcfg_pull_none_6ma>, 761 <3 RK_PD2 1 &pcfg_pull_none_6ma>, 762 <3 RK_PD3 1 &pcfg_pull_none_6ma>, 763 <3 RK_PD7 1 &pcfg_pull_none_6ma>, 764 <4 RK_PA0 1 &pcfg_pull_none_6ma>; 765}; 766 767&i2s0_8ch_bus_bclk_off { 768 rockchip,pins = 769 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none_6ma>, 770 <3 RK_PD1 1 &pcfg_pull_none_6ma>, 771 <3 RK_PD2 1 &pcfg_pull_none_6ma>, 772 <3 RK_PD3 1 &pcfg_pull_none_6ma>, 773 <3 RK_PD7 1 &pcfg_pull_none_6ma>, 774 <4 RK_PA0 1 &pcfg_pull_none_6ma>; 775}; 776 777/* there is no external pull up, so need to set this pin pull up */ 778&sdmmc_cd_pin { 779 rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; 780}; 781 782&sd_pwr_1800_sel { 783 rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; 784}; 785 786&sdmode_en { 787 rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; 788}; 789 790&touch_reset_l { 791 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; 792}; 793 794&touch_int_l { 795 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; 796}; 797 798&pinctrl { 799 pinctrl-0 = < 800 &ap_pwroff /* AP will auto-assert this when in S3 */ 801 &clk_32k /* This pin is always 32k on gru boards */ 802 &wlan_rf_kill_1v8_l 803 >; 804 805 pcfg_pull_none_6ma: pcfg-pull-none-6ma { 806 bias-disable; 807 drive-strength = <6>; 808 }; 809 810 camera { 811 pp1250_cam_en: pp1250-dvdd { 812 rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 813 }; 814 815 pp2800_cam_en: pp2800-avdd { 816 rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 817 }; 818 819 ucam_rst: ucam_rst { 820 rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 821 }; 822 823 wcam_rst: wcam_rst { 824 rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 825 }; 826 }; 827 828 digitizer { 829 pen_int_odl: pen-int-odl { 830 rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; 831 }; 832 833 pen_reset_l: pen-reset-l { 834 rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 835 }; 836 }; 837 838 discrete-regulators { 839 display_rst_l: display-rst-l { 840 rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>; 841 }; 842 843 ppvarp_lcd_en: ppvarp-lcd-en { 844 rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 845 }; 846 847 ppvarn_lcd_en: ppvarn-lcd-en { 848 rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 849 }; 850 }; 851 852 dmic { 853 dmic_en: dmic-en { 854 rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 855 }; 856 }; 857 858 pen { 859 pen_eject_odl: pen-eject-odl { 860 rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; 861 }; 862 }; 863 864 tpm { 865 h1_int_od_l: h1-int-od-l { 866 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; 867 }; 868 }; 869}; 870 871&wifi { 872 bt_en_1v8_l: bt-en-1v8-l { 873 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 874 }; 875 876 wlan_pd_1v8_l: wlan-pd-1v8-l { 877 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 878 }; 879 880 /* Default pull-up, but just to be clear */ 881 wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l { 882 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 883 }; 884 885 wifi_perst_l: wifi-perst-l { 886 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 887 }; 888 889 wlan_host_wake_l: wlan-host-wake-l { 890 rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 891 }; 892}; 893