xref: /linux/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi (revision b83deaa741558babf4b8d51d34f6637ccfff1b26) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11/* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
12#define EMMC	1
13
14/*
15 * To enable uSD card on CN3,
16 * SW1[2] should be at position 3/ON.
17 * Disable eMMC by setting "#define EMMC	0" above.
18 */
19#define SDHI	(!EMMC)
20
21/ {
22	aliases {
23		ethernet0 = &eth0;
24		ethernet1 = &eth1;
25	};
26
27	chosen {
28		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
29	};
30
31	memory@48000000 {
32		device_type = "memory";
33		/* first 128MB is reserved for secure area. */
34		reg = <0x0 0x48000000 0x0 0x78000000>;
35	};
36
37	reg_1p8v: regulator0 {
38		compatible = "regulator-fixed";
39		regulator-name = "fixed-1.8V";
40		regulator-min-microvolt = <1800000>;
41		regulator-max-microvolt = <1800000>;
42		regulator-boot-on;
43		regulator-always-on;
44	};
45
46	reg_3p3v: regulator1 {
47		compatible = "regulator-fixed";
48		regulator-name = "fixed-3.3V";
49		regulator-min-microvolt = <3300000>;
50		regulator-max-microvolt = <3300000>;
51		regulator-boot-on;
52		regulator-always-on;
53	};
54
55	reg_1p1v: regulator-vdd-core {
56		compatible = "regulator-fixed";
57		regulator-name = "fixed-1.1V";
58		regulator-min-microvolt = <1100000>;
59		regulator-max-microvolt = <1100000>;
60		regulator-boot-on;
61		regulator-always-on;
62	};
63
64	vccq_sdhi0: regulator-vccq-sdhi0 {
65		compatible = "regulator-gpio";
66
67		regulator-name = "SDHI0 VccQ";
68		regulator-min-microvolt = <1800000>;
69		regulator-max-microvolt = <3300000>;
70		states = <3300000 1>, <1800000 0>;
71		regulator-boot-on;
72		gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
73		regulator-always-on;
74	};
75};
76
77&adc {
78	pinctrl-0 = <&adc_pins>;
79	pinctrl-names = "default";
80	status = "okay";
81
82	/delete-node/ channel@6;
83	/delete-node/ channel@7;
84};
85
86&eth0 {
87	pinctrl-0 = <&eth0_pins>;
88	pinctrl-names = "default";
89	phy-handle = <&phy0>;
90	phy-mode = "rgmii-id";
91	status = "okay";
92
93	phy0: ethernet-phy@7 {
94		compatible = "ethernet-phy-id0022.1640",
95			     "ethernet-phy-ieee802.3-c22";
96		reg = <7>;
97		rxc-skew-psec = <2400>;
98		txc-skew-psec = <2400>;
99		rxdv-skew-psec = <0>;
100		txdv-skew-psec = <0>;
101		rxd0-skew-psec = <0>;
102		rxd1-skew-psec = <0>;
103		rxd2-skew-psec = <0>;
104		rxd3-skew-psec = <0>;
105		txd0-skew-psec = <0>;
106		txd1-skew-psec = <0>;
107		txd2-skew-psec = <0>;
108		txd3-skew-psec = <0>;
109	};
110};
111
112&eth1 {
113	pinctrl-0 = <&eth1_pins>;
114	pinctrl-names = "default";
115	phy-handle = <&phy1>;
116	phy-mode = "rgmii-id";
117	status = "okay";
118
119	phy1: ethernet-phy@7 {
120		compatible = "ethernet-phy-id0022.1640",
121			     "ethernet-phy-ieee802.3-c22";
122		reg = <7>;
123		rxc-skew-psec = <2400>;
124		txc-skew-psec = <2400>;
125		rxdv-skew-psec = <0>;
126		txdv-skew-psec = <0>;
127		rxd0-skew-psec = <0>;
128		rxd1-skew-psec = <0>;
129		rxd2-skew-psec = <0>;
130		rxd3-skew-psec = <0>;
131		txd0-skew-psec = <0>;
132		txd1-skew-psec = <0>;
133		txd2-skew-psec = <0>;
134		txd3-skew-psec = <0>;
135	};
136};
137
138&extal_clk {
139	clock-frequency = <24000000>;
140};
141
142&gpu {
143	mali-supply = <&reg_1p1v>;
144};
145
146&ostm1 {
147	status = "okay";
148};
149
150&ostm2 {
151	status = "okay";
152};
153
154&pinctrl {
155	adc_pins: adc {
156		pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
157	};
158
159	eth0_pins: eth0 {
160		pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
161			 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
162			 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
163			 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
164			 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
165			 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
166			 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
167			 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
168			 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
169			 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
170			 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
171			 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
172			 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
173			 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
174			 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
175	};
176
177	eth1_pins: eth1 {
178		pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
179			 <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
180			 <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
181			 <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
182			 <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
183			 <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
184			 <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
185			 <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
186			 <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
187			 <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
188			 <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
189			 <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
190			 <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
191			 <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
192			 <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
193	};
194
195	gpio-sd0-pwr-en-hog {
196		gpio-hog;
197		gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
198		output-high;
199		line-name = "gpio_sd0_pwr_en";
200	};
201
202	qspi0_pins: qspi0 {
203		qspi0-data {
204			pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
205			power-source = <1800>;
206		};
207
208		qspi0-ctrl {
209			pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
210			power-source = <1800>;
211		};
212	};
213
214	/*
215	 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
216	 * The below switch logic can be used to select the device between
217	 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
218	 * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
219	 * SW1[2] should be at position 3/ON to enable uSD card CN3
220	 */
221	sd0-dev-sel-hog {
222		gpio-hog;
223		gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
224		output-high;
225		line-name = "sd0_dev_sel";
226	};
227
228	sdhi0_emmc_pins: sd0emmc {
229		sd0_emmc_data {
230			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
231			       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
232			power-source = <1800>;
233		};
234
235		sd0_emmc_ctrl {
236			pins = "SD0_CLK", "SD0_CMD";
237			power-source = <1800>;
238		};
239
240		sd0_emmc_rst {
241			pins = "SD0_RST#";
242			power-source = <1800>;
243		};
244	};
245
246	sdhi0_pins: sd0 {
247		sd0_data {
248			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
249			power-source = <3300>;
250		};
251
252		sd0_ctrl {
253			pins = "SD0_CLK", "SD0_CMD";
254			power-source = <3300>;
255		};
256
257		sd0_mux {
258			pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
259		};
260	};
261
262	sdhi0_pins_uhs: sd0_uhs {
263		sd0_data_uhs {
264			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
265			power-source = <1800>;
266		};
267
268		sd0_ctrl_uhs {
269			pins = "SD0_CLK", "SD0_CMD";
270			power-source = <1800>;
271		};
272
273		sd0_mux_uhs {
274			pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
275		};
276	};
277};
278
279&sbc {
280	pinctrl-0 = <&qspi0_pins>;
281	pinctrl-names = "default";
282	status = "okay";
283
284	flash@0 {
285		compatible = "micron,mt25qu512a", "jedec,spi-nor";
286		reg = <0>;
287		m25p,fast-read;
288		spi-max-frequency = <50000000>;
289		spi-rx-bus-width = <4>;
290
291		partitions {
292			compatible = "fixed-partitions";
293			#address-cells = <1>;
294			#size-cells = <1>;
295
296			boot@0 {
297				reg = <0x00000000 0x2000000>;
298				read-only;
299			};
300			user@2000000 {
301				reg = <0x2000000 0x2000000>;
302			};
303		};
304	};
305};
306
307#if SDHI
308&sdhi0 {
309	pinctrl-0 = <&sdhi0_pins>;
310	pinctrl-1 = <&sdhi0_pins_uhs>;
311	pinctrl-names = "default", "state_uhs";
312
313	vmmc-supply = <&reg_3p3v>;
314	vqmmc-supply = <&vccq_sdhi0>;
315	bus-width = <4>;
316	sd-uhs-sdr50;
317	sd-uhs-sdr104;
318	status = "okay";
319};
320#endif
321
322#if EMMC
323&sdhi0 {
324	pinctrl-0 = <&sdhi0_emmc_pins>;
325	pinctrl-1 = <&sdhi0_emmc_pins>;
326	pinctrl-names = "default", "state_uhs";
327
328	vmmc-supply = <&reg_3p3v>;
329	vqmmc-supply = <&reg_1p8v>;
330	bus-width = <8>;
331	mmc-hs200-1_8v;
332	non-removable;
333	fixed-emmc-driver-type = <1>;
334	status = "okay";
335};
336#endif
337
338&wdt0 {
339	status = "okay";
340	timeout-sec = <60>;
341};
342
343&wdt1 {
344	status = "okay";
345	timeout-sec = <60>;
346};
347
348&wdt2 {
349	status = "okay";
350	timeout-sec = <60>;
351};
352