1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8250.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 chosen { }; 19 20 clocks { 21 xo_board: xo-board { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <38400000>; 25 clock-output-names = "xo_board"; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 clock-frequency = <32000>; 31 #clock-cells = <0>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 CPU0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "qcom,kryo485"; 42 reg = <0x0 0x0>; 43 enable-method = "psci"; 44 next-level-cache = <&L2_0>; 45 L2_0: l2-cache { 46 compatible = "cache"; 47 next-level-cache = <&L3_0>; 48 L3_0: l3-cache { 49 compatible = "cache"; 50 }; 51 }; 52 }; 53 54 CPU1: cpu@100 { 55 device_type = "cpu"; 56 compatible = "qcom,kryo485"; 57 reg = <0x0 0x100>; 58 enable-method = "psci"; 59 next-level-cache = <&L2_100>; 60 L2_100: l2-cache { 61 compatible = "cache"; 62 next-level-cache = <&L3_0>; 63 }; 64 }; 65 66 CPU2: cpu@200 { 67 device_type = "cpu"; 68 compatible = "qcom,kryo485"; 69 reg = <0x0 0x200>; 70 enable-method = "psci"; 71 next-level-cache = <&L2_200>; 72 L2_200: l2-cache { 73 compatible = "cache"; 74 next-level-cache = <&L3_0>; 75 }; 76 }; 77 78 CPU3: cpu@300 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo485"; 81 reg = <0x0 0x300>; 82 enable-method = "psci"; 83 next-level-cache = <&L2_300>; 84 L2_300: l2-cache { 85 compatible = "cache"; 86 next-level-cache = <&L3_0>; 87 }; 88 }; 89 90 CPU4: cpu@400 { 91 device_type = "cpu"; 92 compatible = "qcom,kryo485"; 93 reg = <0x0 0x400>; 94 enable-method = "psci"; 95 next-level-cache = <&L2_400>; 96 L2_400: l2-cache { 97 compatible = "cache"; 98 next-level-cache = <&L3_0>; 99 }; 100 }; 101 102 CPU5: cpu@500 { 103 device_type = "cpu"; 104 compatible = "qcom,kryo485"; 105 reg = <0x0 0x500>; 106 enable-method = "psci"; 107 next-level-cache = <&L2_500>; 108 L2_500: l2-cache { 109 compatible = "cache"; 110 next-level-cache = <&L3_0>; 111 }; 112 113 }; 114 115 CPU6: cpu@600 { 116 device_type = "cpu"; 117 compatible = "qcom,kryo485"; 118 reg = <0x0 0x600>; 119 enable-method = "psci"; 120 next-level-cache = <&L2_600>; 121 L2_600: l2-cache { 122 compatible = "cache"; 123 next-level-cache = <&L3_0>; 124 }; 125 }; 126 127 CPU7: cpu@700 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo485"; 130 reg = <0x0 0x700>; 131 enable-method = "psci"; 132 next-level-cache = <&L2_700>; 133 L2_700: l2-cache { 134 compatible = "cache"; 135 next-level-cache = <&L3_0>; 136 }; 137 }; 138 }; 139 140 firmware { 141 scm: scm { 142 compatible = "qcom,scm"; 143 #reset-cells = <1>; 144 }; 145 }; 146 147 tcsr_mutex: hwlock { 148 compatible = "qcom,tcsr-mutex"; 149 syscon = <&tcsr_mutex_regs 0 0x1000>; 150 #hwlock-cells = <1>; 151 }; 152 153 memory@80000000 { 154 device_type = "memory"; 155 /* We expect the bootloader to fill in the size */ 156 reg = <0x0 0x80000000 0x0 0x0>; 157 }; 158 159 pmu { 160 compatible = "arm,armv8-pmuv3"; 161 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 162 }; 163 164 psci { 165 compatible = "arm,psci-1.0"; 166 method = "smc"; 167 }; 168 169 reserved-memory { 170 #address-cells = <2>; 171 #size-cells = <2>; 172 ranges; 173 174 hyp_mem: memory@80000000 { 175 reg = <0x0 0x80000000 0x0 0x600000>; 176 no-map; 177 }; 178 179 xbl_aop_mem: memory@80700000 { 180 reg = <0x0 0x80700000 0x0 0x160000>; 181 no-map; 182 }; 183 184 cmd_db: memory@80860000 { 185 compatible = "qcom,cmd-db"; 186 reg = <0x0 0x80860000 0x0 0x20000>; 187 no-map; 188 }; 189 190 smem_mem: memory@80900000 { 191 reg = <0x0 0x80900000 0x0 0x200000>; 192 no-map; 193 }; 194 195 removed_mem: memory@80b00000 { 196 reg = <0x0 0x80b00000 0x0 0x5300000>; 197 no-map; 198 }; 199 200 camera_mem: memory@86200000 { 201 reg = <0x0 0x86200000 0x0 0x500000>; 202 no-map; 203 }; 204 205 wlan_mem: memory@86700000 { 206 reg = <0x0 0x86700000 0x0 0x100000>; 207 no-map; 208 }; 209 210 ipa_fw_mem: memory@86800000 { 211 reg = <0x0 0x86800000 0x0 0x10000>; 212 no-map; 213 }; 214 215 ipa_gsi_mem: memory@86810000 { 216 reg = <0x0 0x86810000 0x0 0xa000>; 217 no-map; 218 }; 219 220 gpu_mem: memory@8681a000 { 221 reg = <0x0 0x8681a000 0x0 0x2000>; 222 no-map; 223 }; 224 225 npu_mem: memory@86900000 { 226 reg = <0x0 0x86900000 0x0 0x500000>; 227 no-map; 228 }; 229 230 video_mem: memory@86e00000 { 231 reg = <0x0 0x86e00000 0x0 0x500000>; 232 no-map; 233 }; 234 235 cvp_mem: memory@87300000 { 236 reg = <0x0 0x87300000 0x0 0x500000>; 237 no-map; 238 }; 239 240 cdsp_mem: memory@87800000 { 241 reg = <0x0 0x87800000 0x0 0x1400000>; 242 no-map; 243 }; 244 245 slpi_mem: memory@88c00000 { 246 reg = <0x0 0x88c00000 0x0 0x1500000>; 247 no-map; 248 }; 249 250 adsp_mem: memory@8a100000 { 251 reg = <0x0 0x8a100000 0x0 0x1d00000>; 252 no-map; 253 }; 254 255 spss_mem: memory@8be00000 { 256 reg = <0x0 0x8be00000 0x0 0x100000>; 257 no-map; 258 }; 259 260 cdsp_secure_heap: memory@8bf00000 { 261 reg = <0x0 0x8bf00000 0x0 0x4600000>; 262 no-map; 263 }; 264 }; 265 266 smem: qcom,smem { 267 compatible = "qcom,smem"; 268 memory-region = <&smem_mem>; 269 hwlocks = <&tcsr_mutex 3>; 270 }; 271 272 soc: soc@0 { 273 #address-cells = <2>; 274 #size-cells = <2>; 275 ranges = <0 0 0 0 0x10 0>; 276 dma-ranges = <0 0 0 0 0x10 0>; 277 compatible = "simple-bus"; 278 279 gcc: clock-controller@100000 { 280 compatible = "qcom,gcc-sm8250"; 281 reg = <0x0 0x00100000 0x0 0x1f0000>; 282 #clock-cells = <1>; 283 #reset-cells = <1>; 284 #power-domain-cells = <1>; 285 clock-names = "bi_tcxo", "sleep_clk"; 286 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; 287 }; 288 289 qupv3_id_1: geniqup@ac0000 { 290 compatible = "qcom,geni-se-qup"; 291 reg = <0x0 0x00ac0000 0x0 0x6000>; 292 clock-names = "m-ahb", "s-ahb"; 293 clocks = <&gcc 133>, <&gcc 134>; 294 #address-cells = <2>; 295 #size-cells = <2>; 296 ranges; 297 status = "disabled"; 298 299 uart2: serial@a90000 { 300 compatible = "qcom,geni-debug-uart"; 301 reg = <0x0 0x00a90000 0x0 0x4000>; 302 clock-names = "se"; 303 clocks = <&gcc 113>; 304 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 305 status = "disabled"; 306 }; 307 }; 308 309 ufs_mem_hc: ufs@1d84000 { 310 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 311 "jedec,ufs-2.0"; 312 reg = <0 0x01d84000 0 0x3000>; 313 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 314 phys = <&ufs_mem_phy_lanes>; 315 phy-names = "ufsphy"; 316 lanes-per-direction = <2>; 317 #reset-cells = <1>; 318 resets = <&gcc GCC_UFS_PHY_BCR>; 319 reset-names = "rst"; 320 321 power-domains = <&gcc UFS_PHY_GDSC>; 322 323 clock-names = 324 "core_clk", 325 "bus_aggr_clk", 326 "iface_clk", 327 "core_clk_unipro", 328 "ref_clk", 329 "tx_lane0_sync_clk", 330 "rx_lane0_sync_clk", 331 "rx_lane1_sync_clk"; 332 clocks = 333 <&gcc GCC_UFS_PHY_AXI_CLK>, 334 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 335 <&gcc GCC_UFS_PHY_AHB_CLK>, 336 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 337 <&rpmhcc RPMH_CXO_CLK>, 338 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 339 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 340 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 341 freq-table-hz = 342 <37500000 300000000>, 343 <0 0>, 344 <0 0>, 345 <37500000 300000000>, 346 <0 0>, 347 <0 0>, 348 <0 0>, 349 <0 0>; 350 351 status = "disabled"; 352 }; 353 354 ufs_mem_phy: phy@1d87000 { 355 compatible = "qcom,sm8250-qmp-ufs-phy"; 356 reg = <0 0x01d87000 0 0x1c0>; 357 #address-cells = <2>; 358 #size-cells = <2>; 359 ranges; 360 clock-names = "ref", 361 "ref_aux"; 362 clocks = <&rpmhcc RPMH_CXO_CLK>, 363 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 364 365 resets = <&ufs_mem_hc 0>; 366 reset-names = "ufsphy"; 367 status = "disabled"; 368 369 ufs_mem_phy_lanes: lanes@1d87400 { 370 reg = <0 0x01d87400 0 0x108>, 371 <0 0x01d87600 0 0x1e0>, 372 <0 0x01d87c00 0 0x1dc>, 373 <0 0x01d87800 0 0x108>, 374 <0 0x01d87a00 0 0x1e0>; 375 #phy-cells = <0>; 376 }; 377 }; 378 379 intc: interrupt-controller@17a00000 { 380 compatible = "arm,gic-v3"; 381 #interrupt-cells = <3>; 382 interrupt-controller; 383 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 384 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 385 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 386 }; 387 388 pdc: interrupt-controller@b220000 { 389 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 390 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 391 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 392 <125 63 1>, <126 716 12>; 393 #interrupt-cells = <2>; 394 interrupt-parent = <&intc>; 395 interrupt-controller; 396 }; 397 398 spmi: qcom,spmi@c440000 { 399 compatible = "qcom,spmi-pmic-arb"; 400 reg = <0x0 0x0c440000 0x0 0x0001100>, 401 <0x0 0x0c600000 0x0 0x2000000>, 402 <0x0 0x0e600000 0x0 0x0100000>, 403 <0x0 0x0e700000 0x0 0x00a0000>, 404 <0x0 0x0c40a000 0x0 0x0026000>; 405 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 406 interrupt-names = "periph_irq"; 407 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 408 qcom,ee = <0>; 409 qcom,channel = <0>; 410 #address-cells = <2>; 411 #size-cells = <0>; 412 interrupt-controller; 413 #interrupt-cells = <4>; 414 }; 415 416 apps_rsc: rsc@18200000 { 417 label = "apps_rsc"; 418 compatible = "qcom,rpmh-rsc"; 419 reg = <0x0 0x18200000 0x0 0x10000>, 420 <0x0 0x18210000 0x0 0x10000>, 421 <0x0 0x18220000 0x0 0x10000>; 422 reg-names = "drv-0", "drv-1", "drv-2"; 423 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 426 qcom,tcs-offset = <0xd00>; 427 qcom,drv-id = <2>; 428 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 429 <WAKE_TCS 3>, <CONTROL_TCS 1>; 430 431 rpmhcc: clock-controller { 432 compatible = "qcom,sm8250-rpmh-clk"; 433 #clock-cells = <1>; 434 clock-names = "xo"; 435 clocks = <&xo_board>; 436 }; 437 438 rpmhpd: power-controller { 439 compatible = "qcom,sm8250-rpmhpd"; 440 #power-domain-cells = <1>; 441 operating-points-v2 = <&rpmhpd_opp_table>; 442 443 rpmhpd_opp_table: opp-table { 444 compatible = "operating-points-v2"; 445 446 rpmhpd_opp_ret: opp1 { 447 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 448 }; 449 450 rpmhpd_opp_min_svs: opp2 { 451 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 452 }; 453 454 rpmhpd_opp_low_svs: opp3 { 455 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 456 }; 457 458 rpmhpd_opp_svs: opp4 { 459 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 460 }; 461 462 rpmhpd_opp_svs_l1: opp5 { 463 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 464 }; 465 466 rpmhpd_opp_nom: opp6 { 467 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 468 }; 469 470 rpmhpd_opp_nom_l1: opp7 { 471 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 472 }; 473 474 rpmhpd_opp_nom_l2: opp8 { 475 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 476 }; 477 478 rpmhpd_opp_turbo: opp9 { 479 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 480 }; 481 482 rpmhpd_opp_turbo_l1: opp10 { 483 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 484 }; 485 }; 486 }; 487 }; 488 489 tcsr_mutex_regs: syscon@1f40000 { 490 compatible = "syscon"; 491 reg = <0x0 0x01f40000 0x0 0x40000>; 492 }; 493 494 timer@17c20000 { 495 #address-cells = <2>; 496 #size-cells = <2>; 497 ranges; 498 compatible = "arm,armv7-timer-mem"; 499 reg = <0x0 0x17c20000 0x0 0x1000>; 500 clock-frequency = <19200000>; 501 502 frame@17c21000 { 503 frame-number = <0>; 504 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 506 reg = <0x0 0x17c21000 0x0 0x1000>, 507 <0x0 0x17c22000 0x0 0x1000>; 508 }; 509 510 frame@17c23000 { 511 frame-number = <1>; 512 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 513 reg = <0x0 0x17c23000 0x0 0x1000>; 514 status = "disabled"; 515 }; 516 517 frame@17c25000 { 518 frame-number = <2>; 519 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 520 reg = <0x0 0x17c25000 0x0 0x1000>; 521 status = "disabled"; 522 }; 523 524 frame@17c27000 { 525 frame-number = <3>; 526 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 527 reg = <0x0 0x17c27000 0x0 0x1000>; 528 status = "disabled"; 529 }; 530 531 frame@17c29000 { 532 frame-number = <4>; 533 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 534 reg = <0x0 0x17c29000 0x0 0x1000>; 535 status = "disabled"; 536 }; 537 538 frame@17c2b000 { 539 frame-number = <5>; 540 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 541 reg = <0x0 0x17c2b000 0x0 0x1000>; 542 status = "disabled"; 543 }; 544 545 frame@17c2d000 { 546 frame-number = <6>; 547 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 548 reg = <0x0 0x17c2d000 0x0 0x1000>; 549 status = "disabled"; 550 }; 551 }; 552 553 }; 554 555 timer { 556 compatible = "arm,armv8-timer"; 557 interrupts = <GIC_PPI 13 558 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 559 <GIC_PPI 14 560 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 561 <GIC_PPI 11 562 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 563 <GIC_PPI 12 564 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 565 }; 566}; 567