1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 aconnect { 77 compatible = "nvidia,tegra186-aconnect", 78 "nvidia,tegra210-aconnect"; 79 clocks = <&bpmp TEGRA186_CLK_APE>, 80 <&bpmp TEGRA186_CLK_APB2APE>; 81 clock-names = "ape", "apb2ape"; 82 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 ranges = <0x02900000 0x0 0x02900000 0x200000>; 86 status = "disabled"; 87 88 dma-controller@2930000 { 89 compatible = "nvidia,tegra186-adma"; 90 reg = <0x02930000 0x20000>; 91 interrupt-parent = <&agic>; 92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 124 #dma-cells = <1>; 125 clocks = <&bpmp TEGRA186_CLK_AHUB>; 126 clock-names = "d_audio"; 127 status = "disabled"; 128 }; 129 130 agic: interrupt-controller@2a40000 { 131 compatible = "nvidia,tegra186-agic", 132 "nvidia,tegra210-agic"; 133 #interrupt-cells = <3>; 134 interrupt-controller; 135 reg = <0x02a41000 0x1000>, 136 <0x02a42000 0x2000>; 137 interrupts = <GIC_SPI 145 138 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 139 clocks = <&bpmp TEGRA186_CLK_APE>; 140 clock-names = "clk"; 141 status = "disabled"; 142 }; 143 }; 144 145 mc: memory-controller@2c00000 { 146 compatible = "nvidia,tegra186-mc"; 147 reg = <0x0 0x02c00000 0x0 0xb0000>; 148 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 149 status = "disabled"; 150 151 #interconnect-cells = <1>; 152 #address-cells = <2>; 153 #size-cells = <2>; 154 155 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 156 157 /* 158 * Memory clients have access to all 40 bits that the memory 159 * controller can address. 160 */ 161 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 162 163 emc: external-memory-controller@2c60000 { 164 compatible = "nvidia,tegra186-emc"; 165 reg = <0x0 0x02c60000 0x0 0x50000>; 166 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&bpmp TEGRA186_CLK_EMC>; 168 clock-names = "emc"; 169 170 #interconnect-cells = <0>; 171 172 nvidia,bpmp = <&bpmp>; 173 }; 174 }; 175 176 uarta: serial@3100000 { 177 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 178 reg = <0x0 0x03100000 0x0 0x40>; 179 reg-shift = <2>; 180 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 181 clocks = <&bpmp TEGRA186_CLK_UARTA>; 182 clock-names = "serial"; 183 resets = <&bpmp TEGRA186_RESET_UARTA>; 184 reset-names = "serial"; 185 status = "disabled"; 186 }; 187 188 uartb: serial@3110000 { 189 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 190 reg = <0x0 0x03110000 0x0 0x40>; 191 reg-shift = <2>; 192 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&bpmp TEGRA186_CLK_UARTB>; 194 clock-names = "serial"; 195 resets = <&bpmp TEGRA186_RESET_UARTB>; 196 reset-names = "serial"; 197 status = "disabled"; 198 }; 199 200 uartd: serial@3130000 { 201 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 202 reg = <0x0 0x03130000 0x0 0x40>; 203 reg-shift = <2>; 204 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&bpmp TEGRA186_CLK_UARTD>; 206 clock-names = "serial"; 207 resets = <&bpmp TEGRA186_RESET_UARTD>; 208 reset-names = "serial"; 209 status = "disabled"; 210 }; 211 212 uarte: serial@3140000 { 213 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 214 reg = <0x0 0x03140000 0x0 0x40>; 215 reg-shift = <2>; 216 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&bpmp TEGRA186_CLK_UARTE>; 218 clock-names = "serial"; 219 resets = <&bpmp TEGRA186_RESET_UARTE>; 220 reset-names = "serial"; 221 status = "disabled"; 222 }; 223 224 uartf: serial@3150000 { 225 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 226 reg = <0x0 0x03150000 0x0 0x40>; 227 reg-shift = <2>; 228 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&bpmp TEGRA186_CLK_UARTF>; 230 clock-names = "serial"; 231 resets = <&bpmp TEGRA186_RESET_UARTF>; 232 reset-names = "serial"; 233 status = "disabled"; 234 }; 235 236 gen1_i2c: i2c@3160000 { 237 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 238 reg = <0x0 0x03160000 0x0 0x10000>; 239 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 clocks = <&bpmp TEGRA186_CLK_I2C1>; 243 clock-names = "div-clk"; 244 resets = <&bpmp TEGRA186_RESET_I2C1>; 245 reset-names = "i2c"; 246 status = "disabled"; 247 }; 248 249 cam_i2c: i2c@3180000 { 250 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 251 reg = <0x0 0x03180000 0x0 0x10000>; 252 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 clocks = <&bpmp TEGRA186_CLK_I2C3>; 256 clock-names = "div-clk"; 257 resets = <&bpmp TEGRA186_RESET_I2C3>; 258 reset-names = "i2c"; 259 status = "disabled"; 260 }; 261 262 /* shares pads with dpaux1 */ 263 dp_aux_ch1_i2c: i2c@3190000 { 264 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 265 reg = <0x0 0x03190000 0x0 0x10000>; 266 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 clocks = <&bpmp TEGRA186_CLK_I2C4>; 270 clock-names = "div-clk"; 271 resets = <&bpmp TEGRA186_RESET_I2C4>; 272 reset-names = "i2c"; 273 pinctrl-names = "default", "idle"; 274 pinctrl-0 = <&state_dpaux1_i2c>; 275 pinctrl-1 = <&state_dpaux1_off>; 276 status = "disabled"; 277 }; 278 279 /* controlled by BPMP, should not be enabled */ 280 pwr_i2c: i2c@31a0000 { 281 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 282 reg = <0x0 0x031a0000 0x0 0x10000>; 283 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 clocks = <&bpmp TEGRA186_CLK_I2C5>; 287 clock-names = "div-clk"; 288 resets = <&bpmp TEGRA186_RESET_I2C5>; 289 reset-names = "i2c"; 290 status = "disabled"; 291 }; 292 293 /* shares pads with dpaux0 */ 294 dp_aux_ch0_i2c: i2c@31b0000 { 295 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 296 reg = <0x0 0x031b0000 0x0 0x10000>; 297 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 clocks = <&bpmp TEGRA186_CLK_I2C6>; 301 clock-names = "div-clk"; 302 resets = <&bpmp TEGRA186_RESET_I2C6>; 303 reset-names = "i2c"; 304 pinctrl-names = "default", "idle"; 305 pinctrl-0 = <&state_dpaux_i2c>; 306 pinctrl-1 = <&state_dpaux_off>; 307 status = "disabled"; 308 }; 309 310 gen7_i2c: i2c@31c0000 { 311 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 312 reg = <0x0 0x031c0000 0x0 0x10000>; 313 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 clocks = <&bpmp TEGRA186_CLK_I2C7>; 317 clock-names = "div-clk"; 318 resets = <&bpmp TEGRA186_RESET_I2C7>; 319 reset-names = "i2c"; 320 status = "disabled"; 321 }; 322 323 gen9_i2c: i2c@31e0000 { 324 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 325 reg = <0x0 0x031e0000 0x0 0x10000>; 326 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 clocks = <&bpmp TEGRA186_CLK_I2C9>; 330 clock-names = "div-clk"; 331 resets = <&bpmp TEGRA186_RESET_I2C9>; 332 reset-names = "i2c"; 333 status = "disabled"; 334 }; 335 336 sdmmc1: mmc@3400000 { 337 compatible = "nvidia,tegra186-sdhci"; 338 reg = <0x0 0x03400000 0x0 0x10000>; 339 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 341 clock-names = "sdhci"; 342 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 343 reset-names = "sdhci"; 344 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 345 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 346 interconnect-names = "dma-mem", "write"; 347 iommus = <&smmu TEGRA186_SID_SDMMC1>; 348 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 349 pinctrl-0 = <&sdmmc1_3v3>; 350 pinctrl-1 = <&sdmmc1_1v8>; 351 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 352 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 353 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 354 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 355 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 356 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 357 nvidia,default-tap = <0x5>; 358 nvidia,default-trim = <0xb>; 359 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 360 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 361 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 362 status = "disabled"; 363 }; 364 365 sdmmc2: mmc@3420000 { 366 compatible = "nvidia,tegra186-sdhci"; 367 reg = <0x0 0x03420000 0x0 0x10000>; 368 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 370 clock-names = "sdhci"; 371 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 372 reset-names = "sdhci"; 373 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 374 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 375 interconnect-names = "dma-mem", "write"; 376 iommus = <&smmu TEGRA186_SID_SDMMC2>; 377 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 378 pinctrl-0 = <&sdmmc2_3v3>; 379 pinctrl-1 = <&sdmmc2_1v8>; 380 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 381 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 382 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 383 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 384 nvidia,default-tap = <0x5>; 385 nvidia,default-trim = <0xb>; 386 status = "disabled"; 387 }; 388 389 sdmmc3: mmc@3440000 { 390 compatible = "nvidia,tegra186-sdhci"; 391 reg = <0x0 0x03440000 0x0 0x10000>; 392 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 394 clock-names = "sdhci"; 395 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 396 reset-names = "sdhci"; 397 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 398 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 399 interconnect-names = "dma-mem", "write"; 400 iommus = <&smmu TEGRA186_SID_SDMMC3>; 401 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 402 pinctrl-0 = <&sdmmc3_3v3>; 403 pinctrl-1 = <&sdmmc3_1v8>; 404 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 405 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 406 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 407 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 408 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 409 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 410 nvidia,default-tap = <0x5>; 411 nvidia,default-trim = <0xb>; 412 status = "disabled"; 413 }; 414 415 sdmmc4: mmc@3460000 { 416 compatible = "nvidia,tegra186-sdhci"; 417 reg = <0x0 0x03460000 0x0 0x10000>; 418 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 420 clock-names = "sdhci"; 421 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 422 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 423 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 424 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 425 reset-names = "sdhci"; 426 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 427 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 428 interconnect-names = "dma-mem", "write"; 429 iommus = <&smmu TEGRA186_SID_SDMMC4>; 430 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 431 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 432 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 433 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 434 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 435 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 436 nvidia,default-tap = <0x9>; 437 nvidia,default-trim = <0x5>; 438 nvidia,dqs-trim = <63>; 439 mmc-hs400-1_8v; 440 supports-cqe; 441 status = "disabled"; 442 }; 443 444 hda@3510000 { 445 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 446 reg = <0x0 0x03510000 0x0 0x10000>; 447 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&bpmp TEGRA186_CLK_HDA>, 449 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 450 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 451 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 452 resets = <&bpmp TEGRA186_RESET_HDA>, 453 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 454 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 455 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 456 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 457 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 458 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 459 interconnect-names = "dma-mem", "write"; 460 iommus = <&smmu TEGRA186_SID_HDA>; 461 status = "disabled"; 462 }; 463 464 padctl: padctl@3520000 { 465 compatible = "nvidia,tegra186-xusb-padctl"; 466 reg = <0x0 0x03520000 0x0 0x1000>, 467 <0x0 0x03540000 0x0 0x1000>; 468 reg-names = "padctl", "ao"; 469 470 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 471 reset-names = "padctl"; 472 473 status = "disabled"; 474 475 pads { 476 usb2 { 477 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 478 clock-names = "trk"; 479 status = "disabled"; 480 481 lanes { 482 usb2-0 { 483 status = "disabled"; 484 #phy-cells = <0>; 485 }; 486 487 usb2-1 { 488 status = "disabled"; 489 #phy-cells = <0>; 490 }; 491 492 usb2-2 { 493 status = "disabled"; 494 #phy-cells = <0>; 495 }; 496 }; 497 }; 498 499 hsic { 500 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 501 clock-names = "trk"; 502 status = "disabled"; 503 504 lanes { 505 hsic-0 { 506 status = "disabled"; 507 #phy-cells = <0>; 508 }; 509 }; 510 }; 511 512 usb3 { 513 status = "disabled"; 514 515 lanes { 516 usb3-0 { 517 status = "disabled"; 518 #phy-cells = <0>; 519 }; 520 521 usb3-1 { 522 status = "disabled"; 523 #phy-cells = <0>; 524 }; 525 526 usb3-2 { 527 status = "disabled"; 528 #phy-cells = <0>; 529 }; 530 }; 531 }; 532 }; 533 534 ports { 535 usb2-0 { 536 status = "disabled"; 537 }; 538 539 usb2-1 { 540 status = "disabled"; 541 }; 542 543 usb2-2 { 544 status = "disabled"; 545 }; 546 547 hsic-0 { 548 status = "disabled"; 549 }; 550 551 usb3-0 { 552 status = "disabled"; 553 }; 554 555 usb3-1 { 556 status = "disabled"; 557 }; 558 559 usb3-2 { 560 status = "disabled"; 561 }; 562 }; 563 }; 564 565 usb@3530000 { 566 compatible = "nvidia,tegra186-xusb"; 567 reg = <0x0 0x03530000 0x0 0x8000>, 568 <0x0 0x03538000 0x0 0x1000>; 569 reg-names = "hcd", "fpci"; 570 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 573 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 574 <&bpmp TEGRA186_CLK_XUSB_SS>, 575 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 576 <&bpmp TEGRA186_CLK_CLK_M>, 577 <&bpmp TEGRA186_CLK_XUSB_FS>, 578 <&bpmp TEGRA186_CLK_PLLU>, 579 <&bpmp TEGRA186_CLK_CLK_M>, 580 <&bpmp TEGRA186_CLK_PLLE>; 581 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 582 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 583 "pll_u_480m", "clk_m", "pll_e"; 584 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 585 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 586 power-domain-names = "xusb_host", "xusb_ss"; 587 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 588 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 589 interconnect-names = "dma-mem", "write"; 590 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 status = "disabled"; 594 595 nvidia,xusb-padctl = <&padctl>; 596 }; 597 598 usb@3550000 { 599 compatible = "nvidia,tegra186-xudc"; 600 reg = <0x0 0x03550000 0x0 0x8000>, 601 <0x0 0x03558000 0x0 0x1000>; 602 reg-names = "base", "fpci"; 603 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 605 <&bpmp TEGRA186_CLK_XUSB_SS>, 606 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 607 <&bpmp TEGRA186_CLK_XUSB_FS>; 608 clock-names = "dev", "ss", "ss_src", "fs_src"; 609 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 610 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 611 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 612 power-domain-names = "dev", "ss"; 613 nvidia,xusb-padctl = <&padctl>; 614 status = "disabled"; 615 }; 616 617 fuse@3820000 { 618 compatible = "nvidia,tegra186-efuse"; 619 reg = <0x0 0x03820000 0x0 0x10000>; 620 clocks = <&bpmp TEGRA186_CLK_FUSE>; 621 clock-names = "fuse"; 622 }; 623 624 gic: interrupt-controller@3881000 { 625 compatible = "arm,gic-400"; 626 #interrupt-cells = <3>; 627 interrupt-controller; 628 reg = <0x0 0x03881000 0x0 0x1000>, 629 <0x0 0x03882000 0x0 0x2000>; 630 interrupts = <GIC_PPI 9 631 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 632 interrupt-parent = <&gic>; 633 }; 634 635 cec@3960000 { 636 compatible = "nvidia,tegra186-cec"; 637 reg = <0x0 0x03960000 0x0 0x10000>; 638 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&bpmp TEGRA186_CLK_CEC>; 640 clock-names = "cec"; 641 status = "disabled"; 642 }; 643 644 hsp_top0: hsp@3c00000 { 645 compatible = "nvidia,tegra186-hsp"; 646 reg = <0x0 0x03c00000 0x0 0xa0000>; 647 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 648 interrupt-names = "doorbell"; 649 #mbox-cells = <2>; 650 status = "disabled"; 651 }; 652 653 gen2_i2c: i2c@c240000 { 654 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 655 reg = <0x0 0x0c240000 0x0 0x10000>; 656 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 clocks = <&bpmp TEGRA186_CLK_I2C2>; 660 clock-names = "div-clk"; 661 resets = <&bpmp TEGRA186_RESET_I2C2>; 662 reset-names = "i2c"; 663 status = "disabled"; 664 }; 665 666 gen8_i2c: i2c@c250000 { 667 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 668 reg = <0x0 0x0c250000 0x0 0x10000>; 669 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 clocks = <&bpmp TEGRA186_CLK_I2C8>; 673 clock-names = "div-clk"; 674 resets = <&bpmp TEGRA186_RESET_I2C8>; 675 reset-names = "i2c"; 676 status = "disabled"; 677 }; 678 679 uartc: serial@c280000 { 680 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 681 reg = <0x0 0x0c280000 0x0 0x40>; 682 reg-shift = <2>; 683 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&bpmp TEGRA186_CLK_UARTC>; 685 clock-names = "serial"; 686 resets = <&bpmp TEGRA186_RESET_UARTC>; 687 reset-names = "serial"; 688 status = "disabled"; 689 }; 690 691 uartg: serial@c290000 { 692 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 693 reg = <0x0 0x0c290000 0x0 0x40>; 694 reg-shift = <2>; 695 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&bpmp TEGRA186_CLK_UARTG>; 697 clock-names = "serial"; 698 resets = <&bpmp TEGRA186_RESET_UARTG>; 699 reset-names = "serial"; 700 status = "disabled"; 701 }; 702 703 rtc: rtc@c2a0000 { 704 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 705 reg = <0 0x0c2a0000 0 0x10000>; 706 interrupt-parent = <&pmc>; 707 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 709 clock-names = "rtc"; 710 status = "disabled"; 711 }; 712 713 gpio_aon: gpio@c2f0000 { 714 compatible = "nvidia,tegra186-gpio-aon"; 715 reg-names = "security", "gpio"; 716 reg = <0x0 0xc2f0000 0x0 0x1000>, 717 <0x0 0xc2f1000 0x0 0x1000>; 718 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 719 gpio-controller; 720 #gpio-cells = <2>; 721 interrupt-controller; 722 #interrupt-cells = <2>; 723 }; 724 725 pmc: pmc@c360000 { 726 compatible = "nvidia,tegra186-pmc"; 727 reg = <0 0x0c360000 0 0x10000>, 728 <0 0x0c370000 0 0x10000>, 729 <0 0x0c380000 0 0x10000>, 730 <0 0x0c390000 0 0x10000>; 731 reg-names = "pmc", "wake", "aotag", "scratch"; 732 733 #interrupt-cells = <2>; 734 interrupt-controller; 735 736 sdmmc1_3v3: sdmmc1-3v3 { 737 pins = "sdmmc1-hv"; 738 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 739 }; 740 741 sdmmc1_1v8: sdmmc1-1v8 { 742 pins = "sdmmc1-hv"; 743 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 744 }; 745 746 sdmmc2_3v3: sdmmc2-3v3 { 747 pins = "sdmmc2-hv"; 748 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 749 }; 750 751 sdmmc2_1v8: sdmmc2-1v8 { 752 pins = "sdmmc2-hv"; 753 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 754 }; 755 756 sdmmc3_3v3: sdmmc3-3v3 { 757 pins = "sdmmc3-hv"; 758 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 759 }; 760 761 sdmmc3_1v8: sdmmc3-1v8 { 762 pins = "sdmmc3-hv"; 763 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 764 }; 765 }; 766 767 ccplex@e000000 { 768 compatible = "nvidia,tegra186-ccplex-cluster"; 769 reg = <0x0 0x0e000000 0x0 0x3fffff>; 770 771 nvidia,bpmp = <&bpmp>; 772 }; 773 774 pcie@10003000 { 775 compatible = "nvidia,tegra186-pcie"; 776 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 777 device_type = "pci"; 778 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 779 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 780 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 781 reg-names = "pads", "afi", "cs"; 782 783 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 784 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 785 interrupt-names = "intr", "msi"; 786 787 #interrupt-cells = <1>; 788 interrupt-map-mask = <0 0 0 0>; 789 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 790 791 bus-range = <0x00 0xff>; 792 #address-cells = <3>; 793 #size-cells = <2>; 794 795 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 796 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 797 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 798 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 799 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 800 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 801 802 clocks = <&bpmp TEGRA186_CLK_PCIE>, 803 <&bpmp TEGRA186_CLK_AFI>, 804 <&bpmp TEGRA186_CLK_PLLE>; 805 clock-names = "pex", "afi", "pll_e"; 806 807 resets = <&bpmp TEGRA186_RESET_PCIE>, 808 <&bpmp TEGRA186_RESET_AFI>, 809 <&bpmp TEGRA186_RESET_PCIEXCLK>; 810 reset-names = "pex", "afi", "pcie_x"; 811 812 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 813 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 814 interconnect-names = "dma-mem", "write"; 815 816 iommus = <&smmu TEGRA186_SID_AFI>; 817 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 818 iommu-map-mask = <0x0>; 819 820 status = "disabled"; 821 822 pci@1,0 { 823 device_type = "pci"; 824 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 825 reg = <0x000800 0 0 0 0>; 826 status = "disabled"; 827 828 #address-cells = <3>; 829 #size-cells = <2>; 830 ranges; 831 832 nvidia,num-lanes = <2>; 833 }; 834 835 pci@2,0 { 836 device_type = "pci"; 837 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 838 reg = <0x001000 0 0 0 0>; 839 status = "disabled"; 840 841 #address-cells = <3>; 842 #size-cells = <2>; 843 ranges; 844 845 nvidia,num-lanes = <1>; 846 }; 847 848 pci@3,0 { 849 device_type = "pci"; 850 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 851 reg = <0x001800 0 0 0 0>; 852 status = "disabled"; 853 854 #address-cells = <3>; 855 #size-cells = <2>; 856 ranges; 857 858 nvidia,num-lanes = <1>; 859 }; 860 }; 861 862 smmu: iommu@12000000 { 863 compatible = "arm,mmu-500"; 864 reg = <0 0x12000000 0 0x800000>; 865 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 930 stream-match-mask = <0x7f80>; 931 #global-interrupts = <1>; 932 #iommu-cells = <1>; 933 }; 934 935 host1x@13e00000 { 936 compatible = "nvidia,tegra186-host1x"; 937 reg = <0x0 0x13e00000 0x0 0x10000>, 938 <0x0 0x13e10000 0x0 0x10000>; 939 reg-names = "hypervisor", "vm"; 940 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 942 interrupt-names = "syncpt", "host1x"; 943 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 944 clock-names = "host1x"; 945 resets = <&bpmp TEGRA186_RESET_HOST1X>; 946 reset-names = "host1x"; 947 948 #address-cells = <1>; 949 #size-cells = <1>; 950 951 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 952 953 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 954 interconnect-names = "dma-mem"; 955 956 iommus = <&smmu TEGRA186_SID_HOST1X>; 957 958 dpaux1: dpaux@15040000 { 959 compatible = "nvidia,tegra186-dpaux"; 960 reg = <0x15040000 0x10000>; 961 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 963 <&bpmp TEGRA186_CLK_PLLDP>; 964 clock-names = "dpaux", "parent"; 965 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 966 reset-names = "dpaux"; 967 status = "disabled"; 968 969 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 970 971 state_dpaux1_aux: pinmux-aux { 972 groups = "dpaux-io"; 973 function = "aux"; 974 }; 975 976 state_dpaux1_i2c: pinmux-i2c { 977 groups = "dpaux-io"; 978 function = "i2c"; 979 }; 980 981 state_dpaux1_off: pinmux-off { 982 groups = "dpaux-io"; 983 function = "off"; 984 }; 985 986 i2c-bus { 987 #address-cells = <1>; 988 #size-cells = <0>; 989 }; 990 }; 991 992 display-hub@15200000 { 993 compatible = "nvidia,tegra186-display"; 994 reg = <0x15200000 0x00040000>; 995 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 996 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 997 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 998 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 999 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1000 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1001 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1002 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1003 "wgrp3", "wgrp4", "wgrp5"; 1004 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1005 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1006 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1007 clock-names = "disp", "dsc", "hub"; 1008 status = "disabled"; 1009 1010 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1011 1012 #address-cells = <1>; 1013 #size-cells = <1>; 1014 1015 ranges = <0x15200000 0x15200000 0x40000>; 1016 1017 display@15200000 { 1018 compatible = "nvidia,tegra186-dc"; 1019 reg = <0x15200000 0x10000>; 1020 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1022 clock-names = "dc"; 1023 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1024 reset-names = "dc"; 1025 1026 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1027 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1028 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1029 interconnect-names = "dma-mem", "read-1"; 1030 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1031 1032 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1033 nvidia,head = <0>; 1034 }; 1035 1036 display@15210000 { 1037 compatible = "nvidia,tegra186-dc"; 1038 reg = <0x15210000 0x10000>; 1039 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1040 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1041 clock-names = "dc"; 1042 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1043 reset-names = "dc"; 1044 1045 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1046 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1047 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1048 interconnect-names = "dma-mem", "read-1"; 1049 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1050 1051 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1052 nvidia,head = <1>; 1053 }; 1054 1055 display@15220000 { 1056 compatible = "nvidia,tegra186-dc"; 1057 reg = <0x15220000 0x10000>; 1058 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1060 clock-names = "dc"; 1061 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1062 reset-names = "dc"; 1063 1064 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1065 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1066 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1067 interconnect-names = "dma-mem", "read-1"; 1068 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1069 1070 nvidia,outputs = <&sor0 &sor1>; 1071 nvidia,head = <2>; 1072 }; 1073 }; 1074 1075 dsia: dsi@15300000 { 1076 compatible = "nvidia,tegra186-dsi"; 1077 reg = <0x15300000 0x10000>; 1078 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1079 clocks = <&bpmp TEGRA186_CLK_DSI>, 1080 <&bpmp TEGRA186_CLK_DSIA_LP>, 1081 <&bpmp TEGRA186_CLK_PLLD>; 1082 clock-names = "dsi", "lp", "parent"; 1083 resets = <&bpmp TEGRA186_RESET_DSI>; 1084 reset-names = "dsi"; 1085 status = "disabled"; 1086 1087 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1088 }; 1089 1090 vic@15340000 { 1091 compatible = "nvidia,tegra186-vic"; 1092 reg = <0x15340000 0x40000>; 1093 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1094 clocks = <&bpmp TEGRA186_CLK_VIC>; 1095 clock-names = "vic"; 1096 resets = <&bpmp TEGRA186_RESET_VIC>; 1097 reset-names = "vic"; 1098 1099 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1100 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1101 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1102 interconnect-names = "dma-mem", "write"; 1103 iommus = <&smmu TEGRA186_SID_VIC>; 1104 }; 1105 1106 dsib: dsi@15400000 { 1107 compatible = "nvidia,tegra186-dsi"; 1108 reg = <0x15400000 0x10000>; 1109 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1111 <&bpmp TEGRA186_CLK_DSIB_LP>, 1112 <&bpmp TEGRA186_CLK_PLLD>; 1113 clock-names = "dsi", "lp", "parent"; 1114 resets = <&bpmp TEGRA186_RESET_DSIB>; 1115 reset-names = "dsi"; 1116 status = "disabled"; 1117 1118 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1119 }; 1120 1121 sor0: sor@15540000 { 1122 compatible = "nvidia,tegra186-sor"; 1123 reg = <0x15540000 0x10000>; 1124 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1126 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1127 <&bpmp TEGRA186_CLK_PLLD2>, 1128 <&bpmp TEGRA186_CLK_PLLDP>, 1129 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1130 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1131 clock-names = "sor", "out", "parent", "dp", "safe", 1132 "pad"; 1133 resets = <&bpmp TEGRA186_RESET_SOR0>; 1134 reset-names = "sor"; 1135 pinctrl-0 = <&state_dpaux_aux>; 1136 pinctrl-1 = <&state_dpaux_i2c>; 1137 pinctrl-2 = <&state_dpaux_off>; 1138 pinctrl-names = "aux", "i2c", "off"; 1139 status = "disabled"; 1140 1141 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1142 nvidia,interface = <0>; 1143 }; 1144 1145 sor1: sor@15580000 { 1146 compatible = "nvidia,tegra186-sor"; 1147 reg = <0x15580000 0x10000>; 1148 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1150 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1151 <&bpmp TEGRA186_CLK_PLLD3>, 1152 <&bpmp TEGRA186_CLK_PLLDP>, 1153 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1154 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1155 clock-names = "sor", "out", "parent", "dp", "safe", 1156 "pad"; 1157 resets = <&bpmp TEGRA186_RESET_SOR1>; 1158 reset-names = "sor"; 1159 pinctrl-0 = <&state_dpaux1_aux>; 1160 pinctrl-1 = <&state_dpaux1_i2c>; 1161 pinctrl-2 = <&state_dpaux1_off>; 1162 pinctrl-names = "aux", "i2c", "off"; 1163 status = "disabled"; 1164 1165 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1166 nvidia,interface = <1>; 1167 }; 1168 1169 dpaux: dpaux@155c0000 { 1170 compatible = "nvidia,tegra186-dpaux"; 1171 reg = <0x155c0000 0x10000>; 1172 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1173 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1174 <&bpmp TEGRA186_CLK_PLLDP>; 1175 clock-names = "dpaux", "parent"; 1176 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1177 reset-names = "dpaux"; 1178 status = "disabled"; 1179 1180 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1181 1182 state_dpaux_aux: pinmux-aux { 1183 groups = "dpaux-io"; 1184 function = "aux"; 1185 }; 1186 1187 state_dpaux_i2c: pinmux-i2c { 1188 groups = "dpaux-io"; 1189 function = "i2c"; 1190 }; 1191 1192 state_dpaux_off: pinmux-off { 1193 groups = "dpaux-io"; 1194 function = "off"; 1195 }; 1196 1197 i2c-bus { 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 }; 1201 }; 1202 1203 padctl@15880000 { 1204 compatible = "nvidia,tegra186-dsi-padctl"; 1205 reg = <0x15880000 0x10000>; 1206 resets = <&bpmp TEGRA186_RESET_DSI>; 1207 reset-names = "dsi"; 1208 status = "disabled"; 1209 }; 1210 1211 dsic: dsi@15900000 { 1212 compatible = "nvidia,tegra186-dsi"; 1213 reg = <0x15900000 0x10000>; 1214 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1215 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1216 <&bpmp TEGRA186_CLK_DSIC_LP>, 1217 <&bpmp TEGRA186_CLK_PLLD>; 1218 clock-names = "dsi", "lp", "parent"; 1219 resets = <&bpmp TEGRA186_RESET_DSIC>; 1220 reset-names = "dsi"; 1221 status = "disabled"; 1222 1223 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1224 }; 1225 1226 dsid: dsi@15940000 { 1227 compatible = "nvidia,tegra186-dsi"; 1228 reg = <0x15940000 0x10000>; 1229 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1230 clocks = <&bpmp TEGRA186_CLK_DSID>, 1231 <&bpmp TEGRA186_CLK_DSID_LP>, 1232 <&bpmp TEGRA186_CLK_PLLD>; 1233 clock-names = "dsi", "lp", "parent"; 1234 resets = <&bpmp TEGRA186_RESET_DSID>; 1235 reset-names = "dsi"; 1236 status = "disabled"; 1237 1238 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1239 }; 1240 }; 1241 1242 gpu@17000000 { 1243 compatible = "nvidia,gp10b"; 1244 reg = <0x0 0x17000000 0x0 0x1000000>, 1245 <0x0 0x18000000 0x0 0x1000000>; 1246 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1248 interrupt-names = "stall", "nonstall"; 1249 1250 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1251 <&bpmp TEGRA186_CLK_GPU>; 1252 clock-names = "gpu", "pwr"; 1253 resets = <&bpmp TEGRA186_RESET_GPU>; 1254 reset-names = "gpu"; 1255 status = "disabled"; 1256 1257 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1258 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1259 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1260 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1261 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1262 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1263 }; 1264 1265 sram@30000000 { 1266 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1267 reg = <0x0 0x30000000 0x0 0x50000>; 1268 #address-cells = <1>; 1269 #size-cells = <1>; 1270 ranges = <0x0 0x0 0x30000000 0x50000>; 1271 1272 cpu_bpmp_tx: sram@4e000 { 1273 reg = <0x4e000 0x1000>; 1274 label = "cpu-bpmp-tx"; 1275 pool; 1276 }; 1277 1278 cpu_bpmp_rx: sram@4f000 { 1279 reg = <0x4f000 0x1000>; 1280 label = "cpu-bpmp-rx"; 1281 pool; 1282 }; 1283 }; 1284 1285 bpmp: bpmp { 1286 compatible = "nvidia,tegra186-bpmp"; 1287 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1288 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1289 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1290 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1291 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1292 iommus = <&smmu TEGRA186_SID_BPMP>; 1293 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1294 TEGRA_HSP_DB_MASTER_BPMP>; 1295 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1296 #clock-cells = <1>; 1297 #reset-cells = <1>; 1298 #power-domain-cells = <1>; 1299 1300 bpmp_i2c: i2c { 1301 compatible = "nvidia,tegra186-bpmp-i2c"; 1302 nvidia,bpmp-bus-id = <5>; 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 status = "disabled"; 1306 }; 1307 1308 bpmp_thermal: thermal { 1309 compatible = "nvidia,tegra186-bpmp-thermal"; 1310 #thermal-sensor-cells = <1>; 1311 }; 1312 }; 1313 1314 cpus { 1315 #address-cells = <1>; 1316 #size-cells = <0>; 1317 1318 cpu@0 { 1319 compatible = "nvidia,tegra186-denver"; 1320 device_type = "cpu"; 1321 i-cache-size = <0x20000>; 1322 i-cache-line-size = <64>; 1323 i-cache-sets = <512>; 1324 d-cache-size = <0x10000>; 1325 d-cache-line-size = <64>; 1326 d-cache-sets = <256>; 1327 next-level-cache = <&L2_DENVER>; 1328 reg = <0x000>; 1329 }; 1330 1331 cpu@1 { 1332 compatible = "nvidia,tegra186-denver"; 1333 device_type = "cpu"; 1334 i-cache-size = <0x20000>; 1335 i-cache-line-size = <64>; 1336 i-cache-sets = <512>; 1337 d-cache-size = <0x10000>; 1338 d-cache-line-size = <64>; 1339 d-cache-sets = <256>; 1340 next-level-cache = <&L2_DENVER>; 1341 reg = <0x001>; 1342 }; 1343 1344 cpu@2 { 1345 compatible = "arm,cortex-a57"; 1346 device_type = "cpu"; 1347 i-cache-size = <0xC000>; 1348 i-cache-line-size = <64>; 1349 i-cache-sets = <256>; 1350 d-cache-size = <0x8000>; 1351 d-cache-line-size = <64>; 1352 d-cache-sets = <256>; 1353 next-level-cache = <&L2_A57>; 1354 reg = <0x100>; 1355 }; 1356 1357 cpu@3 { 1358 compatible = "arm,cortex-a57"; 1359 device_type = "cpu"; 1360 i-cache-size = <0xC000>; 1361 i-cache-line-size = <64>; 1362 i-cache-sets = <256>; 1363 d-cache-size = <0x8000>; 1364 d-cache-line-size = <64>; 1365 d-cache-sets = <256>; 1366 next-level-cache = <&L2_A57>; 1367 reg = <0x101>; 1368 }; 1369 1370 cpu@4 { 1371 compatible = "arm,cortex-a57"; 1372 device_type = "cpu"; 1373 i-cache-size = <0xC000>; 1374 i-cache-line-size = <64>; 1375 i-cache-sets = <256>; 1376 d-cache-size = <0x8000>; 1377 d-cache-line-size = <64>; 1378 d-cache-sets = <256>; 1379 next-level-cache = <&L2_A57>; 1380 reg = <0x102>; 1381 }; 1382 1383 cpu@5 { 1384 compatible = "arm,cortex-a57"; 1385 device_type = "cpu"; 1386 i-cache-size = <0xC000>; 1387 i-cache-line-size = <64>; 1388 i-cache-sets = <256>; 1389 d-cache-size = <0x8000>; 1390 d-cache-line-size = <64>; 1391 d-cache-sets = <256>; 1392 next-level-cache = <&L2_A57>; 1393 reg = <0x103>; 1394 }; 1395 1396 L2_DENVER: l2-cache0 { 1397 compatible = "cache"; 1398 cache-unified; 1399 cache-level = <2>; 1400 cache-size = <0x200000>; 1401 cache-line-size = <64>; 1402 cache-sets = <2048>; 1403 }; 1404 1405 L2_A57: l2-cache1 { 1406 compatible = "cache"; 1407 cache-unified; 1408 cache-level = <2>; 1409 cache-size = <0x200000>; 1410 cache-line-size = <64>; 1411 cache-sets = <2048>; 1412 }; 1413 }; 1414 1415 thermal-zones { 1416 a57 { 1417 polling-delay = <0>; 1418 polling-delay-passive = <1000>; 1419 1420 thermal-sensors = 1421 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1422 1423 trips { 1424 critical { 1425 temperature = <101000>; 1426 hysteresis = <0>; 1427 type = "critical"; 1428 }; 1429 }; 1430 1431 cooling-maps { 1432 }; 1433 }; 1434 1435 denver { 1436 polling-delay = <0>; 1437 polling-delay-passive = <1000>; 1438 1439 thermal-sensors = 1440 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1441 1442 trips { 1443 critical { 1444 temperature = <101000>; 1445 hysteresis = <0>; 1446 type = "critical"; 1447 }; 1448 }; 1449 1450 cooling-maps { 1451 }; 1452 }; 1453 1454 gpu { 1455 polling-delay = <0>; 1456 polling-delay-passive = <1000>; 1457 1458 thermal-sensors = 1459 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1460 1461 trips { 1462 critical { 1463 temperature = <101000>; 1464 hysteresis = <0>; 1465 type = "critical"; 1466 }; 1467 }; 1468 1469 cooling-maps { 1470 }; 1471 }; 1472 1473 pll { 1474 polling-delay = <0>; 1475 polling-delay-passive = <1000>; 1476 1477 thermal-sensors = 1478 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1479 1480 trips { 1481 critical { 1482 temperature = <101000>; 1483 hysteresis = <0>; 1484 type = "critical"; 1485 }; 1486 }; 1487 1488 cooling-maps { 1489 }; 1490 }; 1491 1492 always_on { 1493 polling-delay = <0>; 1494 polling-delay-passive = <1000>; 1495 1496 thermal-sensors = 1497 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1498 1499 trips { 1500 critical { 1501 temperature = <101000>; 1502 hysteresis = <0>; 1503 type = "critical"; 1504 }; 1505 }; 1506 1507 cooling-maps { 1508 }; 1509 }; 1510 }; 1511 1512 timer { 1513 compatible = "arm,armv8-timer"; 1514 interrupts = <GIC_PPI 13 1515 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1516 <GIC_PPI 14 1517 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1518 <GIC_PPI 11 1519 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1520 <GIC_PPI 10 1521 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1522 interrupt-parent = <&gic>; 1523 always-on; 1524 }; 1525}; 1526