1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2020 Marvell International Ltd. 4 * 5 * Device tree for the CN9132-DB board. 6 */ 7 8#include "cn9131-db.dtsi" 9 10/ { 11 compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130", 12 "marvell,armada-ap807-quad", "marvell,armada-ap807"; 13 14 aliases { 15 gpio5 = &cp2_gpio1; 16 gpio6 = &cp2_gpio2; 17 ethernet5 = &cp2_eth0; 18 }; 19 20 cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 { 21 compatible = "regulator-fixed"; 22 regulator-name = "cp2-xhci0-vbus"; 23 regulator-min-microvolt = <5000000>; 24 regulator-max-microvolt = <5000000>; 25 enable-active-high; 26 gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>; 27 }; 28 29 cp2_usb3_0_phy0: cp2_usb3_phy0 { 30 compatible = "usb-nop-xceiv"; 31 vcc-supply = <&cp2_reg_usb3_vbus0>; 32 }; 33 34 cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 { 35 compatible = "regulator-fixed"; 36 regulator-name = "cp2-xhci1-vbus"; 37 regulator-min-microvolt = <5000000>; 38 regulator-max-microvolt = <5000000>; 39 enable-active-high; 40 gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>; 41 }; 42 43 cp2_usb3_0_phy1: cp2_usb3_phy1 { 44 compatible = "usb-nop-xceiv"; 45 vcc-supply = <&cp2_reg_usb3_vbus1>; 46 }; 47 48 cp2_reg_sd_vccq: cp2_sd_vccq@0 { 49 compatible = "regulator-gpio"; 50 regulator-name = "cp2_sd_vcc"; 51 regulator-min-microvolt = <1800000>; 52 regulator-max-microvolt = <3300000>; 53 gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>; 54 states = <1800000 0x1 3300000 0x0>; 55 }; 56 57 cp2_sfp_eth0: sfp-eth0 { 58 compatible = "sff,sfp"; 59 i2c-bus = <&cp2_sfpp0_i2c>; 60 los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>; 61 mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>; 62 tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>; 63 tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>; 64 /* 65 * SFP cages are unconnected on early PCBs because of an the I2C 66 * lanes not being connected. Prevent the port for being 67 * unusable by disabling the SFP node. 68 */ 69 status = "disabled"; 70 }; 71}; 72 73/* 74 * Instantiate the second slave CP115 75 */ 76 77#define CP11X_NAME cp2 78#define CP11X_BASE f6000000 79#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000)) 80#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 81#define CP11X_PCIE0_BASE f6600000 82#define CP11X_PCIE1_BASE f6620000 83#define CP11X_PCIE2_BASE f6640000 84 85#include "armada-cp115.dtsi" 86 87#undef CP11X_NAME 88#undef CP11X_BASE 89#undef CP11X_PCIEx_MEM_BASE 90#undef CP11X_PCIEx_MEM_SIZE 91#undef CP11X_PCIE0_BASE 92#undef CP11X_PCIE1_BASE 93#undef CP11X_PCIE2_BASE 94 95&cp2_crypto { 96 status = "disabled"; 97}; 98 99&cp2_ethernet { 100 status = "okay"; 101}; 102 103/* SLM-1521-V2, CON9 */ 104&cp2_eth0 { 105 status = "disabled"; 106 phy-mode = "10gbase-r"; 107 /* Generic PHY, providing serdes lanes */ 108 phys = <&cp2_comphy4 0>; 109 managed = "in-band-status"; 110 sfp = <&cp2_sfp_eth0>; 111}; 112 113&cp2_gpio1 { 114 status = "okay"; 115}; 116 117&cp2_gpio2 { 118 status = "okay"; 119}; 120 121&cp2_i2c0 { 122 clock-frequency = <100000>; 123 124 /* SLM-1521-V2 - U3 */ 125 i2c-mux@72 { 126 compatible = "nxp,pca9544"; 127 #address-cells = <1>; 128 #size-cells = <0>; 129 reg = <0x72>; 130 cp2_sfpp0_i2c: i2c@0 { 131 #address-cells = <1>; 132 #size-cells = <0>; 133 reg = <0>; 134 }; 135 136 i2c@1 { 137 #address-cells = <1>; 138 #size-cells = <0>; 139 reg = <1>; 140 /* U12 */ 141 cp2_module_expander1: pca9555@21 { 142 compatible = "nxp,pca9555"; 143 pinctrl-names = "default"; 144 gpio-controller; 145 #gpio-cells = <2>; 146 reg = <0x21>; 147 }; 148 }; 149 }; 150}; 151 152/* SLM-1521-V2, CON6 */ 153&cp2_pcie0 { 154 status = "okay"; 155 num-lanes = <2>; 156 num-viewport = <8>; 157 /* Generic PHY, providing serdes lanes */ 158 phys = <&cp2_comphy0 0 159 &cp2_comphy1 0>; 160}; 161 162/* SLM-1521-V2, CON8 */ 163&cp2_pcie2 { 164 status = "okay"; 165 num-lanes = <1>; 166 num-viewport = <8>; 167 /* Generic PHY, providing serdes lanes */ 168 phys = <&cp2_comphy5 2>; 169}; 170 171&cp2_sata0 { 172 status = "okay"; 173 174 /* SLM-1521-V2, CON4 */ 175 sata-port@0 { 176 /* Generic PHY, providing serdes lanes */ 177 phys = <&cp2_comphy2 0>; 178 }; 179}; 180 181/* CON 2 on SLM-1683 - microSD */ 182&cp2_sdhci0 { 183 status = "okay"; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&cp2_sdhci_pins>; 186 bus-width = <4>; 187 cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>; 188 vqmmc-supply = <&cp2_reg_sd_vccq>; 189}; 190 191&cp2_syscon0 { 192 cp2_pinctrl: pinctrl { 193 compatible = "marvell,cp115-standalone-pinctrl"; 194 195 cp2_i2c0_pins: cp2-i2c-pins-0 { 196 marvell,pins = "mpp37", "mpp38"; 197 marvell,function = "i2c0"; 198 }; 199 cp2_sdhci_pins: cp2-sdhi-pins-0 { 200 marvell,pins = "mpp56", "mpp57", "mpp58", 201 "mpp59", "mpp60", "mpp61"; 202 marvell,function = "sdio"; 203 }; 204 }; 205}; 206 207&cp2_utmi { 208 status = "okay"; 209}; 210 211&cp2_usb3_0 { 212 status = "okay"; 213 usb-phy = <&cp2_usb3_0_phy0>; 214 phys = <&cp2_utmi0>; 215 phy-names = "usb"; 216 dr_mode = "host"; 217}; 218 219/* SLM-1521-V2, CON11 */ 220&cp2_usb3_1 { 221 status = "okay"; 222 usb-phy = <&cp2_usb3_0_phy1>; 223 /* Generic PHY, providing serdes lanes */ 224 phys = <&cp2_comphy3 1>, <&cp2_utmi1>; 225 phy-names = "usb", "utmi"; 226 dr_mode = "host"; 227}; 228