1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Hisilicon Hi3660 SoC 4 * 5 * Copyright (C) 2016, Hisilicon Ltd. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/hi3660-clock.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/ { 13 compatible = "hisilicon,hi3660"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 psci { 19 compatible = "arm,psci-0.2"; 20 method = "smc"; 21 }; 22 23 cpus { 24 #address-cells = <2>; 25 #size-cells = <0>; 26 27 cpu-map { 28 cluster0 { 29 core0 { 30 cpu = <&cpu0>; 31 }; 32 core1 { 33 cpu = <&cpu1>; 34 }; 35 core2 { 36 cpu = <&cpu2>; 37 }; 38 core3 { 39 cpu = <&cpu3>; 40 }; 41 }; 42 cluster1 { 43 core0 { 44 cpu = <&cpu4>; 45 }; 46 core1 { 47 cpu = <&cpu5>; 48 }; 49 core2 { 50 cpu = <&cpu6>; 51 }; 52 core3 { 53 cpu = <&cpu7>; 54 }; 55 }; 56 }; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 device_type = "cpu"; 61 reg = <0x0 0x0>; 62 enable-method = "psci"; 63 next-level-cache = <&A53_L2>; 64 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 65 capacity-dmips-mhz = <592>; 66 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 67 operating-points-v2 = <&cluster0_opp>; 68 #cooling-cells = <2>; 69 dynamic-power-coefficient = <110>; 70 }; 71 72 cpu1: cpu@1 { 73 compatible = "arm,cortex-a53", "arm,armv8"; 74 device_type = "cpu"; 75 reg = <0x0 0x1>; 76 enable-method = "psci"; 77 next-level-cache = <&A53_L2>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 79 capacity-dmips-mhz = <592>; 80 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 81 operating-points-v2 = <&cluster0_opp>; 82 }; 83 84 cpu2: cpu@2 { 85 compatible = "arm,cortex-a53", "arm,armv8"; 86 device_type = "cpu"; 87 reg = <0x0 0x2>; 88 enable-method = "psci"; 89 next-level-cache = <&A53_L2>; 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 91 capacity-dmips-mhz = <592>; 92 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 93 operating-points-v2 = <&cluster0_opp>; 94 }; 95 96 cpu3: cpu@3 { 97 compatible = "arm,cortex-a53", "arm,armv8"; 98 device_type = "cpu"; 99 reg = <0x0 0x3>; 100 enable-method = "psci"; 101 next-level-cache = <&A53_L2>; 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 103 capacity-dmips-mhz = <592>; 104 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 105 operating-points-v2 = <&cluster0_opp>; 106 }; 107 108 cpu4: cpu@100 { 109 compatible = "arm,cortex-a73", "arm,armv8"; 110 device_type = "cpu"; 111 reg = <0x0 0x100>; 112 enable-method = "psci"; 113 next-level-cache = <&A73_L2>; 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 115 capacity-dmips-mhz = <1024>; 116 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 117 operating-points-v2 = <&cluster1_opp>; 118 #cooling-cells = <2>; 119 dynamic-power-coefficient = <550>; 120 }; 121 122 cpu5: cpu@101 { 123 compatible = "arm,cortex-a73", "arm,armv8"; 124 device_type = "cpu"; 125 reg = <0x0 0x101>; 126 enable-method = "psci"; 127 next-level-cache = <&A73_L2>; 128 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 129 capacity-dmips-mhz = <1024>; 130 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 131 operating-points-v2 = <&cluster1_opp>; 132 }; 133 134 cpu6: cpu@102 { 135 compatible = "arm,cortex-a73", "arm,armv8"; 136 device_type = "cpu"; 137 reg = <0x0 0x102>; 138 enable-method = "psci"; 139 next-level-cache = <&A73_L2>; 140 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 141 capacity-dmips-mhz = <1024>; 142 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 143 operating-points-v2 = <&cluster1_opp>; 144 }; 145 146 cpu7: cpu@103 { 147 compatible = "arm,cortex-a73", "arm,armv8"; 148 device_type = "cpu"; 149 reg = <0x0 0x103>; 150 enable-method = "psci"; 151 next-level-cache = <&A73_L2>; 152 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 153 capacity-dmips-mhz = <1024>; 154 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 155 operating-points-v2 = <&cluster1_opp>; 156 }; 157 158 idle-states { 159 entry-method = "psci"; 160 161 CPU_SLEEP: cpu-sleep { 162 compatible = "arm,idle-state"; 163 local-timer-stop; 164 arm,psci-suspend-param = <0x0010000>; 165 entry-latency-us = <40>; 166 exit-latency-us = <70>; 167 min-residency-us = <3000>; 168 }; 169 170 CLUSTER_SLEEP_0: cluster-sleep-0 { 171 compatible = "arm,idle-state"; 172 local-timer-stop; 173 arm,psci-suspend-param = <0x1010000>; 174 entry-latency-us = <500>; 175 exit-latency-us = <5000>; 176 min-residency-us = <20000>; 177 }; 178 179 CLUSTER_SLEEP_1: cluster-sleep-1 { 180 compatible = "arm,idle-state"; 181 local-timer-stop; 182 arm,psci-suspend-param = <0x1010000>; 183 entry-latency-us = <1000>; 184 exit-latency-us = <5000>; 185 min-residency-us = <20000>; 186 }; 187 }; 188 189 A53_L2: l2-cache0 { 190 compatible = "cache"; 191 }; 192 193 A73_L2: l2-cache1 { 194 compatible = "cache"; 195 }; 196 }; 197 198 cluster0_opp: opp_table0 { 199 compatible = "operating-points-v2"; 200 opp-shared; 201 202 opp00 { 203 opp-hz = /bits/ 64 <533000000>; 204 opp-microvolt = <700000>; 205 clock-latency-ns = <300000>; 206 }; 207 208 opp01 { 209 opp-hz = /bits/ 64 <999000000>; 210 opp-microvolt = <800000>; 211 clock-latency-ns = <300000>; 212 }; 213 214 opp02 { 215 opp-hz = /bits/ 64 <1402000000>; 216 opp-microvolt = <900000>; 217 clock-latency-ns = <300000>; 218 }; 219 220 opp03 { 221 opp-hz = /bits/ 64 <1709000000>; 222 opp-microvolt = <1000000>; 223 clock-latency-ns = <300000>; 224 }; 225 226 opp04 { 227 opp-hz = /bits/ 64 <1844000000>; 228 opp-microvolt = <1100000>; 229 clock-latency-ns = <300000>; 230 }; 231 }; 232 233 cluster1_opp: opp_table1 { 234 compatible = "operating-points-v2"; 235 opp-shared; 236 237 opp10 { 238 opp-hz = /bits/ 64 <903000000>; 239 opp-microvolt = <700000>; 240 clock-latency-ns = <300000>; 241 }; 242 243 opp11 { 244 opp-hz = /bits/ 64 <1421000000>; 245 opp-microvolt = <800000>; 246 clock-latency-ns = <300000>; 247 }; 248 249 opp12 { 250 opp-hz = /bits/ 64 <1805000000>; 251 opp-microvolt = <900000>; 252 clock-latency-ns = <300000>; 253 }; 254 255 opp13 { 256 opp-hz = /bits/ 64 <2112000000>; 257 opp-microvolt = <1000000>; 258 clock-latency-ns = <300000>; 259 }; 260 261 opp14 { 262 opp-hz = /bits/ 64 <2362000000>; 263 opp-microvolt = <1100000>; 264 clock-latency-ns = <300000>; 265 }; 266 }; 267 268 gic: interrupt-controller@e82b0000 { 269 compatible = "arm,gic-400"; 270 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 271 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 272 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 273 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 274 #address-cells = <0>; 275 #interrupt-cells = <3>; 276 interrupt-controller; 277 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 278 IRQ_TYPE_LEVEL_HIGH)>; 279 }; 280 281 a53-pmu { 282 compatible = "arm,cortex-a53-pmu"; 283 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 287 interrupt-affinity = <&cpu0>, 288 <&cpu1>, 289 <&cpu2>, 290 <&cpu3>; 291 }; 292 293 a73-pmu { 294 compatible = "arm,cortex-a73-pmu"; 295 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-affinity = <&cpu4>, 300 <&cpu5>, 301 <&cpu6>, 302 <&cpu7>; 303 }; 304 305 timer { 306 compatible = "arm,armv8-timer"; 307 interrupt-parent = <&gic>; 308 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 309 IRQ_TYPE_LEVEL_LOW)>, 310 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 311 IRQ_TYPE_LEVEL_LOW)>, 312 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 313 IRQ_TYPE_LEVEL_LOW)>, 314 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 315 IRQ_TYPE_LEVEL_LOW)>; 316 }; 317 318 soc { 319 compatible = "simple-bus"; 320 #address-cells = <2>; 321 #size-cells = <2>; 322 ranges; 323 324 crg_ctrl: crg_ctrl@fff35000 { 325 compatible = "hisilicon,hi3660-crgctrl", "syscon"; 326 reg = <0x0 0xfff35000 0x0 0x1000>; 327 #clock-cells = <1>; 328 }; 329 330 crg_rst: crg_rst_controller { 331 compatible = "hisilicon,hi3660-reset"; 332 #reset-cells = <2>; 333 hisi,rst-syscon = <&crg_ctrl>; 334 }; 335 336 337 pctrl: pctrl@e8a09000 { 338 compatible = "hisilicon,hi3660-pctrl", "syscon"; 339 reg = <0x0 0xe8a09000 0x0 0x2000>; 340 #clock-cells = <1>; 341 }; 342 343 pmuctrl: crg_ctrl@fff34000 { 344 compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 345 reg = <0x0 0xfff34000 0x0 0x1000>; 346 #clock-cells = <1>; 347 }; 348 349 sctrl: sctrl@fff0a000 { 350 compatible = "hisilicon,hi3660-sctrl", "syscon"; 351 reg = <0x0 0xfff0a000 0x0 0x1000>; 352 #clock-cells = <1>; 353 }; 354 355 iomcu: iomcu@ffd7e000 { 356 compatible = "hisilicon,hi3660-iomcu", "syscon"; 357 reg = <0x0 0xffd7e000 0x0 0x1000>; 358 #clock-cells = <1>; 359 360 }; 361 362 iomcu_rst: reset { 363 compatible = "hisilicon,hi3660-reset"; 364 hisi,rst-syscon = <&iomcu>; 365 #reset-cells = <2>; 366 }; 367 368 mailbox: mailbox@e896b000 { 369 compatible = "hisilicon,hi3660-mbox"; 370 reg = <0x0 0xe896b000 0x0 0x1000>; 371 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 373 #mbox-cells = <3>; 374 }; 375 376 stub_clock: stub_clock@e896b500 { 377 compatible = "hisilicon,hi3660-stub-clk"; 378 reg = <0x0 0xe896b500 0x0 0x0100>; 379 #clock-cells = <1>; 380 mboxes = <&mailbox 13 3 0>; 381 }; 382 383 dual_timer0: timer@fff14000 { 384 compatible = "arm,sp804", "arm,primecell"; 385 reg = <0x0 0xfff14000 0x0 0x1000>; 386 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&crg_ctrl HI3660_OSC32K>, 389 <&crg_ctrl HI3660_OSC32K>, 390 <&crg_ctrl HI3660_OSC32K>; 391 clock-names = "timer1", "timer2", "apb_pclk"; 392 }; 393 394 i2c0: i2c@ffd71000 { 395 compatible = "snps,designware-i2c"; 396 reg = <0x0 0xffd71000 0x0 0x1000>; 397 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 clock-frequency = <400000>; 401 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 402 resets = <&iomcu_rst 0x20 3>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 405 status = "disabled"; 406 }; 407 408 i2c1: i2c@ffd72000 { 409 compatible = "snps,designware-i2c"; 410 reg = <0x0 0xffd72000 0x0 0x1000>; 411 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 clock-frequency = <400000>; 415 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 416 resets = <&iomcu_rst 0x20 4>; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 419 status = "disabled"; 420 }; 421 422 i2c3: i2c@fdf0c000 { 423 compatible = "snps,designware-i2c"; 424 reg = <0x0 0xfdf0c000 0x0 0x1000>; 425 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 clock-frequency = <400000>; 429 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 430 resets = <&crg_rst 0x78 7>; 431 pinctrl-names = "default"; 432 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 433 status = "disabled"; 434 }; 435 436 i2c7: i2c@fdf0b000 { 437 compatible = "snps,designware-i2c"; 438 reg = <0x0 0xfdf0b000 0x0 0x1000>; 439 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 clock-frequency = <400000>; 443 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 444 resets = <&crg_rst 0x60 14>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 447 status = "disabled"; 448 }; 449 450 uart0: serial@fdf02000 { 451 compatible = "arm,pl011", "arm,primecell"; 452 reg = <0x0 0xfdf02000 0x0 0x1000>; 453 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 455 <&crg_ctrl HI3660_PCLK>; 456 clock-names = "uartclk", "apb_pclk"; 457 pinctrl-names = "default"; 458 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 459 status = "disabled"; 460 }; 461 462 uart1: serial@fdf00000 { 463 compatible = "arm,pl011", "arm,primecell"; 464 reg = <0x0 0xfdf00000 0x0 0x1000>; 465 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 467 <&crg_ctrl HI3660_CLK_GATE_UART1>; 468 clock-names = "uartclk", "apb_pclk"; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 471 status = "disabled"; 472 }; 473 474 uart2: serial@fdf03000 { 475 compatible = "arm,pl011", "arm,primecell"; 476 reg = <0x0 0xfdf03000 0x0 0x1000>; 477 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 479 <&crg_ctrl HI3660_PCLK>; 480 clock-names = "uartclk", "apb_pclk"; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 483 status = "disabled"; 484 }; 485 486 uart3: serial@ffd74000 { 487 compatible = "arm,pl011", "arm,primecell"; 488 reg = <0x0 0xffd74000 0x0 0x1000>; 489 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 491 <&crg_ctrl HI3660_PCLK>; 492 clock-names = "uartclk", "apb_pclk"; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 495 status = "disabled"; 496 }; 497 498 uart4: serial@fdf01000 { 499 compatible = "arm,pl011", "arm,primecell"; 500 reg = <0x0 0xfdf01000 0x0 0x1000>; 501 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 503 <&crg_ctrl HI3660_CLK_GATE_UART4>; 504 clock-names = "uartclk", "apb_pclk"; 505 pinctrl-names = "default"; 506 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 507 status = "disabled"; 508 }; 509 510 uart5: serial@fdf05000 { 511 compatible = "arm,pl011", "arm,primecell"; 512 reg = <0x0 0xfdf05000 0x0 0x1000>; 513 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 515 <&crg_ctrl HI3660_CLK_GATE_UART5>; 516 clock-names = "uartclk", "apb_pclk"; 517 pinctrl-names = "default"; 518 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 519 status = "disabled"; 520 }; 521 522 uart6: serial@fff32000 { 523 compatible = "arm,pl011", "arm,primecell"; 524 reg = <0x0 0xfff32000 0x0 0x1000>; 525 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&crg_ctrl HI3660_CLK_UART6>, 527 <&crg_ctrl HI3660_PCLK>; 528 clock-names = "uartclk", "apb_pclk"; 529 pinctrl-names = "default"; 530 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 531 status = "disabled"; 532 }; 533 534 dma0: dma@fdf30000 { 535 compatible = "hisilicon,k3-dma-1.0"; 536 reg = <0x0 0xfdf30000 0x0 0x1000>; 537 #dma-cells = <1>; 538 dma-channels = <16>; 539 dma-requests = <32>; 540 dma-min-chan = <1>; 541 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; 543 dma-no-cci; 544 dma-type = "hi3660_dma"; 545 }; 546 547 rtc0: rtc@fff04000 { 548 compatible = "arm,pl031", "arm,primecell"; 549 reg = <0x0 0Xfff04000 0x0 0x1000>; 550 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&crg_ctrl HI3660_PCLK>; 552 clock-names = "apb_pclk"; 553 }; 554 555 gpio0: gpio@e8a0b000 { 556 compatible = "arm,pl061", "arm,primecell"; 557 reg = <0 0xe8a0b000 0 0x1000>; 558 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 559 gpio-controller; 560 #gpio-cells = <2>; 561 gpio-ranges = <&pmx0 1 0 7>; 562 interrupt-controller; 563 #interrupt-cells = <2>; 564 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 565 clock-names = "apb_pclk"; 566 }; 567 568 gpio1: gpio@e8a0c000 { 569 compatible = "arm,pl061", "arm,primecell"; 570 reg = <0 0xe8a0c000 0 0x1000>; 571 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 572 gpio-controller; 573 #gpio-cells = <2>; 574 gpio-ranges = <&pmx0 1 7 7>; 575 interrupt-controller; 576 #interrupt-cells = <2>; 577 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 578 clock-names = "apb_pclk"; 579 }; 580 581 gpio2: gpio@e8a0d000 { 582 compatible = "arm,pl061", "arm,primecell"; 583 reg = <0 0xe8a0d000 0 0x1000>; 584 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 585 gpio-controller; 586 #gpio-cells = <2>; 587 gpio-ranges = <&pmx0 0 14 8>; 588 interrupt-controller; 589 #interrupt-cells = <2>; 590 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 591 clock-names = "apb_pclk"; 592 }; 593 594 gpio3: gpio@e8a0e000 { 595 compatible = "arm,pl061", "arm,primecell"; 596 reg = <0 0xe8a0e000 0 0x1000>; 597 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 598 gpio-controller; 599 #gpio-cells = <2>; 600 gpio-ranges = <&pmx0 0 22 8>; 601 interrupt-controller; 602 #interrupt-cells = <2>; 603 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 604 clock-names = "apb_pclk"; 605 }; 606 607 gpio4: gpio@e8a0f000 { 608 compatible = "arm,pl061", "arm,primecell"; 609 reg = <0 0xe8a0f000 0 0x1000>; 610 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 611 gpio-controller; 612 #gpio-cells = <2>; 613 gpio-ranges = <&pmx0 0 30 8>; 614 interrupt-controller; 615 #interrupt-cells = <2>; 616 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 617 clock-names = "apb_pclk"; 618 }; 619 620 gpio5: gpio@e8a10000 { 621 compatible = "arm,pl061", "arm,primecell"; 622 reg = <0 0xe8a10000 0 0x1000>; 623 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 624 gpio-controller; 625 #gpio-cells = <2>; 626 gpio-ranges = <&pmx0 0 38 8>; 627 interrupt-controller; 628 #interrupt-cells = <2>; 629 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 630 clock-names = "apb_pclk"; 631 }; 632 633 gpio6: gpio@e8a11000 { 634 compatible = "arm,pl061", "arm,primecell"; 635 reg = <0 0xe8a11000 0 0x1000>; 636 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 637 gpio-controller; 638 #gpio-cells = <2>; 639 gpio-ranges = <&pmx0 0 46 8>; 640 interrupt-controller; 641 #interrupt-cells = <2>; 642 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 643 clock-names = "apb_pclk"; 644 }; 645 646 gpio7: gpio@e8a12000 { 647 compatible = "arm,pl061", "arm,primecell"; 648 reg = <0 0xe8a12000 0 0x1000>; 649 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 650 gpio-controller; 651 #gpio-cells = <2>; 652 gpio-ranges = <&pmx0 0 54 8>; 653 interrupt-controller; 654 #interrupt-cells = <2>; 655 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 656 clock-names = "apb_pclk"; 657 }; 658 659 gpio8: gpio@e8a13000 { 660 compatible = "arm,pl061", "arm,primecell"; 661 reg = <0 0xe8a13000 0 0x1000>; 662 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 663 gpio-controller; 664 #gpio-cells = <2>; 665 gpio-ranges = <&pmx0 0 62 8>; 666 interrupt-controller; 667 #interrupt-cells = <2>; 668 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 669 clock-names = "apb_pclk"; 670 }; 671 672 gpio9: gpio@e8a14000 { 673 compatible = "arm,pl061", "arm,primecell"; 674 reg = <0 0xe8a14000 0 0x1000>; 675 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 676 gpio-controller; 677 #gpio-cells = <2>; 678 gpio-ranges = <&pmx0 0 70 8>; 679 interrupt-controller; 680 #interrupt-cells = <2>; 681 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 682 clock-names = "apb_pclk"; 683 }; 684 685 gpio10: gpio@e8a15000 { 686 compatible = "arm,pl061", "arm,primecell"; 687 reg = <0 0xe8a15000 0 0x1000>; 688 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 689 gpio-controller; 690 #gpio-cells = <2>; 691 gpio-ranges = <&pmx0 0 78 8>; 692 interrupt-controller; 693 #interrupt-cells = <2>; 694 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 695 clock-names = "apb_pclk"; 696 }; 697 698 gpio11: gpio@e8a16000 { 699 compatible = "arm,pl061", "arm,primecell"; 700 reg = <0 0xe8a16000 0 0x1000>; 701 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 702 gpio-controller; 703 #gpio-cells = <2>; 704 gpio-ranges = <&pmx0 0 86 8>; 705 interrupt-controller; 706 #interrupt-cells = <2>; 707 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 708 clock-names = "apb_pclk"; 709 }; 710 711 gpio12: gpio@e8a17000 { 712 compatible = "arm,pl061", "arm,primecell"; 713 reg = <0 0xe8a17000 0 0x1000>; 714 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 715 gpio-controller; 716 #gpio-cells = <2>; 717 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 718 interrupt-controller; 719 #interrupt-cells = <2>; 720 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 721 clock-names = "apb_pclk"; 722 }; 723 724 gpio13: gpio@e8a18000 { 725 compatible = "arm,pl061", "arm,primecell"; 726 reg = <0 0xe8a18000 0 0x1000>; 727 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 728 gpio-controller; 729 #gpio-cells = <2>; 730 gpio-ranges = <&pmx0 0 102 8>; 731 interrupt-controller; 732 #interrupt-cells = <2>; 733 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 734 clock-names = "apb_pclk"; 735 }; 736 737 gpio14: gpio@e8a19000 { 738 compatible = "arm,pl061", "arm,primecell"; 739 reg = <0 0xe8a19000 0 0x1000>; 740 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 741 gpio-controller; 742 #gpio-cells = <2>; 743 gpio-ranges = <&pmx0 0 110 8>; 744 interrupt-controller; 745 #interrupt-cells = <2>; 746 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 747 clock-names = "apb_pclk"; 748 }; 749 750 gpio15: gpio@e8a1a000 { 751 compatible = "arm,pl061", "arm,primecell"; 752 reg = <0 0xe8a1a000 0 0x1000>; 753 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 754 gpio-controller; 755 #gpio-cells = <2>; 756 gpio-ranges = <&pmx0 0 118 6>; 757 interrupt-controller; 758 #interrupt-cells = <2>; 759 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 760 clock-names = "apb_pclk"; 761 }; 762 763 gpio16: gpio@e8a1b000 { 764 compatible = "arm,pl061", "arm,primecell"; 765 reg = <0 0xe8a1b000 0 0x1000>; 766 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 767 gpio-controller; 768 #gpio-cells = <2>; 769 interrupt-controller; 770 #interrupt-cells = <2>; 771 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 772 clock-names = "apb_pclk"; 773 }; 774 775 gpio17: gpio@e8a1c000 { 776 compatible = "arm,pl061", "arm,primecell"; 777 reg = <0 0xe8a1c000 0 0x1000>; 778 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 779 gpio-controller; 780 #gpio-cells = <2>; 781 interrupt-controller; 782 #interrupt-cells = <2>; 783 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 784 clock-names = "apb_pclk"; 785 }; 786 787 gpio18: gpio@ff3b4000 { 788 compatible = "arm,pl061", "arm,primecell"; 789 reg = <0 0xff3b4000 0 0x1000>; 790 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 791 gpio-controller; 792 #gpio-cells = <2>; 793 gpio-ranges = <&pmx2 0 0 8>; 794 interrupt-controller; 795 #interrupt-cells = <2>; 796 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 797 clock-names = "apb_pclk"; 798 }; 799 800 gpio19: gpio@ff3b5000 { 801 compatible = "arm,pl061", "arm,primecell"; 802 reg = <0 0xff3b5000 0 0x1000>; 803 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 804 gpio-controller; 805 #gpio-cells = <2>; 806 gpio-ranges = <&pmx2 0 8 4>; 807 interrupt-controller; 808 #interrupt-cells = <2>; 809 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 810 clock-names = "apb_pclk"; 811 }; 812 813 gpio20: gpio@e8a1f000 { 814 compatible = "arm,pl061", "arm,primecell"; 815 reg = <0 0xe8a1f000 0 0x1000>; 816 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 817 gpio-controller; 818 #gpio-cells = <2>; 819 gpio-ranges = <&pmx1 0 0 6>; 820 interrupt-controller; 821 #interrupt-cells = <2>; 822 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 823 clock-names = "apb_pclk"; 824 }; 825 826 gpio21: gpio@e8a20000 { 827 compatible = "arm,pl061", "arm,primecell"; 828 reg = <0 0xe8a20000 0 0x1000>; 829 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 830 gpio-controller; 831 #gpio-cells = <2>; 832 interrupt-controller; 833 #interrupt-cells = <2>; 834 gpio-ranges = <&pmx3 0 0 6>; 835 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 836 clock-names = "apb_pclk"; 837 }; 838 839 gpio22: gpio@fff0b000 { 840 compatible = "arm,pl061", "arm,primecell"; 841 reg = <0 0xfff0b000 0 0x1000>; 842 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 843 gpio-controller; 844 #gpio-cells = <2>; 845 /* GPIO176 */ 846 gpio-ranges = <&pmx4 2 0 6>; 847 interrupt-controller; 848 #interrupt-cells = <2>; 849 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 850 clock-names = "apb_pclk"; 851 }; 852 853 gpio23: gpio@fff0c000 { 854 compatible = "arm,pl061", "arm,primecell"; 855 reg = <0 0xfff0c000 0 0x1000>; 856 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 857 gpio-controller; 858 #gpio-cells = <2>; 859 /* GPIO184 */ 860 gpio-ranges = <&pmx4 0 6 7>; 861 interrupt-controller; 862 #interrupt-cells = <2>; 863 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 864 clock-names = "apb_pclk"; 865 }; 866 867 gpio24: gpio@fff0d000 { 868 compatible = "arm,pl061", "arm,primecell"; 869 reg = <0 0xfff0d000 0 0x1000>; 870 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 871 gpio-controller; 872 #gpio-cells = <2>; 873 /* GPIO192 */ 874 gpio-ranges = <&pmx4 0 13 8>; 875 interrupt-controller; 876 #interrupt-cells = <2>; 877 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 878 clock-names = "apb_pclk"; 879 }; 880 881 gpio25: gpio@fff0e000 { 882 compatible = "arm,pl061", "arm,primecell"; 883 reg = <0 0xfff0e000 0 0x1000>; 884 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 885 gpio-controller; 886 #gpio-cells = <2>; 887 /* GPIO200 */ 888 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 889 interrupt-controller; 890 #interrupt-cells = <2>; 891 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 892 clock-names = "apb_pclk"; 893 }; 894 895 gpio26: gpio@fff0f000 { 896 compatible = "arm,pl061", "arm,primecell"; 897 reg = <0 0xfff0f000 0 0x1000>; 898 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 899 gpio-controller; 900 #gpio-cells = <2>; 901 /* GPIO208 */ 902 gpio-ranges = <&pmx4 0 28 8>; 903 interrupt-controller; 904 #interrupt-cells = <2>; 905 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 906 clock-names = "apb_pclk"; 907 }; 908 909 gpio27: gpio@fff10000 { 910 compatible = "arm,pl061", "arm,primecell"; 911 reg = <0 0xfff10000 0 0x1000>; 912 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 913 gpio-controller; 914 #gpio-cells = <2>; 915 /* GPIO216 */ 916 gpio-ranges = <&pmx4 0 36 6>; 917 interrupt-controller; 918 #interrupt-cells = <2>; 919 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 920 clock-names = "apb_pclk"; 921 }; 922 923 gpio28: gpio@fff1d000 { 924 compatible = "arm,pl061", "arm,primecell"; 925 reg = <0 0xfff1d000 0 0x1000>; 926 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 927 gpio-controller; 928 #gpio-cells = <2>; 929 interrupt-controller; 930 #interrupt-cells = <2>; 931 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 932 clock-names = "apb_pclk"; 933 }; 934 935 spi2: spi@ffd68000 { 936 compatible = "arm,pl022", "arm,primecell"; 937 reg = <0x0 0xffd68000 0x0 0x1000>; 938 #address-cells = <1>; 939 #size-cells = <0>; 940 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 942 clock-names = "apb_pclk"; 943 pinctrl-names = "default"; 944 pinctrl-0 = <&spi2_pmx_func>; 945 num-cs = <1>; 946 cs-gpios = <&gpio27 2 0>; 947 status = "disabled"; 948 }; 949 950 spi3: spi@ff3b3000 { 951 compatible = "arm,pl022", "arm,primecell"; 952 reg = <0x0 0xff3b3000 0x0 0x1000>; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 957 clock-names = "apb_pclk"; 958 pinctrl-names = "default"; 959 pinctrl-0 = <&spi3_pmx_func>; 960 num-cs = <1>; 961 cs-gpios = <&gpio18 5 0>; 962 status = "disabled"; 963 }; 964 965 pcie@f4000000 { 966 compatible = "hisilicon,kirin960-pcie"; 967 reg = <0x0 0xf4000000 0x0 0x1000>, 968 <0x0 0xff3fe000 0x0 0x1000>, 969 <0x0 0xf3f20000 0x0 0x40000>, 970 <0x0 0xf5000000 0x0 0x2000>; 971 reg-names = "dbi", "apb", "phy", "config"; 972 bus-range = <0x0 0x1>; 973 #address-cells = <3>; 974 #size-cells = <2>; 975 device_type = "pci"; 976 ranges = <0x02000000 0x0 0x00000000 977 0x0 0xf6000000 978 0x0 0x02000000>; 979 num-lanes = <1>; 980 #interrupt-cells = <1>; 981 interrupts = <0 283 4>; 982 interrupt-names = "msi"; 983 interrupt-map-mask = <0xf800 0 0 7>; 984 interrupt-map = <0x0 0 0 1 985 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 986 <0x0 0 0 2 987 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 988 <0x0 0 0 3 989 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 990 <0x0 0 0 4 991 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 993 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 994 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 995 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 996 <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 997 clock-names = "pcie_phy_ref", "pcie_aux", 998 "pcie_apb_phy", "pcie_apb_sys", 999 "pcie_aclk"; 1000 reset-gpios = <&gpio11 1 0 >; 1001 }; 1002 1003 /* UFS */ 1004 ufs: ufs@ff3b0000 { 1005 compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; 1006 /* 0: HCI standard */ 1007 /* 1: UFS SYS CTRL */ 1008 reg = <0x0 0xff3b0000 0x0 0x1000>, 1009 <0x0 0xff3b1000 0x0 0x1000>; 1010 interrupt-parent = <&gic>; 1011 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, 1013 <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; 1014 clock-names = "ref_clk", "phy_clk"; 1015 freq-table-hz = <0 0>, <0 0>; 1016 /* offset: 0x84; bit: 12 */ 1017 resets = <&crg_rst 0x84 12>; 1018 reset-names = "rst"; 1019 }; 1020 1021 /* SD */ 1022 dwmmc1: dwmmc1@ff37f000 { 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 cd-inverted; 1026 compatible = "hisilicon,hi3660-dw-mshc"; 1027 bus-width = <0x4>; 1028 disable-wp; 1029 cap-sd-highspeed; 1030 supports-highspeed; 1031 card-detect-delay = <200>; 1032 reg = <0x0 0xff37f000 0x0 0x1000>; 1033 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1034 clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 1035 <&crg_ctrl HI3660_HCLK_GATE_SD>; 1036 clock-names = "ciu", "biu"; 1037 clock-frequency = <3200000>; 1038 resets = <&crg_rst 0x94 18>; 1039 reset-names = "reset"; 1040 cd-gpios = <&gpio25 3 0>; 1041 hisilicon,peripheral-syscon = <&sctrl>; 1042 pinctrl-names = "default"; 1043 pinctrl-0 = <&sd_pmx_func 1044 &sd_clk_cfg_func 1045 &sd_cfg_func>; 1046 sd-uhs-sdr12; 1047 sd-uhs-sdr25; 1048 sd-uhs-sdr50; 1049 sd-uhs-sdr104; 1050 status = "disabled"; 1051 1052 slot@0 { 1053 reg = <0x0>; 1054 bus-width = <4>; 1055 disable-wp; 1056 }; 1057 }; 1058 1059 /* SDIO */ 1060 dwmmc2: dwmmc2@ff3ff000 { 1061 compatible = "hisilicon,hi3660-dw-mshc"; 1062 reg = <0x0 0xff3ff000 0x0 0x1000>; 1063 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 1065 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 1066 clock-names = "ciu", "biu"; 1067 resets = <&crg_rst 0x94 20>; 1068 reset-names = "reset"; 1069 card-detect-delay = <200>; 1070 supports-highspeed; 1071 keep-power-in-suspend; 1072 pinctrl-names = "default"; 1073 pinctrl-0 = <&sdio_pmx_func 1074 &sdio_clk_cfg_func 1075 &sdio_cfg_func>; 1076 status = "disabled"; 1077 }; 1078 1079 watchdog0: watchdog@e8a06000 { 1080 compatible = "arm,sp805-wdt", "arm,primecell"; 1081 reg = <0x0 0xe8a06000 0x0 0x1000>; 1082 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&crg_ctrl HI3660_OSC32K>; 1084 clock-names = "apb_pclk"; 1085 }; 1086 1087 watchdog1: watchdog@e8a07000 { 1088 compatible = "arm,sp805-wdt", "arm,primecell"; 1089 reg = <0x0 0xe8a07000 0x0 0x1000>; 1090 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1091 clocks = <&crg_ctrl HI3660_OSC32K>; 1092 clock-names = "apb_pclk"; 1093 }; 1094 1095 tsensor: tsensor@fff30000 { 1096 compatible = "hisilicon,hi3660-tsensor"; 1097 reg = <0x0 0xfff30000 0x0 0x1000>; 1098 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1099 #thermal-sensor-cells = <1>; 1100 }; 1101 1102 thermal-zones { 1103 1104 cls0: cls0 { 1105 polling-delay = <1000>; 1106 polling-delay-passive = <100>; 1107 sustainable-power = <4500>; 1108 1109 /* sensor ID */ 1110 thermal-sensors = <&tsensor 1>; 1111 1112 trips { 1113 threshold: trip-point@0 { 1114 temperature = <65000>; 1115 hysteresis = <1000>; 1116 type = "passive"; 1117 }; 1118 1119 target: trip-point@1 { 1120 temperature = <75000>; 1121 hysteresis = <1000>; 1122 type = "passive"; 1123 }; 1124 }; 1125 1126 cooling-maps { 1127 map0 { 1128 trip = <&target>; 1129 contribution = <1024>; 1130 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1131 }; 1132 map1 { 1133 trip = <&target>; 1134 contribution = <512>; 1135 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1136 }; 1137 }; 1138 }; 1139 }; 1140 }; 1141}; 1142