1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/pinctrl/pads-imx8qxp.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 mmc0 = &usdhc1; 21 mmc1 = &usdhc2; 22 mmc2 = &usdhc3; 23 serial0 = &adma_lpuart0; 24 mu1 = &lsio_mu1; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 /* We have 1 clusters with 4 Cortex-A35 cores */ 32 A35_0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a35"; 35 reg = <0x0 0x0>; 36 enable-method = "psci"; 37 next-level-cache = <&A35_L2>; 38 clocks = <&clk IMX_A35_CLK>; 39 operating-points-v2 = <&a35_opp_table>; 40 #cooling-cells = <2>; 41 }; 42 43 A35_1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a35"; 46 reg = <0x0 0x1>; 47 enable-method = "psci"; 48 next-level-cache = <&A35_L2>; 49 clocks = <&clk IMX_A35_CLK>; 50 operating-points-v2 = <&a35_opp_table>; 51 #cooling-cells = <2>; 52 }; 53 54 A35_2: cpu@2 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x2>; 58 enable-method = "psci"; 59 next-level-cache = <&A35_L2>; 60 clocks = <&clk IMX_A35_CLK>; 61 operating-points-v2 = <&a35_opp_table>; 62 #cooling-cells = <2>; 63 }; 64 65 A35_3: cpu@3 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a35"; 68 reg = <0x0 0x3>; 69 enable-method = "psci"; 70 next-level-cache = <&A35_L2>; 71 clocks = <&clk IMX_A35_CLK>; 72 operating-points-v2 = <&a35_opp_table>; 73 #cooling-cells = <2>; 74 }; 75 76 A35_L2: l2-cache0 { 77 compatible = "cache"; 78 }; 79 }; 80 81 a35_opp_table: opp-table { 82 compatible = "operating-points-v2"; 83 opp-shared; 84 85 opp-900000000 { 86 opp-hz = /bits/ 64 <900000000>; 87 opp-microvolt = <1000000>; 88 clock-latency-ns = <150000>; 89 }; 90 91 opp-1200000000 { 92 opp-hz = /bits/ 64 <1200000000>; 93 opp-microvolt = <1100000>; 94 clock-latency-ns = <150000>; 95 opp-suspend; 96 }; 97 }; 98 99 gic: interrupt-controller@51a00000 { 100 compatible = "arm,gic-v3"; 101 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 102 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 103 #interrupt-cells = <3>; 104 interrupt-controller; 105 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 106 }; 107 108 pmu { 109 compatible = "arm,armv8-pmuv3"; 110 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 111 }; 112 113 psci { 114 compatible = "arm,psci-1.0"; 115 method = "smc"; 116 }; 117 118 scu { 119 compatible = "fsl,imx-scu"; 120 mbox-names = "tx0", "tx1", "tx2", "tx3", 121 "rx0", "rx1", "rx2", "rx3", 122 "gip3"; 123 mboxes = <&lsio_mu1 0 0 124 &lsio_mu1 0 1 125 &lsio_mu1 0 2 126 &lsio_mu1 0 3 127 &lsio_mu1 1 0 128 &lsio_mu1 1 1 129 &lsio_mu1 1 2 130 &lsio_mu1 1 3 131 &lsio_mu1 3 3>; 132 133 clk: clock-controller { 134 compatible = "fsl,imx8qxp-clk"; 135 #clock-cells = <1>; 136 clocks = <&xtal32k &xtal24m>; 137 clock-names = "xtal_32KHz", "xtal_24Mhz"; 138 }; 139 140 iomuxc: pinctrl { 141 compatible = "fsl,imx8qxp-iomuxc"; 142 }; 143 144 pd: imx8qx-pd { 145 compatible = "fsl,imx8qxp-scu-pd"; 146 #power-domain-cells = <1>; 147 }; 148 149 rtc: rtc { 150 compatible = "fsl,imx8qxp-sc-rtc"; 151 }; 152 }; 153 154 timer { 155 compatible = "arm,armv8-timer"; 156 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 157 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 158 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 159 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 160 }; 161 162 xtal32k: clock-xtal32k { 163 compatible = "fixed-clock"; 164 #clock-cells = <0>; 165 clock-frequency = <32768>; 166 clock-output-names = "xtal_32KHz"; 167 }; 168 169 xtal24m: clock-xtal24m { 170 compatible = "fixed-clock"; 171 #clock-cells = <0>; 172 clock-frequency = <24000000>; 173 clock-output-names = "xtal_24MHz"; 174 }; 175 176 adma_subsys: bus@59000000 { 177 compatible = "simple-bus"; 178 #address-cells = <1>; 179 #size-cells = <1>; 180 ranges = <0x59000000 0x0 0x59000000 0x2000000>; 181 182 adma_lpcg: clock-controller@59000000 { 183 compatible = "fsl,imx8qxp-lpcg-adma"; 184 reg = <0x59000000 0x2000000>; 185 #clock-cells = <1>; 186 }; 187 188 adma_lpuart0: serial@5a060000 { 189 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 190 reg = <0x5a060000 0x1000>; 191 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 192 interrupt-parent = <&gic>; 193 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; 194 clock-names = "ipg"; 195 power-domains = <&pd IMX_SC_R_UART_0>; 196 status = "disabled"; 197 }; 198 199 adma_lpuart1: serial@5a070000 { 200 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 201 reg = <0x5a070000 0x1000>; 202 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 203 interrupt-parent = <&gic>; 204 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; 205 clock-names = "ipg"; 206 power-domains = <&pd IMX_SC_R_UART_1>; 207 status = "disabled"; 208 }; 209 210 adma_lpuart2: serial@5a080000 { 211 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 212 reg = <0x5a080000 0x1000>; 213 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 214 interrupt-parent = <&gic>; 215 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; 216 clock-names = "ipg"; 217 power-domains = <&pd IMX_SC_R_UART_2>; 218 status = "disabled"; 219 }; 220 221 adma_lpuart3: serial@5a090000 { 222 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 223 reg = <0x5a090000 0x1000>; 224 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 225 interrupt-parent = <&gic>; 226 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; 227 clock-names = "ipg"; 228 power-domains = <&pd IMX_SC_R_UART_3>; 229 status = "disabled"; 230 }; 231 232 adma_i2c0: i2c@5a800000 { 233 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 234 reg = <0x5a800000 0x4000>; 235 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 236 interrupt-parent = <&gic>; 237 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; 238 clock-names = "per"; 239 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; 240 assigned-clock-rates = <24000000>; 241 power-domains = <&pd IMX_SC_R_I2C_0>; 242 status = "disabled"; 243 }; 244 245 adma_i2c1: i2c@5a810000 { 246 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 247 reg = <0x5a810000 0x4000>; 248 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 249 interrupt-parent = <&gic>; 250 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; 251 clock-names = "per"; 252 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; 253 assigned-clock-rates = <24000000>; 254 power-domains = <&pd IMX_SC_R_I2C_1>; 255 status = "disabled"; 256 }; 257 258 adma_i2c2: i2c@5a820000 { 259 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 260 reg = <0x5a820000 0x4000>; 261 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 262 interrupt-parent = <&gic>; 263 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; 264 clock-names = "per"; 265 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; 266 assigned-clock-rates = <24000000>; 267 power-domains = <&pd IMX_SC_R_I2C_2>; 268 status = "disabled"; 269 }; 270 271 adma_i2c3: i2c@5a830000 { 272 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 273 reg = <0x5a830000 0x4000>; 274 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 275 interrupt-parent = <&gic>; 276 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; 277 clock-names = "per"; 278 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; 279 assigned-clock-rates = <24000000>; 280 power-domains = <&pd IMX_SC_R_I2C_3>; 281 status = "disabled"; 282 }; 283 }; 284 285 conn_subsys: bus@5b000000 { 286 compatible = "simple-bus"; 287 #address-cells = <1>; 288 #size-cells = <1>; 289 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 290 291 conn_lpcg: clock-controller@5b200000 { 292 compatible = "fsl,imx8qxp-lpcg-conn"; 293 reg = <0x5b200000 0xb0000>; 294 #clock-cells = <1>; 295 }; 296 297 usdhc1: mmc@5b010000 { 298 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 299 interrupt-parent = <&gic>; 300 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 301 reg = <0x5b010000 0x10000>; 302 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, 303 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, 304 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; 305 clock-names = "ipg", "per", "ahb"; 306 assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; 307 assigned-clock-rates = <200000000>; 308 power-domains = <&pd IMX_SC_R_SDHC_0>; 309 status = "disabled"; 310 }; 311 312 usdhc2: mmc@5b020000 { 313 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 314 interrupt-parent = <&gic>; 315 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 316 reg = <0x5b020000 0x10000>; 317 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, 318 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, 319 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; 320 clock-names = "ipg", "per", "ahb"; 321 assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; 322 assigned-clock-rates = <200000000>; 323 power-domains = <&pd IMX_SC_R_SDHC_1>; 324 fsl,tuning-start-tap = <20>; 325 fsl,tuning-step= <2>; 326 status = "disabled"; 327 }; 328 329 usdhc3: mmc@5b030000 { 330 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 331 interrupt-parent = <&gic>; 332 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 333 reg = <0x5b030000 0x10000>; 334 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, 335 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, 336 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; 337 clock-names = "ipg", "per", "ahb"; 338 assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; 339 assigned-clock-rates = <200000000>; 340 power-domains = <&pd IMX_SC_R_SDHC_2>; 341 status = "disabled"; 342 }; 343 344 fec1: ethernet@5b040000 { 345 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 346 reg = <0x5b040000 0x10000>; 347 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, 352 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, 353 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, 354 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; 355 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 356 fsl,num-tx-queues=<3>; 357 fsl,num-rx-queues=<3>; 358 power-domains = <&pd IMX_SC_R_ENET_0>; 359 status = "disabled"; 360 }; 361 362 fec2: ethernet@5b050000 { 363 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 364 reg = <0x5b050000 0x10000>; 365 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, 370 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, 371 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, 372 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; 373 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 374 fsl,num-tx-queues=<3>; 375 fsl,num-rx-queues=<3>; 376 power-domains = <&pd IMX_SC_R_ENET_1>; 377 status = "disabled"; 378 }; 379 }; 380 381 lsio_subsys: bus@5d000000 { 382 compatible = "simple-bus"; 383 #address-cells = <1>; 384 #size-cells = <1>; 385 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; 386 387 lsio_lpcg: clock-controller@5d400000 { 388 compatible = "fsl,imx8qxp-lpcg-lsio"; 389 reg = <0x5d400000 0x400000>; 390 #clock-cells = <1>; 391 }; 392 393 lsio_mu0: mailbox@5d1b0000 { 394 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 395 reg = <0x5d1b0000 0x10000>; 396 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 397 #mbox-cells = <2>; 398 status = "disabled"; 399 }; 400 401 lsio_mu1: mailbox@5d1c0000 { 402 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 403 reg = <0x5d1c0000 0x10000>; 404 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 405 #mbox-cells = <2>; 406 }; 407 408 lsio_mu2: mailbox@5d1d0000 { 409 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 410 reg = <0x5d1d0000 0x10000>; 411 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 412 #mbox-cells = <2>; 413 status = "disabled"; 414 }; 415 416 lsio_mu3: mailbox@5d1e0000 { 417 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 418 reg = <0x5d1e0000 0x10000>; 419 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 420 #mbox-cells = <2>; 421 status = "disabled"; 422 }; 423 424 lsio_mu4: mailbox@5d1f0000 { 425 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 426 reg = <0x5d1f0000 0x10000>; 427 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 428 #mbox-cells = <2>; 429 status = "disabled"; 430 }; 431 432 lsio_gpio0: gpio@5d080000 { 433 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 434 reg = <0x5d080000 0x10000>; 435 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 436 gpio-controller; 437 #gpio-cells = <2>; 438 interrupt-controller; 439 #interrupt-cells = <2>; 440 power-domains = <&pd IMX_SC_R_GPIO_0>; 441 }; 442 443 lsio_gpio1: gpio@5d090000 { 444 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 445 reg = <0x5d090000 0x10000>; 446 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 447 gpio-controller; 448 #gpio-cells = <2>; 449 interrupt-controller; 450 #interrupt-cells = <2>; 451 power-domains = <&pd IMX_SC_R_GPIO_1>; 452 }; 453 454 lsio_gpio2: gpio@5d0a0000 { 455 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 456 reg = <0x5d0a0000 0x10000>; 457 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 458 gpio-controller; 459 #gpio-cells = <2>; 460 interrupt-controller; 461 #interrupt-cells = <2>; 462 power-domains = <&pd IMX_SC_R_GPIO_2>; 463 }; 464 465 lsio_gpio3: gpio@5d0b0000 { 466 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 467 reg = <0x5d0b0000 0x10000>; 468 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 469 gpio-controller; 470 #gpio-cells = <2>; 471 interrupt-controller; 472 #interrupt-cells = <2>; 473 power-domains = <&pd IMX_SC_R_GPIO_3>; 474 }; 475 476 lsio_gpio4: gpio@5d0c0000 { 477 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 478 reg = <0x5d0c0000 0x10000>; 479 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 480 gpio-controller; 481 #gpio-cells = <2>; 482 interrupt-controller; 483 #interrupt-cells = <2>; 484 power-domains = <&pd IMX_SC_R_GPIO_4>; 485 }; 486 487 lsio_gpio5: gpio@5d0d0000 { 488 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 489 reg = <0x5d0d0000 0x10000>; 490 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 491 gpio-controller; 492 #gpio-cells = <2>; 493 interrupt-controller; 494 #interrupt-cells = <2>; 495 power-domains = <&pd IMX_SC_R_GPIO_5>; 496 }; 497 498 lsio_gpio6: gpio@5d0e0000 { 499 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 500 reg = <0x5d0e0000 0x10000>; 501 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 502 gpio-controller; 503 #gpio-cells = <2>; 504 interrupt-controller; 505 #interrupt-cells = <2>; 506 power-domains = <&pd IMX_SC_R_GPIO_6>; 507 }; 508 509 lsio_gpio7: gpio@5d0f0000 { 510 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 511 reg = <0x5d0f0000 0x10000>; 512 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 513 gpio-controller; 514 #gpio-cells = <2>; 515 interrupt-controller; 516 #interrupt-cells = <2>; 517 power-domains = <&pd IMX_SC_R_GPIO_7>; 518 }; 519 }; 520 521 watchdog { 522 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 523 timeout-sec = <60>; 524 }; 525}; 526